JP2012168719A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system that can reduce current consumption.SOLUTION: The memory system includes a plurality of data buses provided between a NAND type flash memory and an input/output part and between the NAND type flash memory and an input/output buffer part, a switch that selects a desired data bus based on an input selecting signal, and a control part that, when data is written in the NAND type flash memory at least from the input/output buffer part by controlling the NAND type flash memory, the input/output part, and the switch, outputs the selecting signal, which connects between the NAND type flash memory and the input/output buffer part through the selected data bus and dose not connect between the NAND type flash memory and the input/output buffer part through the rest of the data buses, to the switch.

Description

  Embodiments described herein relate generally to a memory system, for example, a semiconductor device including a NAND flash memory.

  As a semiconductor storage device in which a plurality of types of memories are integrated on one chip, for example, there is a semiconductor storage device in which a NAND flash memory (storage unit) and an SRAM (Static Random Access Memory) are integrated on a single chip.

JP 2003-0667260 A

  Embodiments provide a memory system capable of reducing current consumption.

  According to the memory system of the present embodiment, the NAND flash memory includes an ECC unit that performs ECC processing on data input to the NAND flash memory or data output from the NAND flash memory. An input / output unit that controls input / output of data between the NAND flash memory and the outside; an data output from the input / output unit; or an input / output buffer unit that holds data input to the input / output unit; Based on a plurality of data buses provided between the NAND flash memory and the input / output unit, and between the NAND flash memory and the input / output buffer unit, and a selection signal input, a desired A switch for selecting the data bus; the NAND flash memory; the input / output unit; and the switch. When writing data from the input / output buffer unit to the NAND type flash memory or reading data from the NAND type flash memory to the input / output buffer unit via the selected data bus The selection signal is connected between the NAND flash memory and the input / output buffer unit and not connected between the NAND flash memory and the input / output buffer unit via the remaining data bus. And a control unit that outputs the data.

1 is a block diagram showing a memory system according to a first embodiment. A circuit diagram showing a memory cell array of a 1st embodiment. The block diagram which shows the switch of 1st Embodiment. A circuit diagram showing buffer circuit BFA0-1 of a 1st embodiment. FIG. 3 is a circuit diagram illustrating a circuit that generates a signal to be input to the buffer circuit A according to the first embodiment. A circuit diagram showing buffer circuit B of a 1st embodiment.

(First embodiment)
Next, a first embodiment will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[Memory system configuration]
The memory system according to the first embodiment will be described with reference to the block diagram of FIG.

  As shown in FIG. 1, the memory system 100 includes a NAND flash memory 10, an input / output unit 20, and a control unit 30. For example, in the memory system 100, the NAND flash memory 10, the input / output unit 20, and the control unit 30 are formed on the same semiconductor substrate and integrated on one chip.

<NAND flash memory>
First, the NAND flash memory 10 will be described with reference to the circuit diagrams of FIGS.

  The NAND flash memory 10 functions as a main storage unit of the memory system 100. As shown in FIG. 1, the NAND flash memory 10 includes a memory cell array 11, a row decoder 12, a sense amplifier and page buffer 13, a column decoder 14, a voltage generation circuit 15, a sequencer 16, an input buffer circuit 17, and an oscillator 18. 19 is provided.

<< Memory cell array >>
As shown in FIG. 2, the memory cell array 11 includes blocks BLK0 to BLKs including a plurality of nonvolatile memory cells MT (s is a natural number). Each of the blocks BLK0 to BLKs includes a plurality of NAND strings NS. The NAND string NS includes a plurality of nonvolatile memory cells MT0 to MTn (n is a natural number) and select transistors ST1 and ST2. As shown in FIG. 2, (n + 1) memory cells are arranged between the select transistors ST1 and ST2 such that their current paths are connected in series. The drain region on one end side (memory cell MTn) of the memory cells MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side (memory cell MT0) is connected to the drain region of the select transistor ST2. ing. The adjacent memory cells MT share the source and drain.

  The memory cell MT can hold binary or higher data. The structure of the memory cell MT is formed, for example, by a floating gate (charge conductive layer) formed on a p-type semiconductor substrate via a gate insulating film and an inter-gate insulating film interposed on the floating gate. The structure includes a control gate. The structure of the memory cell MT includes a charge storage layer (for example, an insulating film) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and an insulating film (a dielectric constant higher than that of the charge storage layer). MONOS structure having a high insulating film) and a control gate formed on the insulating film.

  The control gate of the memory cell MT is electrically connected to the word line WL, the drain is electrically connected to the bit line BL, and the source is electrically connected to the source line.

  The control gates of the memory cells MT in the same row are commonly connected to any of the word lines WL0 to WLn, and the gate electrodes of the select transistors ST1 and ST2 of the memory cells MT in the same row are connected to the select gate lines SGD and SGS, respectively. Commonly connected. That is, the select gate lines SGS and SGD are arranged in parallel adjacent to both ends of the word line WL0 and the word line WLn so as to sandwich the plurality of word lines WL0 to WLn.

  Further, the drains of the select transistors ST1 in the same column in the memory cell array 11 are commonly connected to any of the bit lines BL0 to BLj (j is a natural number). The sources of the selection transistors ST2 are commonly connected to the source line SL.

  Further, data is written or read in a plurality of memory cells MT connected to the same word line WL, and this unit is called a page. Further, data is erased collectively from the plurality of memory cells MT in units of blocks BLK.

  The memory cell array 11 includes a first area where normal data is stored, and a second area where data is stored as a spare area of the first area. For example, parity for correcting an error is stored in the second area.

<< Sense amplifier and page buffer >>
Returning to FIG. 1, the description will be continued. The sense amplifier and page buffer 13 is a buffer memory capable of holding page size data, and functions as a primary data cache and a secondary data cache in the NAND flash memory 10, respectively.

  At the time of reading data, the sense amplifier senses and amplifies data read from the memory cell array 11, temporarily holds it, and transfers it to the page buffer. At the time of writing, the data transferred from the page buffer is transferred to the bit line BL, and the data program is executed.

  The page buffer is connected to the input / output unit 20 via a NAND data bus. When data is read, the data transferred from the sense amplifier is output to the input / output unit 20. Further, at the time of writing, data input from the input / output unit 20 is temporarily held and transferred to the sense amplifier.

  The sense amplifier and page buffer 13 includes a latch circuit provided for each bit line BL, for example, and can hold data for one page. Therefore, a part of the area is used for holding main data, and the rest is used for holding ECC data such as parity. For example, the latch circuit only needs to be for one page.

<< Row decoder and column decoder >>
The row decoder 12 selects any page (that is, the word line WL) in the memory cell array 11. The column decoder 14 selects any column (that is, the bit line BL) in the memory cell array 11.

<< Voltage generation circuit >>
The voltage generation circuit 15 generates a voltage necessary for data programming, reading, and erasing by boosting or stepping down a voltage applied from the outside. The generated voltage is supplied to the row decoder 12, for example. The voltage generated by the voltage generation circuit 15 is applied to the word line WL.

<< Sequencer >>
The sequencer 16 governs the overall operation of the NAND flash memory 10. That is, when an instruction (NAND I / F Command) is received from the control unit 30, a sequence for executing data programming, reading, and erasing is executed in response thereto. Then, according to this sequence, the operations of the voltage generation circuit 15, the sense amplifier, the page buffer 13, and the like are controlled.

<< Input / output buffer circuit >>
The input / output buffer circuit 17 has a function as a buffer that temporarily holds data input from the outside via an access controller 24 described later or data read from the NAND flash memory 10.

<< Oscillator >>
The oscillator 18 generates an internal clock ICLK. That is, it functions as a clock generator. The oscillator 18 supplies the generated internal clock ICLK to the sequencer 16. The sequencer 16 operates in synchronization with the internal clock ICLK.

  The oscillator 19 generates an internal clock ACLK. That is, it functions as a clock generator. The oscillator 19 supplies the generated internal clock ACLK to the control unit 30 and the input / output unit 20. The internal clock ACLK is a reference clock for the operation of the control unit 30 and the input / output unit 40.

<Input / output unit>
Next, the input / output unit 20 will be described with reference to FIG. The input / output unit 20 includes a buffer unit 21, a burst buffer 22, a user interface 23, an access controller 24, and an ECC unit 25.

  In the memory system 100 according to the present embodiment, the NAND flash memory 10 functions as a main storage unit, and the input / output unit 20 controls input / output of data to / from the NAND flash memory 10. Accordingly, when reading data from the NAND flash memory 10 to the outside, first, the data read from the memory cell array 11 of the NAND flash memory 10 is stored in the page buffer. Thereafter, the data in the page buffer is output to the outside via the user interface 23 in response to a user request. On the other hand, when data is stored in the NAND flash memory 10, first, externally applied data is stored in the page buffer via the user interface 23. Thereafter, the data in the page buffer is written into the memory cell array 11.

  Hereinafter, an operation until data is read from the memory cell array 11 to the page buffer is referred to as “load” of data. The operation until the data in the page buffer is transferred to the user interface 23 is called “read” of the data.

  Furthermore, an operation until data to be stored in the NAND flash memory 10 is transferred from the user interface 23 to the page buffer is referred to as data “write”. The operation until the data in the page buffer is written into the memory cell array 11 is called a “program” of data.

Returning to the description of the input / output unit 20.
<< Buffer section >>
The buffer unit 21 functions as a primary data cache in the NAND flash memory 10. The buffer unit 21 includes a plurality of data buffers 21a (for example, 2K bytes), a boot buffer 21b (for example, 1K bytes), and an SRAM buffer 21c. The buffer unit 21 is connected to the ECC data bus and the RAM register data bus. During data write, data transferred from the burst buffer 22 is temporarily held. Then, the data is written into the page buffer via the NAND data bus. At the time of data reading, data is read from the page buffer via the NAND data bus 6 and transferred to the burst buffer 22.

  As shown in FIG. 1, each of the plurality of data buffers 21a and boot buffers 21b includes a memory cell array, a sense amplifier, and a row decoder.

  The memory cell array of the plurality of data buffers 21a includes a plurality of SRAM cells capable of holding data. Each SRAM cell is connected to a word line and a bit line. Similarly to the memory cell array 11, the memory cell array of the data buffer 21a includes an area for holding main data and an area for holding parity and the like. The sense amplifier of the data buffer 21a senses and amplifies data read from the SRAM cell to the bit line. The sense amplifier of the data buffer 21a also functions as a load when data in the SRAM buffer 21c is written to the SRAM cell. The row decoder of the data buffer 21a selects a word line in the memory cell array of the data buffer 21a.

  The boot buffer 21b temporarily holds a boot code for starting the memory system 100, for example.

  The SRAM buffer 21c temporarily holds data when data is written to or read from the data buffer 21a or the boot buffer 21b.

<< Burst buffer >>
The burst buffer 22 can transfer data to and from the buffer unit 21 and the control unit 30 via a RAM register data bus. Then, data given from the host device via the user interface 23 or data given from the buffer unit 21 is temporarily held.

<< User interface >>
Next, the user interface 23 will be described. The user interface 23 can be connected to a host device (user) outside the memory system 100 and controls input / output of various signals such as data, control signals, and address Add to / from the host device. Examples of control signals include a chip enable signal / CE that enables the entire memory system 100, an address valid signal / AVD for latching an address, a clock CLK for burst read, and a write that enables a write operation. An enable signal / WE, an output enable signal / OE for enabling output of data to the outside, and the like.

  The user interface 23 is connected to the burst buffer 22 by a data input / output bus. The data input / output bus is, for example, 2 bytes. Then, the user interface 23 transfers control signals related to a data read request, a load request, a program request, and the like from the host device to the access controller 24. At the time of data reading, the data in the burst buffer 22 is output to the host device. At the time of data write, data given from the host device is transferred to the burst buffer 22.

<< Access controller >>
Next, the access controller 24 will be described. The access controller 24 receives a control signal and an address from the user interface 23. Then, the buffer unit 21, the burst buffer 22, the control unit 30, the switch (described later) 40, and the like are controlled so as to execute an operation that satisfies the request of the host device.

  For example, in response to a request from the host device, the access controller 24 sets a register 33 (described later) in the control unit 30 to an active state, and sets a command (Write / Read) in the register. Further, when the buffer unit 21 is used as a cache, the access controller 24 instructs the buffer unit 21 to read data from the page buffer or burst buffer 22. When the buffer unit 21 is not used as a cache, data is read from the PureNAND USER I / F in the user interface 23 to, for example, a RAM in the access controller 24 and the data is output to the input buffer circuit 17. Command.

<ECC Department>
Next, the ECC unit 25 will be described with reference to FIG.

  The ECC unit 25 executes error detection and error correction for input / output data to / from the NAND flash memory 10 and parity generation (hereinafter, these may be collectively referred to as ECC processing). The ECC unit 25 includes an ECC buffer 25a and an ECC engine 25b. The ECC engine 25b includes a decoder (Error Position Dec in FIG. 1), a parity syndrome, and an ECC control unit.

  The ECC buffer 25a is connected to the ECC data bus. Then, it is connected to the page buffer of the NAND flash memory 10 via the NAND data bus. Then, the data is read from the page buffer via the NAND data bus and transferred to the ECC engine 25b. The ECC buffer 25a temporarily holds the data error-corrected by the decoder in the ECC engine 25b and the parity generated by the parity syndrome, and writes this to the page buffer via the NAND data bus. The size of the ECC buffer 25a is, for example, the same size as the bus width of the ECC data bus, for example, 4 bytes. However, it may be larger than the ECC data bus width.

  When the data is loaded, the parity syndrome performs ECC processing using the data transferred from the ECC buffer 25a, and determines whether there is an error in the data. Further, when data is programmed, a parity is generated based on the data transferred from the ECC buffer 25a.

When it is determined that there is an error in the parity syndrome when loading data, the decoder specifies the position and reads the corresponding data from the page buffer to the ECC buffer 25a to correct the data. In programming data, the parity generated by the parity syndrome is held in the ECC buffer 25a and transferred to the page buffer. The ECC control unit controls the parity syndrome.

<Control unit>
Next, the control unit 30 will be described with continued reference to FIG. The control unit 30 controls operations of the NAND flash memory 10 and the input / output unit 20. That is, the memory system 100 has a function of supervising the operation as a whole.

  As illustrated, the control unit 30 includes a NAND address / command generation circuit 31, a state machine 32, a register 33, a command user interface 34, and an SRAM address / timing generation circuit 35. .

<< NAND Address / Command Generation Circuit >>
The NAND address / command generation circuit 31 controls the operation of the NAND flash memory 10 based on the control of the state machine 32. More specifically, an address, a command (Program / Load) supported by the NAND interface, and the like are generated and output to the NAND flash memory 10.

<< State Machine >>
The state machine 32 controls a sequence operation in the memory system 100 based on an internal command signal given from the command user interface 34. There are many functions supported by the state machine 32, such as loading, programming, and erasing. The operations of the NAND flash memory 10 and the input / output unit 20 are controlled so as to execute these functions. The state machine 32 performs these controls in synchronization with the internal clock ACLK generated by the oscillator 19. The state machine 32 can grasp the operation state of the NAND flash memory 10 based on the ready signal and the error signal given from the NAND sequencer 16.

<< Register >>
The register 33 is a register for setting the operation state of the function. That is, the register 33 sets the operation state of the function according to the command given from the access controller 24. More specifically, in the register 33, for example, a load command is set when data is loaded, and a program command is set when data is programmed.

<< Command User Interface >>
The command user interface 34 recognizes that a function execution command is given to the memory system 100 by setting a predetermined command in the register 33. Then, an internal command signal (Command) is issued and output to the state machine 32.

<< SRAM address / timing generation circuit >>
The SRAM address / timing generation circuit 35 controls the operation of the input / output unit 20 based on the control of the state machine 32. More specifically, the input / output unit 20 issues necessary addresses and commands and outputs them to the access controller 24 and the parity syndrome.

<Switch>
Next, the switch 40 will be described with reference to the block diagrams of FIGS.

  As illustrated in FIG. 1, the switch 40 is provided between the sense amplifier and page buffer 13 of the NAND flash memory 10 and the ECC unit 25 or the input / output buffer circuit 17 of the input / output unit 20. Is controlled by the sequencer 16 of the NAND flash memory 10.

  A specific configuration will be described with reference to FIG. Note that the latch circuit groups A0 to A1, B0 to B3, and D0 to D7 shown in FIG. 3 are omitted in FIG. 1 for convenience of explanation.

  The switch 40 includes a plurality of buffer circuit groups BFA (BFA0 to BFA7), a plurality of latch circuit groups C0 to C7, and a plurality of buffer circuit groups BFB (BFB0 to BFB7).

  Here, of the plurality of buffer circuit groups BFA, for example, BFA0 includes eight buffer circuits, but for the sake of the drawing, eight buffer circuits are shown as one box. Similarly to the buffer circuit group BFA, the latch circuit group C and the buffer circuit group BFB also have eight latch circuits and eight buffer circuits.

  That is, the switch 40 includes, for example, eight buffer circuit groups BFA each including eight buffer circuits, eight latch circuit groups C including eight latch circuits, and a buffer circuit group including eight buffer circuits. It has 8 BFBs. Here, the buffer circuit of the buffer circuit group BFA corresponding to the column direction, the latch circuit C, and the buffer circuit of the buffer circuit group BFB have one data bus (in FIG. 2, for convenience, the buffer circuit group BFA, the latch circuit group C, the buffer circuit Although the circuit group BFB is shown by one data bus, as described above, the buffer circuit group BFA in Fig. 3 has eight buffer circuits, and there are eight data buses. The eight data buses are displayed by collectively displaying the eight data buses).

  Hereinafter, as an example, one buffer circuit (BFA0-1) in the buffer circuit group BFA0 corresponding to the column direction, one latch circuit (C0-1) in the latch circuit group C0, and one in the buffer circuit group BFBFB0 This will be described using the buffer circuit (BFB0-1).

  As shown in FIG. 4, the buffer circuit BFA0-1 includes a first clocked inverter 60 connected to the latch circuit group A0, a second clocked inverter 61 connected to the latch circuit group B0, and a first inverter 62. A first NAND gate 63, a second NAND gate 64, a first NOR gate 65, a P-channel MOS transistor P1, and an N-channel MOS transistor N1.

  As shown in FIG. 4, the output terminals of the first and second clocked inverters 60 and 61 are connected in common and connected to the input terminal of the first inverter 62. The output terminal of the first inverter 62 is connected to the first input terminal of the first NAND gate 63. A PROGRAM signal is supplied to the second input terminal of the first NAND gate 63. This PROGRAM signal is a pulse signal that becomes H level during writing.

  The output terminal of the first NAND gate 63 is connected in common with the output terminals of the first and second clocked inverters 60 and 61, and is connected to the input terminal of the first inverter 62.

  The output terminal of the first inverter 62 is connected to the input terminals of the second NAND gate 64 and the first NOR gate 65. The PROGRAM signal is supplied to the other input terminal of the second NAND gate 64, and the READ signal is supplied to the other input terminal of the first NOR gate 65. This READ signal is a pulse signal that becomes H level during reading, and is an inverted signal of the PROGRAM signal.

  The output terminal of the second NAND gate 64 is connected to the gate of a P-channel MOS transistor P1 (hereinafter also referred to as transistor P1). One end of the power supply path of the transistor P1 is connected to the power supply VDD, and the other end is connected to one end of the N-channel MOS transistor.

  The output terminal of the first NOR gate 65 is connected to the gate of an N-channel MOS transistor N1 (hereinafter also referred to as transistor N1). The other end of the transistor N1 is grounded Vss. A common connection point between the other end of the transistor P1 and one end of the transistor N1 is connected to the latch circuit C0-1.

  The first and second clocked inverters 60 and 61 receive the CSLENN_PURE signal and the / CSLENN_PURE signal (inversion signal of the CSLENN_PURE signal). A signal such as the controlled CSLENN_PURE signal is input to the buffer circuit group BFA, so that the latch circuit group A and the latch circuit group C are connected, or the connection between the latch circuit group A and the latch circuit group C is disconnected. It has a function.

  A signal generation circuit such as the CSLENN_PURE signal will be described with reference to FIG.

  As shown in FIG. 5A, at the time of writing, when the buffer unit 21 is not used as a cache, the PURE signal becomes H level, and the second inverter 70 outputs an L level ONE signal. When the buffer unit 21 is used as a cache during writing, the PURE signal becomes L level, and the second inverter 70 outputs an H level ONE signal.

  As shown in FIG. 5B, the generation circuit is connected to the third NAND gate 71, the third inverter 72 connected to the output terminal of the third NAND gate 71, the fourth NAND gate 73, and the output terminal of the fourth NAND gate 73. The fourth inverter 74 is provided.

  The third NAND gate 71 receives the PURE signal and the CSLENN signal input to the second inverter 70, and the CSLENN_PURE signal is output from the third inverter 72. The fourth NAND gate 73 receives the ONE signal and CSLENN signal output from the second inverter 70, and outputs the CSLENN_ONE signal from the fourth inverter 74. Here, the CSLENN signal has a function for selecting a desired buffer circuit group BFA among the plurality of buffer circuit groups BFA using the state machine 32, and the selected buffer circuit group BFA has a CSLENN signal. H level is input, and L level is input as the CSLENN signal to the unselected buffer circuit group BFA.

  Next, the buffer circuit BFB0-1 will be described with reference to FIG. As shown in FIG. 6, the buffer circuit BFB0-1 includes a first clocked inverter 80, a fifth inverter 81, a fourth NAND gate 82, a fifth NAND gate 83, and a second NOR gate connected to the latch circuit C0. 84, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The details are the same as those of the buffer circuit BFA0-1, and thus are omitted.

[How the switch works]
Next, the operation method of the switch 40 of this embodiment is demonstrated using FIG. When the buffer circuit BFA0-1 in FIG. 4 is selected, since the same signal as that of the first clocked inverter 60 is input to the third clocked inverter 80, the buffer circuit BFB0-1 is also selected. Therefore, in this specification, (1) an operation method of the switch 40 when the buffer circuit BFA0-1 shown in FIG. 4 is selected when the buffer unit 21 is not used as a cache at the time of writing, and (2) When the buffer unit 21 is used as a cache at the time of writing and the buffer circuit BFA0-1 shown in FIG. 4 is selected, and (3) at the time of writing, the buffer circuit BFA0- shown in FIG. Three types of operation methods of the switch 40 when 1 is not selected will be described. When the buffer unit 21 is used as a cache during writing, all the buffer circuit groups BFA and BFB are selected.

<Operation method (1)>
When the buffer unit 21 is not used as a cache during writing and the buffer circuit BFA0-1 shown in FIG. 4 is selected, the PROGRAM signal is H level, the PURE signal is H level, the ONE signal is L level, and the CSLENN signal Is at the H level. Therefore, the first clocked inverter 60 is turned on, and the data of the latch circuit A0 is transferred. For example, when the data of the latch circuit A0 is at the H level, the L level is output from the first clocked inverter 60. On the other hand, the second clocked inverter 61 is turned off.

  Since the PROGRAM signal is at the H level, the output of the first inverter 62 is at the H level. Therefore, the output of the second NAND gate 64 becomes L level, and the transistor P1 is turned on. The output of the first NOR gate becomes L level, and the transistor N1 is turned off. A common connection point between the transistor P1 and the transistor N1 is charged by the power supply VDD, and an H level signal is output to the latch circuit C0-1.

  Similarly, since the buffer circuit BFB0-1 is also conducted, the data of the latch circuit C0-1 is transferred to the latch circuit D0-1.

<Operation method (2)>
When the buffer unit 21 is used as a cache at the time of writing and the buffer circuit BFA0-1 shown in FIG. 4 is selected, the PROGRAM signal is H level, the PURE signal is L level, the ONE signal is H level, and the CSLENN signal is H level. Therefore, the first clocked inverter 60 is turned off, and the second clocked inverter 61 is turned on. The data of the latch circuit B0 is transferred. For example, when the data in the latch circuit B0 is at the H level, the L level is output from the second clocked inverter 61.

  Since the PROGRAM signal is at the H level, the output of the first inverter 62 is at the H level. Therefore, the output of the second NAND gate becomes L level, and the transistor P1 is turned on. The output of the first NOR gate becomes L level, and the transistor N1 is turned off. A common connection point between the transistor P1 and the transistor N1 is charged by the power supply VDD, and an H level signal is output to the latch circuit C0-1.

  Similarly, since the buffer circuit BFB0-1 is also conducted, the data of the latch circuit C0-1 is transferred to the latch circuit D0-1.

<Operation method (3)>
At the time of writing, when the buffer circuit BFA0-1 shown in FIG. 4 is not selected, the PROGRAM signal is at the H level and the CSLENN signal is at the L level. In this case, as shown in the generation circuit of FIG. 5B, the outputs of the third NAND gate 71 and the fourth NAND gate 73 are both at the H level. Therefore, both the CSLENN_PURE signal and the CSLENN_ONE signal are at the L level, and both the first and second clocked inverters 60 and 61 are turned off. As a result, neither the latch circuit A0 nor the latch circuit B0 is transferred.

[Effect of this embodiment]
As described above, this embodiment can provide a memory system capable of reducing current consumption.

  In the memory system of the present embodiment, a signal such as the controlled CSLENN_PURE signal is input to the buffer circuit group BFA, whereby the selected latch circuit group A and the latch circuit group C are connected, and the non-selected latch circuit group The connection between A and the latch circuit group C can be disconnected.

  The first and second clocked inverters 60 and 61, the first inverter 62, and the first NAND gate 63 are not provided from the switch 40 of the present embodiment, and the present embodiment is compared with the first comparative example in which CSLENN0 to 7 are not input. Can provide a memory system capable of reducing current consumption.

  The effects will be specifically described below.

  In the present embodiment, as shown in FIG. 3, the input / output buffer circuit 17 is connected to two latch circuits A0 and A1. The latch circuit A0 is commonly connected to the buffer circuit groups BFA0 to BFA3 among the plurality of buffer circuit groups BFA. The latch circuit A1 is commonly connected to the buffer circuit groups BFA4 to BFA7 among the plurality of buffer circuit groups BFA.

  Therefore, common data is transferred to the buffer circuit groups BFA0 to BFA3. The same applies to the buffer circuit groups BFA4 to BFA7.

  In the case of the comparative example 1, when writing to a memory cell, for example, every 16 bits in the page buffer 13, 1 is selected from (0) to (3) in the page buffer, and (4) to ( 7), it is necessary to select 1 and when transferring data from the input buffer circuit 17, all buffer circuit groups BFA, all latch circuit groups C, all buffer circuit groups BFB, all latch circuit groups D must be in an operating state, which consumes current.

  However, in the memory system of this embodiment, for example, when writing into memory cells every 16 bits, the page buffer 13 (for example, (0) and (4)) corresponding to the column selected in advance, the buffer circuit groups BFA0, BFA4, The latch circuit groups C0 and C4 and the buffer circuit groups BFB0 and BFB4 are set in an operating state, and the page buffers 13 ((1) to (3), (5) to (7)) corresponding to the remaining non-selected columns are operated. It can be turned off without being in a state. As a result, the memory system of the present embodiment can reduce current consumption as compared with Comparative Example 1.

  In the memory system of the present embodiment, the plurality of buffer circuit groups BFA are provided not only as buffer circuit groups corresponding to the input / output buffer circuit 17 but also as buffer circuit groups corresponding to the ECC unit 25. Yes.

  Therefore, the memory system of the present embodiment can reduce the circuit area as compared with Comparative Example 2 in which a buffer circuit group corresponding to the input buffer circuit 17 and a buffer circuit group corresponding to the ECC unit 25 are separately provided. In addition, the memory system of the present embodiment can reduce the current consumption as compared with the case where the CSLENN signal is input to two separate buffer circuit groups by improving the comparative example 2. By shortening the data bus, the capacity of the data bus can be reduced, and as a result, data exchange can be speeded up.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

DESCRIPTION OF SYMBOLS 10 ... NAND type flash memory 11 ... Memory cell array 12 ... Row decoder 13 ... Sense amplifier, page buffer 14 ... Column decoder 15 ... Voltage generation circuit 16 ... Sequencer 17 ... Input buffer circuit 18 19 ... Oscillator 20 ... I / O part 21 ... Buffer Unit 22 ... Burst buffer 23 ... User interface 24 ... Access controller 25 ... ECC unit 30 ... Control unit 31 ... Address / command generation circuit 32 ... State machine 33 ... Register 34 ... CUI
35 ... Address / timing generation circuit 100 ... Memory system

Claims (5)

NAND flash memory,
An ECC unit that performs ECC processing on data input to the NAND flash memory or data output from the NAND flash memory, and controls input / output of data between the NAND flash memory and the outside An input / output unit;
Data output from the input / output unit, or an input / output buffer unit for holding data input to the input / output unit;
A plurality of data buses provided between the NAND flash memory and the input / output unit, and between the NAND flash memory and the input / output buffer unit;
A switch for selecting the desired data bus based on an input selection signal;
Controlling the NAND flash memory, the input / output unit, and the switch;
When writing data from the input / output buffer unit to the NAND flash memory or reading data from the NAND flash memory to the input / output buffer unit, the NAND flash memory is selected via the selected data bus. And a control unit that outputs the selection signal to the switch that does not connect between the NAND flash memory and the input / output buffer unit via the remaining data bus. A memory system comprising: 2. The memory according to claim 1, wherein the switch is connected between the NAND flash memory and the ECC unit, and is connected between the NAND flash memory and the input / output buffer unit. system. The NAND flash memory further includes a memory cell array,
The switch has a buffer circuit group corresponding to each column of the memory cell array,
3. The memory system according to claim 1, wherein a selection signal is input to a buffer circuit group corresponding to each column. 4. The memory system according to claim 3, wherein the buffer circuit group corresponding to each column includes a buffer circuit having a first clocked inverter to which a selection signal is input. The buffer circuit group corresponding to each column is:
A first inverter connected to the first clocked inverter;
A first NAND gate having a first input terminal connected to the output terminal of the first inverter and a second input terminal receiving a program signal;
A first NOR gate having a first input terminal connected to the output terminal of the first inverter and a second input terminal receiving a read signal;
A first P-channel MOS transistor having an output terminal of the first NAND gate connected to a gate and one end of a power supply path connected to a power supply;
An output terminal of the NOR gate is connected to the gate, one end of the power supply path is grounded, and the other end of the power supply path is connected to the other end of the power supply path of the P-channel MOS transistor. The memory system according to claim 4, further comprising:

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