KR20090068588A - Method for forming pattern in semiconductor device - Google Patents

Method for forming pattern in semiconductor device Download PDF

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Publication number
KR20090068588A
KR20090068588A KR1020070136266A KR20070136266A KR20090068588A KR 20090068588 A KR20090068588 A KR 20090068588A KR 1020070136266 A KR1020070136266 A KR 1020070136266A KR 20070136266 A KR20070136266 A KR 20070136266A KR 20090068588 A KR20090068588 A KR 20090068588A
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KR
South Korea
Prior art keywords
polymer layer
rich polymer
semiconductor device
pattern
layer
Prior art date
Application number
KR1020070136266A
Other languages
Korean (ko)
Inventor
이성권
Original Assignee
주식회사 하이닉스반도체
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070136266A priority Critical patent/KR20090068588A/en
Publication of KR20090068588A publication Critical patent/KR20090068588A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

A method for forming a pattern of a semiconductor device is provided to prevent generation of SiXOYCZ-based residues by removing a surface layer of a carbon rich polymer layer through a strip process using oxygen-based gas and fluorine-based gas. A hard mask pattern including a carbon rich polymer layer(21) and a silicon rich polymer layer(22) is formed on an etch target layer. An etch process is performed to etch the etch target layer in order to form an etch target layer pattern. The etch process is performed by using the hard mask pattern as an etch barrier. A strip process is performed to remove the silicon rich polymer layer. The strip process is performed by using oxygen-based gas and fluorine-based gas. The flow rate of the fluorine-based gas is smaller than the flow rate of the oxygen-based gas. A removal process is performed to remove the carbon rich polymer layer.

Description

METHODS FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a pattern forming method of a semiconductor device.

Recently, as the degree of integration of semiconductor devices increases, amorphous carbon is used as part of a hard mask for device patterning when forming a fine pattern of 100 nm or less. When amorphous carbon is used as a hard mask, patterning is easy and the selectivity is superior to that of conventional silicon oxide film (SiO 2 ), silicon nitride film (Si 3 N 4 ), silicon oxynitride film (SiON), and the like.

However, the use of amorphous carbon as a hard mask greatly increases the cost in device fabrication as compared with the case of using a conventional hard mask material film (for example, a polysilicon film).

In addition, since amorphous carbon is deposited on areas with deep steps on the peripheral circuits (e.g., various alignment keys used for monitoring masks and etching processes), the step coverage characteristics are poor, since the amorphous phase is poor. The silicon oxynitride film on carbon is deposited unevenly. As a result, when a rework process is performed on the photoresist pattern during the exposure process, a part of the amorphous carbon is lost, and a defect of the device such as lifting and particle generation is caused therein. There is this.

In order to solve this problem, a technique for patterning an underlying etching layer using heterogeneous polymer hard masks has recently been studied. Hereinafter, this will be described with reference to FIG. 1.

FIG. 1 is a view for explaining a method of forming a pattern of a semiconductor device according to the prior art. As an example, a method of forming a contact hole by etching an interlayer insulating layer will be described.

As shown in (a), a polymer layer containing a large amount of carbon (hereinafter referred to as a carbon rich polymer 11) and a polymer layer containing a large amount of silicon on the interlayer insulating film 10 made of an oxide film ( Hereinafter, a silicon rich polymer layer 12 is sequentially formed.

Subsequently, a photoresist pattern 13 for forming a contact hole is formed on the silicon rich polymer layer 12.

As shown in (b), the silicon rich polymer layer 12 and the carbon rich polymer layer 11 are etched using the photoresist pattern 13 as an etching barrier. In this etching process, the photoresist pattern 13 may be removed.

Subsequently, the interlayer insulating film 10 is etched using the etched silicon rich polymer layer 12 and the carbon rich polymer layer 11 as an etch barrier to form a contact hole 14.

As shown in (c), the silicon rich polymer layer 12 is removed by a strip process using a fluorine-based gas.

As shown in (d), by removing the carbon rich polymer layer 11 in a strip process using an oxygen-based gas, a desired pattern (contact hole 14 in this drawing) can be formed.

However, the above-described processes (a) to (d) have the following problems.

First, when the silicon rich polymer layer 12 is stripped, an interlayer insulating film 10 made of an oxide film may be lost to an attack by a fluorine-based gas, thereby increasing the size of the contact hole 14.

In addition, as a heterogeneous hard mask including the carbon rich polymer layer 11 and the silicon rich polymer layer 12 is formed, and a mask and etching process are performed, Si of the silicon rich polymer layer 12 is a lower carbon rich polymer layer. While penetrating into (11), a small amount of Si X O Y C Z series material is present in the carbon rich polymer layer 11, especially the surface layer. Such Si X O Y C Z- based material remains in the vicinity of the contact hole 14 in spite of the stripping process of the silicon rich polymer layer 12 and the carbon rich polymer layer 11 to cause a device defect. . In order to solve this problem, it may be considered to perform a separate process of removing the residue of the Si X O Y C Z series. However, further performing a separate process (eg, a strip process using a fluorine-based gas) to remove the Si X O Y C Z series residues causes loss of the interlayer insulating film 10 and the resulting contact holes 14. Will increase the size problem.

The present invention has been proposed in order to solve the above problems of the prior art, by performing a stripping process by adding a small amount of fluorine-based gas to a large amount of oxygen-based gas when stripping the silicon rich polymer layer, the loss of the etching layer and the resulting pattern A method of forming a pattern of a semiconductor device that can prevent the increase in size and prevent the occurrence of Si X O Y C Z series residue by removing the surface layer of the carbon rich polymer layer in which Si has penetrated together with the silicon rich polymer layer. To provide.

The pattern forming method of the semiconductor device of the present invention for solving the above problems comprises the steps of: forming a hard mask pattern consisting of a carbon rich polymer layer and a silicon rich polymer layer on the etched layer; Forming the etched layer pattern by etching the etched layer using the hard mask pattern as an etch barrier; Removing the silicon rich polymer layer by a strip process using an oxygen gas and a fluorine gas having a flow rate smaller than that of the oxygen gas; And removing the carbon rich polymer layer.

In the method of forming a pattern of a semiconductor device according to the present invention described above, a strip process is performed by adding a small amount of fluorine-based gas to a large amount of oxygen-based gas when stripping a silicon rich polymer layer, thereby increasing the loss of the etching layer and the resulting pattern size. In addition, the surface layer of the carbon-rich polymer layer in which Si has penetrated together with the silicon-rich polymer layer may be removed to prevent the occurrence of the residue of the Si X O Y C Z series.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a view for explaining a method of forming a pattern of a semiconductor device according to an embodiment of the present invention. In this drawing, a method of forming a contact hole by etching an interlayer insulating layer will be described as an example.

As shown in (a), the carbon rich polymer layer 21 containing a large amount of carbon and the silicon rich polymer layer 22 containing a large amount of silicon are sequentially formed on the interlayer insulating film 20 formed of an oxide film.

Next, a photoresist pattern 23 for forming a contact hole is formed on the silicon rich polymer layer 22.

As shown in (b), the silicon rich polymer layer 22 and the carbon rich polymer layer 21 are etched using the photoresist pattern 23 as an etching barrier. In the etching process, the photoresist pattern 23 may be removed.

Subsequently, the interlayer insulating layer 20 is etched using the etched silicon rich polymer layer 22 and the carbon rich polymer layer 21 as an etch barrier to form a contact hole 24.

At this time, as the processes of (a) and (b) proceed, Si penetrates into the surface layer of the carbon rich polymer layer 21 so that a small amount of Si X O Y C Z series material is present.

As shown in (c), a small amount of fluorine-based gas (for example, 50 sccm of CF 4 gas) is added to a large amount of oxygen-based gas (for example, 7000 sccm of O 2 gas) to perform a primary strip process. While removing the silicon rich polymer layer 22, the surface layer (for example, about 500 GPa) of the carbon rich polymer layer 21 in which Si penetrated is removed together. As such, since a small amount of fluorine-based gas is used in the first strip process, the loss of the interlayer insulating film 20 and the increase in the size of the contact hole 24 can be prevented, and the carbon-rich polymer layer 21 in which Si has penetrated. By removing the surface layer of the Si X O Y C Z series residues can be prevented inherently. More specifically, the primary strip process is preferably performed with a ratio of oxygen-based gas to fluorine-based gas of at least 100: 1 (ie, oxygen-based gas / fluorine-based gas ≥ 100), and relatively low bias power (e.g., For example, it is preferably carried out at 200 ~ 500W).

As shown in (d), the remaining carbon rich polymer layer 21 is removed by performing a secondary strip process using an oxygen-based gas. At this time, since the surface layer of the carbon rich polymer layer 21 is already removed through the above-described process (c), the Si X O Y C Z series residue does not occur around the contact hole 24. More specifically, the secondary strip process is preferably performed using a mixed gas of O 2 and N 2 , and is performed at a relatively high bias power (for example, 500 to 1500 W) than the process of (c). It is preferable.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a view for explaining a pattern formation method of a semiconductor device according to the prior art.

2 is a view for explaining a pattern forming method of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: interlayer insulating film 21: carbon rich polymer layer

22 silicon rich polymer layer 23 photoresist pattern

24: contact hole

Claims (9)

Forming a hard mask pattern including a carbon rich polymer layer and a silicon rich polymer layer on the etched layer; Forming the etched layer pattern by etching the etched layer using the hard mask pattern as an etch barrier; Removing the silicon rich polymer layer by a strip process using an oxygen gas and a fluorine gas having a flow rate smaller than that of the oxygen gas; And Removing the carbon rich polymer layer Pattern forming method of a semiconductor device comprising a. The method of claim 1, In the step of removing the silicon rich polymer layer, The surface layer of the carbon rich polymer layer penetrated by Si is removed together Pattern formation method of a semiconductor device. The method according to claim 1 or 2, The ratio of the oxygen-based gas to the fluorine-based gas is 100: 1 or more Pattern formation method of a semiconductor device. The method according to claim 1 or 2, The carbon rich polymer layer removing step, Performed in a strip process using an oxygen-based gas Pattern formation method of a semiconductor device. The method according to claim 1 or 2, The removing of the silicon rich polymer layer is performed while applying a first bias power. The carbon rich polymer layer removing step may be performed while a second bias power greater than the first bias power is applied. Pattern formation method of a semiconductor device. The method of claim 5, The first bias power is 200 ~ 500W Pattern formation method of a semiconductor device. The method of claim 5, The second bias power is 500 ~ 1500W Pattern formation method of a semiconductor device. The method according to claim 1 or 2, The etched layer is an oxide film Pattern formation method of a semiconductor device. The method according to claim 1 or 2, The etched layer pattern may be a contact hole pattern. Pattern formation method of a semiconductor device.
KR1020070136266A 2007-12-24 2007-12-24 Method for forming pattern in semiconductor device KR20090068588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070136266A KR20090068588A (en) 2007-12-24 2007-12-24 Method for forming pattern in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070136266A KR20090068588A (en) 2007-12-24 2007-12-24 Method for forming pattern in semiconductor device

Publications (1)

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KR20090068588A true KR20090068588A (en) 2009-06-29

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