KR20090068133A - Semiconductor memory device and memory system including the same - Google Patents

Abstract

A semiconductor memory device and a memory system including the same are provided, which maintain the dosage balance between the sense wire and the reference sense wire. A first memory block comprises the first memory cell. The second memory block comprises the second memory cell. The column decode circuit(100) accesses the first memory cell of the first memory block through the first conductor line. At this time, the second memory cell of the second memory block is accessed through the second conductor line. The column decode circuit activates the first and the second conductor line. The column decode circuit comprises the first and the second switch for activating the first and the second conductor lines.

Description

A semiconductor memory device and a memory system including the same {Semiconductor memory device and memory system INCLUDING THE SAME}

The present invention relates to the connection of select bit lines and non-select bit lines of nonvolatile semiconductor memory arrays, and sense (sensing) lines and reference sense (sensing) lines of sense (sensing) circuits. More specifically, the present invention does not require an increase in the column free decorder circuit, and the column is connected while maintaining the maximum capacity balance between the sense line and the reference sense line. A semiconductor memory device having a decode circuit.

As described in Patent Document 1 (Japanese Unexamined Patent Publication No. 2002-8386), in a nonvolatile semiconductor memory, one of the plurality of bit lines constituting the memory array is selectively connected to one of the main bit lines, One of the plurality of main bit lines is selectively connected to one of the data lines. In addition, the sense (sensing) line of the differential amplifier constituting the sense (sensing) circuit is connected to the data line, and the reference sense (sensing) line is connected to the reference data line, respectively, to determine the data read from the memory cell. .

In the differential amplifier constituting the sense circuit, it is important to obtain a capacity balance by accurately matching the capacitance of the reference sense line to the capacitance of the sense line in view of the speed of reading and immunity to noise. . However, if the capacity of the reference sense (sensing) line is to be matched to the capacity of the sense (sensing) line by using the dummy capacitance, it is difficult to accurately match the capacitance, and the place where the capacitance is arranged is weakened to noise. In addition, there is a problem that an area demerit occurs.

For this reason, patent document 1 is equipped with the memory array in which the 1st and 2nd memory cells are arrange | positioned, and the 1st and 2nd column tree containing the wiring group to which the data of a 1st and 2nd memory cell is transmitted, When the first memory cell is selected, a configuration is described in which the first column tree side is coupled to the sense (sense) signal input terminal of the differential amplifier and the second column tree side is coupled to the reference signal input terminal to obtain the capacity balance. This configuration will be described below.

FIG. 2 is a memory block diagram illustrating a configuration of a memory array that obtains a capacity balance between a sense (sensing) line and a reference sense (sensing) line of a differential amplifier. In FIG. 2, the first column tree is a wiring group through which data of the first memory cell is transferred, and includes a first intermediate data line IDL01, a main bit line MBL0-01, and a bit line Bi: BL0, 1, and Bj. : BL0, 1). The second column tree is a wiring group through which data of another memory cell is transferred, and includes a second intermediate data line IDL23, a main bit line MBL0-23, and a bit line Bi: BL2, 3, Bj: BL2, 3 ) Is included. Memory cells (not shown) are connected to these bit lines BL to form a memory array.

The expansion of the memory array is extended by the first column gates 0103-Bi: 1 and 0103-Bj: 1 having the same configuration shown by broken lines to form blocks Bi and Bj. As a result, since the second column gate 0105 is selected by the second column selection D1 of the second column selection decoder 0104, the main bit lines MBL1-01 and MBL1-23 are connected to the first intermediate data line. (IDL01, IDL23), respectively.

Next, the selection of the bit line BL will be described. The first column select decoder 0102 decodes the column address internal address signal, and selects and activates one of the plurality of first column select signals Bi: H0 to Bi: H3 and Bj: H0 to Bj: H3. . As a result, one of the gates of the first column gates 1010-Bi: 0 and 0103-Bj: 0 is turned on, and one of the bit lines Bi: BL0 to Bi: BL3 and Bj: BL0 to Bj: BL3 is turned on. Is connected to the main bit line (MBL0-01 or MBL0-23). At this time, since the second column select decoder 0104 is activated by the second column select signal D0, the main bit line MBL0-01 is connected to the first intermediate data line IDL01 and the main bit line ( MBL0-23 is connected to the second intermediate data line IDL23.

The column replacement select decoder 0106 decodes an internal address signal for column selection, and selects one of the first column replacement signals SW01 and SW23. When the memory cell in the first column tree is selected, the replacement signal SW01 is set high and the replacement signal SW23 is set low. As a result, the first intermediate data line IDL01 is connected to the data line DL. At the same time, the second intermediate data line IDL23 is connected to the reference data line RDL. When the memory cell in the second column tree is selected, the replacement signal SW01 goes low and the replacement signal SW23 goes high, and the second intermediate data line IDL23 is connected to the data line DL. At the same time, the first intermediate data line IDL01 is connected to the reference data line RDL.

Further, since the data line DL is coupled to the sense signal input terminal side of the differential amplifier in the sense circuit, the reference data line RDL is coupled to the reference signal input terminal side (not shown). A column tree including memory cells read-selected among the first and second column trees is coupled to the data line DL, and the other non-selected column tree is coupled to the reference data line RDL. Thereby, since the structure of a 1st and 2nd column tree is the same, the capacity of a tree is the same. Therefore, the capacitances added to the data lines DL and the reference data lines RDL can be made the same, and the capacitances can be accurately matched.

According to this configuration, however, in order to connect the selected bit line and the unselected bit line of the first and second column trees to either of the main bit lines MBL0-01 or MBL0-23, respectively, the same first column select decoder ( 0102 is provided in each of the blocks Bi and Block Bj independently. Thus, since the number of circuits of the first column select decoder is doubled, the area of the circuit layout is doubled, resulting in an increase in chip size.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to select selected and unselected bit lines of a nonvolatile semiconductor memory array, sense (sensing) lines and reference sense (sensing) lines of a sense (sensing) circuit; To provide a semiconductor memory device having a column decode circuit connected to each other while maintaining a maximum capacity balance between a sense (sensing) line and a reference sense (sensing) line without requiring an increase in the column free decoder circuit. Is in.

In an embodiment, a semiconductor memory device may include a first memory block including a first memory cell; A second memory block including a second memory cell; And a column decode circuit for accessing the first memory cell of the first memory block through a first conductor line and accessing the second memory cell of the second memory block through a second conductor line; A column decode circuit activates the first and second conductor lines in response to one of an address for reading the first memory cell or an address for reading the second memory cell.

In an embodiment, the column decode circuit comprises: first and second switches for activating the first and second conductor lines, respectively; And the column decode circuit includes a predecode circuit for activating the first and second switches in response to one of an address for reading the first memory cell or an address for reading the second memory cell.

In an embodiment, the apparatus may further include a sense amplifier for determining data read from the first memory cell, wherein the column decode circuit connects the first conductor line to a sense line of the sense amplifier, and the second conductor line. Is connected to a reference sense line of the sense amplifier, the sense line is a line for receiving and determining the read data, and the reference sense line is a line for providing a capacity balance with the sense line.

In an embodiment, the column decode circuit activates the first and second conductor lines in response to an address for reading the second memory cell.

In an embodiment, a memory system may include a semiconductor memory device; And a controller for controlling the semiconductor memory device, wherein the semiconductor memory device comprises: a first memory block including a first memory cell; A second memory block including a second memory cell; A column decode circuit for reading data of the first memory cell of the first memory block through a first conductor line and reading data of the second memory cell of the second memory block through a second conductor line; The column decode circuit activates the first and second conductor lines in response to an address for reading the first memory cell.

In an embodiment, the semiconductor memory device and the controller are integrated into one semiconductor device.

In an embodiment, the semiconductor memory device and the controller form a semiconductor disk device.

In an embodiment, the semiconductor memory device and the controller form a memory card.

A memory array in which a first memory cell is disposed on a first direction side of the plurality of first and second blocks, and a second memory cell is disposed on a second direction side; A first column tree including a wiring group through which data of the first memory cell disposed on the first direction side of the first and second blocks is transferred; A second column tree including a wiring group through which data of the second memory cell disposed on the second direction side of the first and second blocks is transferred; And a column decode coupling a bit line of the first memory cell to a first main bit line of the first column tree and a bit line of the second memory cell to a second main bit line of the second column tree. In a semiconductor memory device including a circuit, the column decode circuit may include a first column gate circuit belonging to the first block, a second column gate circuit belonging to the second block, and the first and first blocks. A column free decoder circuit for controlling a two column gate circuit, wherein the first and second column gate circuits are disposed opposite each other, simultaneously selected by the column free decoder circuit, and when the first memory cell is selected Coupling a bit line of the selected first memory cell to a first main bit line of the first column tree, and simultaneously Couple an unselected bit line to a second main bit line of the second column tree, and when the second memory cell is selected, connect the bit line of the selected second memory cell to the second main bit of the second column tree At the same time as coupling to a line, an unselected bit line of the first column tree is coupled to the first main bit line of the first column tree.

According to the present invention, it is necessary to increase the column predecoder circuit in the connection between the select bit line and the non-select bit line of the nonvolatile semiconductor memory array, and the sense (sensing) line and the reference sense (sensing) line of the sense circuit. It is possible to connect to each other without using. In addition, it is possible to provide a semiconductor memory device having a column decode circuit capable of maintaining a maximum capacity balance between a sense (sensing) line and a reference sense (sensing) line.

In an exemplary embodiment, a memory device includes a first memory block including a first memory cell, a second memory block including a second memory cell, and a first memory cell of the first memory block through a first conductor line. And a column decode circuit for accessing a second memory cell of the second memory block through a second conductor line, the column decode circuit in response to an address for reading the first memory cell. Activate the line. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1 is a block diagram illustrating a column decode circuit 100 according to an exemplary embodiment of the present invention. In FIG. 1, the column decode circuit 100 includes bit lines 13-1 and 13-2 to which first memory cells arranged on one side of the first and second blocks 10-1 and 20-1 belong. , A first column tree having bit lines 23-1 and 23-2, and a first main bit line 30-1, and another of the first and second blocks 10-1 and 20-1. A bit line 13-3, 13-4, a bit line 23-3, 23-4, and a second main bit line 40-1, to which the second memory cells arranged on one direction side belong; It contains a second column tree.

Based on this tree configuration, one of the bit lines 13-1 and 13-2 of the first memory cell is coupled to the first main bit line 30-1 of the first column tree or the second memory. First column gate circuit belonging to first block 10-1 coupling one of the bit lines 13-3, 13-4 of the cell to the second main bit line 40-1 of the second column tree. (15-1) and one of the bit lines 23-1 and 23-2 of the first memory cell to the first main bit line 30-1 of the first column tree or the second memory A second column gate circuit belonging to a second block 20-1 coupling one of the bit lines 23-3 and 23-4 of the cell to the second main bit line 40-1 of the second column tree (25-1) and column predecoder circuit 50 for controlling the first and second column gate circuits 15-1, 25-1.

In the first column gate circuit 15-1 belonging to the first block 10-1, the sources of the NMOS transistors 17-1, 17-2 are first main bit lines 30-1 of the first column tree. ), The drain is connected to the bit lines 13-1 and 13-2, respectively, and the gate is connected to the column free decoder circuit 50, respectively. In addition, the sources of the NMOS transistors 17-3 and 17-4 are connected to each other to the second main bit line 40-1 of the second column tree, and the drain is connected to the bit lines 13-3 and 13-4. The gates are respectively connected, and the gates are respectively connected to the column free decoder circuit 50. A plurality of first memory cells are connected to the bit lines 13-1 and 13-2, and a plurality of second memory cells are connected to the bit lines 13-3 and 13-4, respectively (not shown).

In the second column gate circuit 25-1 belonging to the second block 20-1, the sources of the NMOS transistors 27-1, 27-2 are connected to the first main bit line 30-1 of the first column tree. ), The drain is connected to the bit lines 23-1 and 23-2, respectively, and the gate is connected to the column free decoder circuit 50, respectively. In addition, the source of the NMOS transistors 27-3 and 27-4 is connected to the second main bit line 40-1 of the second column tree, and the drain is connected to the bit lines 23-3 and 23-4. The gates are respectively connected, and the gates are respectively connected to the column free decoder circuit 50. A plurality of first memory cells are connected to the bit lines 13-1 and 23-2, and a plurality of second memory cells are connected to the bit lines 23-3 and 23-4, respectively (not shown).

When one of the first memory cells of the bit line 13-1 is selected, the column free decoder circuit 50 receives the selection address signal from the selection address signal line and outputs the selection signal to the selection line SEL1. By this signal, the NMOS transistors 17-1 and 27-4 are selected, and the read signal of the first memory cell is the first main bit through the bit line 13-1 and the NMOS transistor 17-1. The unselected bit line 23-4 is transmitted to the line 30-1 and is connected as a load capacitance to the second main bit line 40-1 through the NMOS transistor 27-4. When one of the first memory cells of the bit line 13-2 is selected, the selection signal is output to the selection line SEL2 by the same process, and the NMOS transistors 17-2 and 27-3 are selected. The read signal of the first memory cell is transmitted to the first main bit line 30-1, and the unselected bit line 23-3 is connected to the second main bit line 40-1 as a load capacitance.

When one of the second memory cells of the bit line 13-3 is selected, the column free decoder circuit 50 receives the selection address signal from the selection address signal line and outputs the selection signal to the selection line SEL3. By this signal, the NMOS transistors 17-3 and 27-2 are selected, and the read signal of the second memory cell is the second main bit through the bit line 13-3 and the NMOS transistor 17-3. The unselected bit line 23-2 is connected to the first main bit line 30-1 as a load capacitance via the NMOS transistor 27-2. When one of the second memory cells of the bit line 13-4 is selected, the selection signal is output to the selection line SEL4 by the same process, and the NMOS transistors 17-4 and 27-1 are selected. The read signal of the second memory cell is transmitted to the second main bit line 40-1, and the unselected bit line 23-1 is connected to the first main bit line 30-1 as a load capacitance. .

When one of the first memory cells of the bit line 23-1 is selected, the NMOS transistors 27-1 and 17-4 are selected, and one of the first memory cells of the bit line 23-2 is selected. In this case, the NMOS transistors 27-2 and 17-3 are selected, and when one of the second memory cells of the bit line 23-3 is selected, the NMOS transistors 27-3 and 17-2 are selected. When selected, and when one of the second memory cells of the bit line 23-4 is selected, the NMOS transistors 27-4 and 17-1 are selected, and the transfer and unselect bit of the read signal of the selected memory cell is selected. The load capacity of the line is connected. The first main bit line 30-1 and the second main bit line 40-1 are connected to a sense (sensing) line of a sense amplifier through a column select decoder and a column replacement gate to connect the memory cell. The read signal is transmitted and connected to the reference sense (sense) line to apply the load capacity of the unselected bit line.

In the expansion of the memory array, the first block 10-2, to which the first column gate circuit 15-2 belongs, and the second block 20-2, to which the second column gate circuit 25-2 belongs, As shown, expansion is achieved by expanding the first and second blocks in pairs. In this case, in selecting each tree, the first main bit lines 30-1 and 30-2 and the second main bit lines 40-1 and 40 in which the selection bit line and the non-selection bit line are combined by the same process. -2) is selected by the column select decoder, the read signal of the select bit line is transmitted to the sense (sensing) line of the sense amplifier through the column replacement gate, and the load capacity of the non-select bit line is transferred to the reference sense (sensing) line. It is connected as if it is authorized.

As described above, according to the exemplary embodiment of the present invention, the first and second column gate circuits are disposed to face each other and are simultaneously selected by the column free decoder circuit. It is possible to connect the selection bit line and the sense (sensing) line and the reference sense (sensing) line of the sense (sensing) circuit without requiring an increase in the column free decoder circuit, and furthermore, It is possible to keep the capacity balance with the reference sense (sensing) line to the maximum. By applying this column decode circuit, it is possible to provide a semiconductor memory device having excellent capacity balance between a sense (sensing) line and a reference sense (sensing) line without causing an increase in chip size.

3 is a block diagram illustrating a memory system 200 including a semiconductor memory device 210 including a column decode circuit 100 according to an exemplary embodiment of the inventive concept. Referring to FIG. 3, a memory system 200 according to an embodiment of the present invention includes a semiconductor memory device 210 and a controller 220.

The controller 220 is connected to the host and the semiconductor memory device 210. The controller 220 transfers data read from the semiconductor memory device 210 to the host, and stores data transferred from the host in the semiconductor memory device 210.

Controller 220 may include well known components such as a RAM, a processing unit, a host interface, and a memory interface. The RAM will be used as the operating memory of the processing unit. The processing unit will control the overall operation of the controller 220. The host interface will include a protocol for performing data exchange between the host and the controller 220. In an exemplary embodiment, the controller 220 may be configured among various interface protocols such as USB, MMC, PCI-E, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, SCSI, ESDI, and Integrated Drive Electronics (IDE). It will be configured to communicate with the outside (host) through one. The memory interface will interface with the semiconductor memory device 210. The controller 220 may further include an error correction block. The error correction block will detect and correct an error of data read from the semiconductor memory device 210.

The semiconductor memory device 210 may include a memory cell array for storing data, a read / write circuit for writing and reading data to the memory cell array, an address decoder for decoding an address transferred from an external source and transmitting the decoded address to a read / write circuit; Control logic for controlling the overall operation of the semiconductor memory device 210. In addition, the semiconductor memory device 210 may include a column decode circuit 100 according to an embodiment of the present invention described with reference to FIG. 1. In exemplary embodiments, the semiconductor memory device 210 may include a volatile memory device such as SRAM, DRAM, SDRAM, or the like. As another example, the semiconductor memory device 210 may include a nonvolatile memory device such as a ROM, a PROM, an EPROM, an EEPROM, a flash memory device, a PRAM, an MRAM, an RRAM, an FRAM, or the like.

The controller 220 and the semiconductor memory device 210 may be integrated into one semiconductor device. In exemplary embodiments, the controller 220 and the semiconductor memory device 210 may be integrated into one semiconductor device to constitute a memory card. For example, the controller 220 and the semiconductor memory device 210 may be integrated into a single semiconductor device such that a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM / SMC), a memory stick, and a multimedia card are provided. Memory cards such as (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD), Universal Flash Storage (UFS), etc.

As another example, the controller 220 and the semiconductor memory device 210 may be integrated into one semiconductor device to constitute a solid state disk / drive (SSD). When the memory system 200 is used as the semiconductor disk SSD, an operating speed of a host connected to the memory system 10 may be improved.

As another example, the memory system 200 may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or information. It will be applied to devices that can transmit and receive in a wireless environment.

As another example, the semiconductor memory device 210 or the memory system 200 may be mounted in various types of packages. For example, the semiconductor memory device 210 or the memory system 200 may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), It will be packaged and implemented in the same way as a Wafer-Level Processed Stack Package (WSP).

4 is a block diagram illustrating an embodiment of a computing system 300 including the memory system 200 of FIG. 3. Referring to FIG. 4, a computing system 300 according to an embodiment of the present invention may include a central processing unit 310, a random access memory (RAM) 320, a user interface 330, a power source 340, and a memory. System 200.

The memory system 200 is electrically connected to the CPU 310, the RAM 320, the user interface 330, and the power source 340 through the system bus 350. Data provided through the user interface 330 or processed by the central processing unit 310 is stored in the memory system 10. The memory system 10 includes a controller 220 and a semiconductor memory device 210.

When the memory system 200 is mounted as a semiconductor disk device (SSD), the booting speed of the computing system 300 may be dramatically increased. Although not shown in the drawings, it will be understood by those skilled in the art that the system according to the present invention may further include an application chipset, a camera image processor, and the like.

In the detailed description of the present invention, specific embodiments have been described, but it is obvious that various modifications can be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a block diagram illustrating a column decode circuit according to an exemplary embodiment of the present invention.

FIG. 2 is a memory block diagram illustrating a memory array configuration for obtaining a capacity balance between a sense (sensing) line and a reference sense (sensing) line of a differential amplifier.

3 is a block diagram illustrating a memory system including a semiconductor memory device including a column decode circuit according to an embodiment of the present invention.

4 is a block diagram illustrating an embodiment of a computing system including the memory system of FIG. 3.

Claims (9)

A first memory block including a first memory cell; A second memory block including a second memory cell; And A column decode circuit for accessing the first memory cell of the first memory block through a first conductor line and accessing the second memory cell of the second memory block through a second conductor line; And the column decode circuit activates the first and second conductor lines in response to one of an address for reading the first memory cell or an address for reading the second memory cell. The method of claim 1, The column decode circuit is First and second switches for activating the first and second conductor wires, respectively; And And the column decode circuit comprises a predecode circuit for activating the first and second switches in response to one of an address for reading the first memory cell or an address for reading the second memory cell. The method of claim 1, And a sense amplifier for determining data read from the first memory cell, The column decode circuit connects the first conductor line to the sense line of the sense amplifier, the second conductor line to the reference sense line of the sense amplifier, The sensing line is a line for receiving and reading the read data, and the reference sensing line is a line for providing a capacity balance with the sensing line. The method of claim 1, And the column decode circuit activates the first and second conductor lines in response to an address for reading the second memory cell. Semiconductor memory devices; And A controller for controlling the semiconductor memory device, The semiconductor memory device A first memory block including a first memory cell; A second memory block including a second memory cell; A column decode circuit for reading data of the first memory cell of the first memory block through a first conductor line and reading data of the second memory cell of the second memory block through a second conductor line; And the column decode circuit activates the first and second conductor lines in response to an address for reading the first memory cell. The method of claim 5, wherein And the semiconductor memory device and the controller are integrated into one semiconductor device. The method of claim 5, wherein And the semiconductor memory device and the controller form a semiconductor disk device. The method of claim 5, wherein And the semiconductor memory device and the controller form a memory card. A memory array in which a first memory cell is disposed on a first direction side of the plurality of first and second blocks, and a second memory cell is disposed on a second direction side; A first column tree including a wiring group through which data of the first memory cell disposed on the first direction side of the first and second blocks is transferred; A second column tree including a wiring group through which data of the second memory cell disposed on the second direction side of the first and second blocks is transferred; And A column decode circuit for coupling a bit line of the first memory cell to a first main bit line of the first column tree and a bit line of the second memory cell to a second main bit line of the second column tree In a semiconductor memory device comprising: The column decode circuit comprises a first column gate circuit belonging to the first block, a second column gate circuit belonging to the second block, and a column pre decoder circuit for controlling the first and second column gate circuits, The first and second column gate circuits are arranged opposite to each other and simultaneously selected by the column free decoder circuit, When the first memory cell is selected, couples the bit line of the selected first memory cell to the first main bit line of the first column tree, and simultaneously connects the unselected bit line of the second column tree to the second column. To the second main bit line of the tree, When the second memory cell is selected, couples the bit line of the selected second memory cell to the second main bit line of the second column tree, and simultaneously unselects the bit line of the first column tree to the first column. And coupled to the first main bit line of the tree.

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