KR20090067365A - Fabrication method of a semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor device is provided to improve the electrical characteristic of the MIM capacitor by preventing a production of voids in the bottom electrode and between diffusion barriers. A manufacturing method of the semiconductor device comprises a formation step(402) of a damascene patterns, a formation step(404) of filling patterns, a formation step(406) of the diffusion barrier, and a formation step(408, 410, 412) of the metal wiring structure. In a damascene pattern formation step, the damascene process is performed to in the inter-layer insulating film in order to form the damascene patterns on the inter-layer insulating film. The inter-layer insulating film is formed on the top of the substrate. The formation step of the filling patterns performed to form the bottom electrode and down metal wiring on damascene patterns. The bottom electrode and down metal wiring comprise copper and metallic ions. Metal is copper and other material. The formation step of the diffusion barrier is performed in order to form the diffusion barrier on the bottom electrode and down metal wiring. The diffusion barrier is formed on the inter-layer insulating film in order to cover the bottom electrode and down metal wiring. The formation step of the metal wiring structure is performed in order to form the metal wiring structure on the diffusion barrier. The metal wiring structure electrically connects through the diffusion barrier with the bottom electrode and down metal wiring.

Description

Manufacturing method of semiconductor device {FABRICATION METHOD OF A SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device suitable for manufacturing a MIM (Metal / Insulator / Metal) capacitor in a semiconductor device such as a CMOS image sensor (CIS). It relates to a manufacturing method.

As is well known, an image sensor refers to an apparatus for converting optical information of one or two or more dimensions into an electrical signal.

Such image sensors are classified into image capturing tubes and solid-state image capturing apparatuses. Image capturing tubes are widely used in measurement, control, and recognition using image processing technology centered on televisions, and application technologies have been developed. Commercially available solid-state image capturing devices are CMOS (Complementary). There are two types of metal oxide semiconductor (CCD) type and charge coupled device (CCD) type.

In particular, a CMOS image sensor (CIS) refers to a device for converting an optical image into an electrical signal using a CMOS manufacturing technology, such a CMOS image device for image sensors such as digital still cameras, mobile phone cameras, door phone cameras As demand increases explosively, the demand for CIS devices is growing exponentially, and high performance CIS devices are required in various applications. In response to this demand, process development has been conducted to develop a CIS device using a 0.18 micron design rule. Next-generation image sensors require a process development based on a 0.13 micron design rule.

In general, a semiconductor device having a small pattern of 0.13 microns or less is difficult to form a metal wiring using aluminum (Al). Therefore, it is preferable to apply metal wiring using copper (Cu) instead of aluminum. However, in the case of forming the metal wiring using copper, diffusion using SiN, SiC, or the like to prevent the diffusion of Cu in the intermetal dielectric (IMD) and function as an etch stopper layer It was necessary to form a protective film.

On the other hand, the structure of the MIM (Metal / Insulator / Metal) capacitors generally used in CIS devices include T-shaped, U-shaped, and symmetric (Asymmetric) MIM structures. Among them, symmetrical MIM capacitors have a simpler process than the formation of T-shaped or U-shaped capacitors and are currently used in various ways. In particular, recently, copper metal wiring is used as the lower electrode of the MIM capacitor, and a copper diffusion barrier is used as a dielectric film. Attention has been paid to the formation of the MIM capacitor of the image sensor.

1 is a cross-sectional view showing an image sensor having a conventional MIM capacitor.

Referring to FIG. 1, first, a first interlayer insulating film 102 is deposited on a semiconductor substrate 100 on which a predetermined lower layer is formed, and then copper (Cu) is used in the first interlayer insulating film 102 through a damascene process. To form lower metal interconnections 104a and 104b, and to deposit a SiN film or a SiC film with a diffusion barrier film 106 to prevent diffusion of copper, and to form titanium (Ti) on the diffusion barrier film 106 corresponding to the capacitor region. The upper electrode 108 of the patterned capacitor is formed by depositing and etching a metal such as).

In this case, the lower metal wire 104a formed in the first interlayer insulating layer 102 corresponding to the capacitor region means a lower electrode of the capacitor (hereinafter, reference numeral 104a is referred to as a lower electrode). In addition, 104b is a lower metal wiring which functions as a general metal wiring in a logic element area | region. Thereby, the MIM capacitor consisting of the lower electrode 104a / diffusion prevention film 106 / upper electrode 108 is completed. Here, an etch stop layer 110 may be formed on the upper electrode 108 to protect the surface of the upper electrode 108.

Subsequently, a second interlayer insulating layer 112 is formed on the diffusion barrier layer 106 on which the MIM capacitor is completed, an etch stop layer 114 is formed on the second interlayer insulating layer 112, and the etch stop layer 114 is formed. After the third interlayer insulating film 116 is deposited on the first and second metal wirings 118a for capacitors for connecting the lower electrode 104a and the upper electrode 108 to an external circuit through a dual damascene process. 118b and an upper metal wiring 118c for connecting the lower metal wiring 104b with an external circuit.

However, when a metal wiring made of copper (Cu) is used as the lower electrode 104a as in the related art, voids (interfaces) between the lower electrode 104a of the physical properties of copper and the dielectric film made of SiN, which is the diffusion barrier film 106, are used. void is generated, and when SiN is deposited by a chemical vapor deposition process (CVD) through a subsequent process, bacon seams that existed in the lower electrode 104a are caused by stress generated during SiN deposition. Vacancy moves to the interface of the lower electrode 104a / diffusion prevention film 106. Accordingly, as shown in FIG. 2, there is a problem in that voids are generated at the interface of the lower electrode 104a / diffusion barrier 106 (that is, the interface of Cu / SiN). It is a situation that acts as a factor to lower the operating characteristics.

Accordingly, the present invention forms a lower electrode by adding metal ions into the copper plating film during the electroplating of copper used as the lower electrode, thereby manufacturing a semiconductor device capable of preventing the generation of voids between the lower electrode and the diffusion barrier layer. To provide a method.

The present invention includes forming a first interlayer insulating film on a semiconductor substrate including an image sensor-related device and then patterning it through a damascene process; Forming a lower electrode and a lower metal interconnection through copper electroplating in which metal ions are added to the semiconductor substrate including the patterned first interlayer insulating layer; Forming a diffusion barrier over the lower electrode and the lower metal wiring; and forming a metal wiring structure connected to the lower electrode and the lower metal wiring on the semiconductor substrate on which the lower electrode is formed. It provides a method for producing.

The present invention, unlike the conventional method of forming the lower electrode using only copper in the process of manufacturing the MIM capacitor of the semiconductor device, such as an image sensor, the lower electrode for forming the MIM capacitor in the semiconductor device, such as an image sensor The diffusion barrier layer is formed after the copper electroplating with ions, and then the upper structure is formed to prevent voids occurring at the interface between the lower electrode and the diffusion barrier layer, thereby improving the MIM capacitor characteristics of the semiconductor device. This can improve the yield of the semiconductor device.

SUMMARY OF THE INVENTION In accordance with an aspect of the present invention, after forming a lower electrode for forming a MIM capacitor in a semiconductor device such as an image sensor by performing copper electroplating with metal ions, a diffusion barrier is formed, and then an upper electrode is formed thereon. And the first and second metal wires and the upper metal wires connected to the upper and second metal wires, respectively. The technical problems can be solved through the technical means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view showing the formation of the lower electrode of the MIM capacitor by electroplating according to a preferred embodiment of the present invention, Figure 4 is a flowchart showing a process of manufacturing a MIM capacitor according to a preferred embodiment of the present invention to be. Through these drawings will be described for the MIM capacitor manufacturing method according to the present invention. Hereinafter, the reference numerals of the image sensor including the MIM capacitor illustrated in FIG. 1 will be described.

Referring to FIGS. 3 and 4, first, a first interlayer insulating layer 102 is deposited on a semiconductor substrate 100 on which a predetermined lower layer (eg, an image sensor related device) is formed, and then a contact first method or a trench first method. The first interlayer insulating film 102 is patterned through a damascene process of the method (step 402).

Subsequently, lower metal interconnections 104a and 104b are formed in the patterned first interlayer insulating layer 102 by using copper (Cu) electroplating (step 404).

Here, copper electroplating is performed by adding metal ions such as Pb, Ti, Co, etc. in the copper plating film, and the addition of metal elements such as Pb, Ti, Co, etc. is performed in the copper electrode as shown in FIG. 3. (Cu Anode) and the semiconductor substrate electrode (w / f Cathode) are connected through a wiring, and the first interlayer insulating film 102 is patterned on an electrolyte to which metal ions of Pb2 +, Ti +, or Co2 + are added. The semiconductor substrate 100 is immersed to perform electroplating. Here, metal elements such as Pb, Ti, Co, and the like have conditions in the range of approximately 95 ppm-100 ppm.

In addition, the standard reduction potential of Cu2 ++ 2e → Cu is about 0.3402 V (Standard Hydration Electrode (SHE), and the standard reduction potential of Pb2 ++ 2e → Pb) during copper electroplating. Is approximately -0.13V (SHE), the standard reduction potential of Ti is approximately -0.28V, the standard reduction potential of Co is approximately -0.34V, and the reduction potential for copper plating is each of Pb2 +, Ti +, and Co2 + potentials. Since it is relatively higher, when a voltage lower than the reduction potential of the metal element (ie, Pb, Ti, or Co) to be added during electroplating is applied, the plating of Cu-Pb (or Cu-Ti or Cu-Co) is performed. Can be done.

In addition, since an electrolytic solution containing H + ions is used during copper electroplating, the plating voltage must be adjusted so that a reaction of '2H ++ 2e → H2' does not occur during electroplating, so that an H2 evolution reaction occurs. In this case, defects on the surface of the plating film are generated due to the bubble caused by the H 2 emission reaction, and the plating efficiency decreases as much as the H 2 emission reaction in the entire reduction reaction. Since the reduction potential for either one is lower than the H2 emission potential, H2 emission reaction occurs during Cu-Pb (or Cu-Ti or Cu-Co) plating, and the pH in the electrolyte (i.e. plating solution) is adjusted to prevent this. By controlling the H2 emission potential to be relatively lower than the respective potentials of Pb2 +, Ti + and Co2 +, it is possible to prevent the H2 emission reaction, which, in electrochemical view, shows that the reduction potential for H2 emission is 'E = -0.0592pH' Since it is possible to prevent the 'pH> 6.0' by controlling the conditions of Cu-Pb (or Cu-Ti or Cu-Co) plating during H2-emitting reaction.

Impurities (metal elements of any one of Pb, Ti, and Co) added to the copper plating film are pinned at a grain boundary of the copper plating film later, thereby preventing diffusion of baconcies existing in the plating film. This prevents the generation of voids at the interface between the lower metal wiring 104a formed of the copper plating film and the SiN film or the diffusion barrier film 106 of the SiC film.

Next, a SiN film or a SiC film is formed as a diffusion barrier film 106 for preventing the diffusion of copper (step 406), and a metal such as titanium (Ti) is deposited on the diffusion barrier film 106 corresponding to the capacitor region. And forming the upper electrode 108 of the patterned capacitor by etching (step 408).

In this case, the lower metal interconnection 104a formed in the first interlayer insulating layer 102 corresponding to the capacitor region means a lower electrode of the capacitor (hereinafter, reference numeral 104a is referred to as a lower electrode). Further, 104b is a lower metallization that functions as a general metallization in the logic element region. Thereby, the MIM capacitor consisting of the lower electrode 104a / diffusion prevention film 106 / upper electrode 108 is completed. Here, an etch stop layer 110 may be formed on the upper electrode 108 to protect the surface of the upper electrode 108.

Subsequently, a second interlayer insulating layer 112 is formed on the diffusion barrier layer 106 on which the MIM capacitor is completed, an etch stop layer 114 is formed on the second interlayer insulating layer 112, and the etch stop layer 114 is formed. After the third interlayer insulating film 116 is deposited on the substrate (step 410), the first and second capacitors for connecting the lower electrode 104a and the upper electrode 108 to an external circuit through a dual damascene process. The metal wires 118a and 118b are formed, and the upper metal wires 118c are formed to connect the lower metal wires 104b with an external circuit (step 412).

Therefore, in a semiconductor device such as an image sensor, a lower electrode for forming a MIM capacitor is formed by performing copper electroplating with metal ions, and thereafter, a diffusion barrier is formed, and then connected to the lower electrode and the lower metal wiring thereon. By forming a metal wiring structure, a void phenomenon occurring at the interface between the lower electrode and the diffusion barrier layer can be prevented, thereby effectively manufacturing the MIM capacitor of the semiconductor device.

In the foregoing description, the present invention has been described with reference to preferred embodiments, but the present invention is not necessarily limited thereto. Those skilled in the art will appreciate that the present invention may be modified without departing from the spirit of the present invention. It will be readily appreciated that branch substitutions, modifications and variations are possible.

1 is a cross-sectional view showing an image sensor having a conventional MIM capacitor;

2 is a view showing that voids are generated at a Cu / SiN interface after a SiN film is deposited on a copper plating film according to the related art.

3 is a view showing the formation of the lower electrode of the MIM capacitor by electroplating according to a preferred embodiment of the present invention;

4 is a flowchart illustrating a process of manufacturing a MIM capacitor according to a preferred embodiment of the present invention.

Claims (6)

Forming a first interlayer insulating film on a semiconductor substrate including an image sensor-related device and patterning the first interlayer insulating film through a damascene process; Forming a lower electrode and a lower metal interconnection through copper electroplating in which metal ions are added to the semiconductor substrate including the patterned first interlayer insulating layer; Forming a diffusion barrier over the lower electrode and the lower metal wire; Forming a metal wiring structure connected to the lower electrode and the lower metal wiring on the semiconductor substrate on which the lower electrode is formed; Method for manufacturing a semiconductor device comprising a. The method of claim 1, The manufacturing method is characterized in that the lower electrode and the lower metal wiring of Cu-Pb, Cu-Ti or Cu-Co are formed using the copper electroplating in which Pb, Ti or Co is added as the metal ions. The manufacturing method of the semiconductor element. The method according to claim 1 or 2, The said manufacturing method is a manufacturing method of the semiconductor element characterized by the density | concentration of the said metal ion having the range of 95 ppm-100 ppm. The method of claim 3, wherein The manufacturing method is a method of manufacturing a semiconductor device, characterized in that for adjusting the pH of the electrolyte for suppressing the H2 emission phenomenon generated during the copper electroplating. The method of claim 4, wherein The pH control method of manufacturing a semiconductor device, characterized in that carried out under the condition of 'pH> 6.0'. The method of claim 5, wherein The diffusion barrier is a SiN film or a SiC film, the manufacturing method of a semiconductor device.

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