KR20090065911A - Method for fabricating via hole using rie - Google Patents

Abstract

A method for forming a via hole using a reactive ion etch method is provided to improve reliability of electrical connection by forming an anisotropic via hole having a vertical wall surface. An insulating layer is formed on an upper part of a substrate. A mask having a through-hole of a via forming pattern is formed on the upper part of the substrate. The substrate including the mask is loaded between an upper electrode and a lower electrode of a vacuum chamber. A via hole is formed by performing a RIE(Reaction Ion Etching) process within the chamber. A plasma discharge process is performed within the chamber by injecting reactive gas into the inside of the vacuum chamber. A radical of an electron particle type is formed by performing the plasma discharge process. The radical is accelerated from the upper electrode to the lower electrode.

Description

Via hole formation method using reactive ion etching {Method for fabricating via hole using RIE}

The present invention relates to a method of forming a via hole, and more particularly, by placing a printed circuit board in which a mask is covered in a vacuum chamber to form a via hole by using reactive ion etching (RIE). The present invention relates to a via hole forming method using reactive ion etching for via hole processing.

In general, a printed circuit board (PCB) mounts many components of various types on a flat plate made of phenol resin or epoxy resin, and denses a circuit electrically connecting each component on the surface of the resin plate. As a fixed circuit board, a thin plate of copper or the like is laminated on one surface of a phenol resin insulator plate or an epoxy resin insulator plate, and then etched according to the wiring pattern of the circuit to form a necessary circuit and drill holes for attaching and mounting components. Manufacture by connecting electrically.

Recently, multilayer printed circuit boards having improved integration have emerged as electronic products are lighter and shorter, higher in density, packaged, and more portable, and fine patterns are also used in the multilayer printed circuit board. Miniaturization, miniaturization and packaging are in progress.

Therefore, even in the case of multilayer printed circuit boards, there is a tendency to change to a structure in which the layer structure of the circuit is combined with the change of raw materials in order to increase the fine pattern formation, the reliability, and the design density. As the type is changed from the surface mount technology (SMT) type, the design of the printed circuit board is complicated and a high degree of integration design technology is required.

Referring to Figure 1 below briefly described the manufacturing process of a conventional general printed circuit board as follows.

First, as shown in FIG. 1A, a copper clad laminate (CCL) 101 having a thin copper foil 102 formed on both surfaces thereof is provided through an insulating layer 103.

Here, the copper-clad laminate 101 is a disk made of a printed circuit board is generally a thin laminated plate with a thin copper coating on the insulating layer, depending on the purpose of the glass / epoxy copper laminated board, heat-resistant resin copper laminated board, paper / phenol copper laminated board There are many kinds of high frequency copper clad laminates, flexible copper clad laminates (polyimide films) and composite copper clad laminates, but glass / epoxy copper clad laminates are mainly used for double-sided PCBs and multilayer PCBs.

Thereafter, as shown in FIGS. 1B and 1C, after forming the via holes 104 for interlayer connection by drilling in the copper foil laminated disc 101, the electroless copper plating for the copper foil layers and via holes and Electrolytic copper plating is performed to form a copper plating layer 105.

Here, electroless copper plating is performed first and then electrolytic copper plating is performed because electrolytic copper plating that requires electricity cannot be performed on the insulating layer. That is, in order to form the electroconductive film required for electrolytic copper plating, electroless copper plating is thinly performed as the pretreatment. Since electroless copper plating is difficult to process and economically disadvantageous, it is preferable to form the conductive portion of the circuit pattern by electrolytic copper plating.

After the electroless and electrolytic copper plating is performed as described above, as shown in FIG. 1D, paste is applied to the inner region of the via hole to protect the electroless and electrolytic copper plating layer 105 formed on the inner wall of the via hole 104. Fill (106).

Here, the paste 106 generally uses an insulating ink material, but a conductive paste may also be used depending on the purpose of the printed circuit board. The conductive paste is obtained by mixing a metal such as Cu, Ag, Au, Sn, Pb as a main component alone or in an alloy form with an organic adhesive.

Subsequently, as shown in FIGS. 1E and 1F, an ultraviolet ray irradiation is performed on an artwork film having a predetermined circuit pattern to transfer the predetermined circuit pattern to the photosensitive dry film, thereby forming an etching resist pattern for forming an inner circuit pattern. After forming 107, by performing an etching process using a predetermined etching solution, the copper foil layer 105 in the region where the etching resist pattern 107 is not formed is removed to form a predetermined circuit pattern.

After forming the circuit pattern as described above, as shown in Figures 1g and 1h, after laminating by using Resin Coated Copper (RCC) or coreless (coreless) material on both sides of the substrate between the inner layer and the outer layer The blind via hole 110 which performs electrical connection is machined.

In this case, the blind via hole 110 may be a mechanical drilling method, a plasma etching method, a photo via method, a laser method, or the like. In particular, the laser method is the most widely used method for forming the blind via hole of the current printed circuit board. Excimer, Nd: YAG, and a method using a laser drill of the CO ₂ type, and the like, and the like, are typically suitable for the processing of micro blind via holes having a depth of less than 150㎛ and a diameter of 250㎛ or less.

Here, YAG laser is a laser capable of processing both the copper layer and the insulating layer, CO ₂ laser is a laser capable of processing only the insulating layer.

A via hole forming method of a printed circuit board using a conventional laser drill process is made of a circuit forming process through a desmear process and a copper plating process after the laser drill process.

Therefore, after the via hole is formed by using the laser drill as described above, as shown in FIGS. 1I and 1J, the outer layer 111 is laminated by the plating process, and then the inner layer 111 is formed on the outer layer 111. By forming the circuit pattern on the outer layer using the same method as the circuit pattern forming method, the production of the printed circuit board is completed.

However, the method of forming the via hole using the laser drill as described above requires additional facility investment, and the inner surface of the via hole is inclined at 3.5 to 5 ° as shown in FIG. 2 due to the effect of isotropic etching after laser processing. It is inevitably formed as an inclined surface having an angle θ.

2 is a partial cross-sectional view showing the shape of a via hole formed by a conventional via hole forming method.

If the via hole sidewall is formed as an inclined surface as in the prior art, resin may remain on the lower surface of the via hole during the via hole processing, and the electrical contact area may be reduced, resulting in a decrease in reliability when mounting components.

Accordingly, the present invention was devised to solve the above-mentioned disadvantages and problems in the conventional method of forming a via hole. A mask is formed on an insulating layer of a substrate to position a substrate inside a vacuum chamber, and within the chamber. It is an object of the present invention to provide a via hole formation method using reactive ion etching, in which active species are generated by plasma discharge and the via surface is etched to form via holes, thereby facilitating large-area via hole processing.

The object of the present invention is to load a substrate having an insulating layer formed therein, and to move it into a chamber, a substrate transferred into the chamber is positioned above the lower electrode, and a mask is moved onto the substrate to be seated on the substrate. Determining a degree of alignment between the substrate and the mask and maintaining the inside of the chamber in a vacuum state, injecting gas into the chamber, and plasma discharge by the gas injected into the chamber. Provided is a method of forming a via hole using reactive ion etching comprising the step of forming a sheet of paper and etching the substrate surface exposed through the mask to form a via hole.

In the step of moving the substrate into the chamber, the substrate is transferred into the chamber with a predetermined circuit pattern formed on the upper surface.

In addition, the substrate is mounted on a table to which a lower electrode is connected, and a mask having a through hole of a via hole pattern is covered by a preliminary design of via hole formation.

The gas injected into the chamber of the vacuum is a reactive gas, the reactive gas is plasma discharged into the chamber to form a radical, and the active species is at the lower electrode side, i.e., in the chamber, at the upper electrode inside the chamber. The insulating layer, which is the surface of the substrate exposed through the through-holes of the mask, is rapidly etched from top to bottom.

At this time, the reactive gas reacts the active species present in the plasma with atoms on the surface of the etching material to generate a volatile reaction product, and the reaction product is released from the surface of the substrate to allow etching.

As such, when the via hole is formed on the upper surface of the substrate by reactive ion etching, a separate desmear process is not required to remove the residue in the via hole after the laser drilling as in the prior art, and the tapered inclined surface of the inner wall of the via hole is perpendicular to each other. It can be formed as a wall surface.

In the method of forming a via hole using reactive ion etching according to the present invention, a mask is covered on an upper surface of a substrate on which an insulating layer is formed so that via holes are formed by reactive ion etching (RIE) in a chamber in a vacuum state. Via hole processing for interlayer connection can be easily performed without a process, and the wall surface is formed of anisotropic via holes in a vertical state, thereby improving reliability of electrical connection.

Matters relating to the operational effects including the technical configuration for the above object of the method for forming the via hole using the ion etching according to the present invention will be clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

First, FIG. 3 is a flowchart illustrating a method of forming a via hole according to the present invention. FIG. 4 is a schematic configuration diagram of a chamber for forming a via hole according to the present invention. FIG. 5 is an enlarged cross section of a substrate when forming a via hole according to the present invention. It is also.

As shown, the via hole forming method using the reactive ion etching of the present invention after the deposition of the substrate 20 in which the mask 21 is covered in the chamber 10 of the vacuum 10, the reactive gas is injected into the chamber 10 to react The via hole is formed by Reactive Ion Etching (RIE).

The substrate 20 stacked inside the vacuum chamber 10 has a predetermined circuit pattern formed on an upper surface thereof and is transferred into the chamber. Thus, the substrate 10 before being transferred into the chamber 10 has a predetermined size. After transferring the circuit pattern to the photosensitive dry film to form an etching resist pattern for forming the inner circuit pattern, the copper foil layer in the region where the etching resist pattern is not formed is removed by performing an etching process using an etching solution so that a predetermined circuit is removed. The pattern is conveyed in a formed state.

As described above, the substrate having the circuit pattern formed thereon is loaded and moved into the chamber 10, and is disposed on the upper surface of the table 40 positioned between the upper electrode 31 and the lower electrode 32 formed in the chamber 10. Are stacked.

In this case, the table 40 is electrically connected to the lower electrode 32, and the upper electrode 31 is disposed directly above the table 40.

Next, a mask 21 having a plurality of through holes 21a is covered on the upper surface of the substrate 20 which is moved into the chamber 10 and is seated on the table 40.

The mask 21 may be formed of a photoresist layer, and a plurality of through holes 21a designed according to a formation pattern of via holes to be formed on the substrate 20 are provided.

Next, the degree of alignment between the substrate 20 seated on the table 40 and the mask 21 disposed on the upper surface of the substrate 40 is determined, and the mask 21 and the substrate 20 for forming the via hole at the correct position. When the alignment is performed, the vacuum pump 50 attached to one side of the chamber 10 is operated to maintain the inside of the chamber 10 in a vacuum state.

At this time, the reactive gas is injected into the chamber 10 to form active species (radical, A) in the form of electron particles by plasma discharge in the chamber 10, and the active species (A) is the upper portion. The surface of the substrate 20 is accelerated from the electrode 31 to the lower electrode 32 and exposed through the through hole 21a of the mask 21.

Accordingly, the surface of the substrate 20 exposed through the through hole 21a of the mask 21 is changed into a volatile reaction product with active species A of the electron particles accelerated downward, and the reaction product is converted into a substrate. The via hole 22 is formed by the etching process of leaving off the surface of (20).

As such, a method of forming active species A by plasma discharge in the chamber by the reactive gas injected into the chamber 10 of vacuum is called Reaction Ion Etching (RIE). Acceleration of the active species A by ion etching allows a relatively large diameter via hole 22 to be formed on the substrate 20 while having a vertical wall.

Finally, when the via hole 22 is processed on the upper surface of the substrate 20 stacked in the chamber 10, the reactive gas is discharged in the chamber 10, and a mask ( After the 21 is removed, the substrate 20 in which the via hole 22 processing is completed is withdrawn in the chamber 10.

The via hole 22 formed on the substrate 20 through such a sequential process is not only capable of processing the via hole having a diameter larger than that of the via hole formed using a conventional laser drill, but also vertically without a separate desmear process. A via hole having a wall of can be easily formed.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

1 is a cross-sectional view showing a manufacturing process of a general printed circuit board.

Figure 2 is a cross-sectional view of the substrate at the time of conventional via hole formation.

3 is a flowchart disclosed in a method for forming a via hole according to the present invention.

4 is a schematic diagram of a chamber for forming a via hole according to the present invention;

Figure 5 is an enlarged cross-sectional view of the substrate when forming the via hole according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10. Chamber 20. Substrate

21.Mask 31.Top Electrode

32. Lower electrode 40. Table

50. Vacuum Pump

Claims (6)

A mask having a through hole of a via formation pattern is covered on an upper surface of a substrate having an insulating layer formed thereon, and the mask-covered substrate is seated between upper and lower electrodes in a vacuum chamber, and reactive ion etching is performed inside the chamber. A via hole forming method using reactive ion etching, characterized in that via holes are formed by (RIE: Reaction Ion Etching). The method of claim 1, Reactive gas is injected into the chamber of the vacuum to form active species (radical) in the form of electron particles that are accelerated from the upper electrode to the lower electrode by a plasma discharge in the chamber. Forming method. The method of claim 1, And the via hole is an anisotropic via hole having a vertical wall surface. Loading and moving the substrate on which the insulating layer is formed into the chamber; Placing the substrate transferred into the chamber above the lower electrode; Moving the mask over the substrate to be seated on the substrate; Determining an alignment degree between the substrate and the mask and maintaining a vacuum inside the chamber by operating a vacuum pump connected to one side of the chamber; Injecting gas into the chamber; And Active species are generated by plasma discharge by the gas injected into the chamber, and the substrate surface exposed through the mask is etched to form via holes; Via hole forming method using a reactive ion etching comprising a. The method of claim 4, wherein The gas injected into the chamber is a reactive gas, characterized in that via hole formation using a reactive ion etching. The method of claim 4, wherein And the via hole is an anisotropic via hole having a vertical wall surface.

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