KR20090065817A - Digital if design and verification method for high throught wireless communication system using multiple antenna - Google Patents

Abstract

A method for designing and verifying a DIF for a giga-class high speed wireless communication system using a multiple antenna is provided to transmit eight streaming signals at the same time by using eight multiple antennas. A high speed wireless communication system uses an orthogonal frequency division multiplex modulation mode. The high speed wireless communication system includes a multiple antenna. The high speed wireless communication system enhances frequency use efficiency by using a DIF(Digital Intermediate Frequency) structure applying a band expansion. The high speed wireless communication system includes a high speed data processing part which minimizes the number of connection lines of a base band module and a DIF module by using an ultra high speed module. The high speed wireless communication system supports a multiple antenna technique of a modem by applying a multiple DIF channel.

Description

DIIF DESIGN AND VERIFICATION METHOD FOR HIGH THROUGHT WIRELESS COMMUNICATION SYSTEM USING MULTIPLE ANTENNA}

The present invention relates to a DIF design and verification method for a giga-class high-speed wireless communication system using multiple antennas.

The present invention is derived from a study conducted as a part of the IT growth engine core technology development project of the Ministry of Information and Communication and the Ministry of Information and Telecommunication Research and Development.

Title: Development of 3Gbps 4G Wireless LAN System].

The present invention relates to a design and verification method of a digital intermediate frequency (DIF) module for a giga-class high-speed wireless communication system using an orthogonal frequency division modulation scheme and multiple antennas. In the past, academic research has been focused on multi-antenna technology capable of transmitting multimedia contents at high speed, and commercial products including multi-antenna such as WiBro and wireless LAN have recently begun to appear. However, two to three antennas are used as the number of transmit / receive terminals, and the bandwidth is not more than 40 MHz, and the transmission speed of several hundred mega-megabyte has become the limit channel capacity. Recently, Giga-class wireless communication in the VHT (Very High Throuhgput) task group As the research environment for the system is being created, it is necessary to design an ultra-high-capacity large-capacity DIF module structure capable of supporting such a modem technology. The present invention requires various signal processing techniques, including analog digital converters and digital analog converter technologies, ultrafast data signal processing technologies, and filter technologies.

 The present invention relates to a design and verification method of a digital intermediate frequency (DIF) module for a giga-class high-speed wireless communication system using an orthogonal frequency division modulation scheme and multiple antennas. Modulation such as 64-QAM (quadrature amplitude modulation) in the modem part by making the multi-band partitioning technology to improve the signal processing and the frequency efficiency of the multi-channel when applying the multi-antenna technology for high-speed data transmission with high reliability and performance The goal is to reduce the error rate to enable the method and to maintain maximum data throughput. In order to efficiently verify the DIF module with such a high speed interface and multi-channel and multi-band, it is designed from the structural design to the verification stage, and the various signal analysis techniques are used to complete the verification in a short time.

The present invention proposed to solve this problem by using a DIF structure and ultra-high speed module to which the band extension to improve the frequency usage efficiency in the high-speed wireless communication system having an orthogonal frequency division multiplexing modulation scheme as shown in FIG. A high-speed data processor that minimizes the number of connection lines between the baseband module and the DIF module and a method of increasing channel capacity by supporting multiple antenna technologies of a modem by applying multiple DIF channels.

In addition, the present invention is another feature of the design method of the ultra-high speed interface structure between the baseband module and the DIF module for designing a giga-class high-speed wireless communication system having multiple antennas as shown in FIGS.

In addition, in the high-speed wireless communication system having an orthogonal frequency division multiplexing modulation scheme and multiple antennas as shown in FIG. 4, the final filter data is added to each band and output through a digital analog converter in a desired band, and fine adjustment is performed. Another method is to adjust the power of the output signal of the digital analog converter.

In addition, the present invention generates test data through the loop back test board configuration and Flash RAM for the DIF test of the giga-class wireless communication system using multiple antennas as shown in Figs. Another feature is the method of receiving and testing the MICTOR connector.

In addition, the present invention is characterized by another method of compensating and demodulating the distorted received signal as shown in FIG. 7 to calculate the error value as a quantitative value and to numerically calculate the type and degree of the uncompensated offset.

Multi-antenna technology can increase the transmission rate by transmitting and receiving multiple streaming signals simultaneously with a plurality of transmission and reception antennas, but the complexity is significantly increased, difficult to implement. The present invention dramatically increases the transmission speed by implementing a technique of transmitting eight streaming signals simultaneously using eight multiple antennas, which have not been implemented in real time. The present invention relates to a design and verification method of a digital intermediate frequency (DIF) module for a giga-class high-speed wireless communication system using an orthogonal frequency division modulation scheme and multiple antennas. By applying the orthogonal frequency modulation method and the multi-antenna system using the invented system, the ubiquitous service that can utilize HD-quality video and high-definition content in a real-time wireless environment in home, office, and university classroom is realized.

1 is a block diagram showing the overall structure of a giga-class high-speed wireless communication system using an orthogonal frequency division modulation scheme and multiple antennas. Giga-class high-speed wireless communication system is composed of four layers. Server / application unit for displaying audio and video contents on PC or home appliances and portable video devices, and baseband unit for processing and demodulating data received from server / application to high-speed and reliable data, and receiving digital signals from baseband. It can be divided into a DIF unit which receives an analog signal or converts an analog signal from an RF unit into a digital signal, and an RF unit that is responsible for high frequency modulation and demodulation. The base band unit may be classified into a medium access control (MAC) unit for transmitting voice and video data according to a communication protocol, and a PHY unit performing digital modulation and demodulation to reliably and rapidly process data.

2 and 3 illustrate a structure of a transmitter and a receiver in a method for designing an ultrafast interface structure between a baseband module and a DIF module for designing a giga-class high-speed wireless communication system having multiple antennas, respectively. 2 and 3 are designed to be divided into n bands in the case of having m transmit antennas and m receive antennas so as to process signals with a low clock in DIF. For example, if a wireless communication system is designed to have eight transmit antennas and eight receive antennas for high-speed data transmission and a bandwidth of 120 MHz, m = 8 and n = 3 in this figure. At this time, if the digital analog converter is 12 bits and the analog digital converter uses 14 bits, the transmitter has a total of 40 MHz (operating speed) x 12 bits x 2 (I / Q) x 3 (band) x 8 (antenna number). It has a speed of 23.04 Gbps and a transmission rate of 7.68 Gbps for each band. The receiver has a total speed of 40MHz (operating speed) x 14bit x 2 (I / Q) x 3 (band) x 8 (antenna number) = 26.88 Gbps, and has a transmission rate of 8.96 Gbps for each band.

4 is divided into a frequency conversion filter unit of each band configured in 40 MHz units. It receives I, Q 40Mbps signals of multiple channels through modem and performs frequency conversion function using filter for each band step by step. At this time, the output of each band is added to the final filter data and output through the digital analog converter to the desired band, and the power of the output signal of the digital analog converter is adjusted through fine adjustment (FIG. 4 shows three signals at 120 MHz bandwidth. Shows the filter structure of the transmitter when divided into 40 MHz band and processed in the base band.)

5 and 6 are block diagrams of a loopback test board for DIF testing of a giga-class wireless communication system using multiple antennas. 5 and 6 are used for the operation and performance testing of the transmit and receive DIFs, respectively. The transmit DIF board test stores the test data through Flash RAM and passes the data through SRAM when the power is turned on. The receive DIF board test connects the transmit DIF board output to the input of the receive DIF board to receive the transmitted data so that the digitally converted signal can be observed with the logic analyzer through the MICTOR connector.

FIG. 7 illustrates a method of receiving a transmission signal of FIG. 5 through a MICTOR connector to a logic analyzer and analyzing it on a PC as shown in FIG. In the file stored as a text file (extension txt) or an Excel file (extension csv), a signal converted into a digital signal through a transmission DIF and a reception DIF is stored. In order to determine how much the received signal is distorted, a stepwise compensation algorithm is applied to calculate an error value of the finally corrected signal. In order, the “Load” step reads the stored received signal and the “dc cancel” step compensates for the DC on the board. In the “I / Q mismatch compensation” step, the Q channel gain or phase offset is compensated based on the I channel value. In the “Frame sync” phase, the symbol synchronization is synchronized by the correlation of the short preamble and the long preamble. In the “CFO correct” phase, the frequency offset is corrected by the phase offset obtained by the long preamble. In the “FFT” phase, the frequency domain signal is adjusted. It converts to a time domain signal and compensates for the phase offset estimated by the pilot signal in the phase correct phase. In the “Channel Equalization” step, the data is equalized with the channel estimate estimated by the long preamble to compensate for the distorted signal due to the channel. In the “Demapping” step, the original bit string is restored according to the modulation signal mode. In the “Characterization” step, the distortion level of the signal is calculated by EVM (Error Vector Magnitude), and the average deviation from the ideal signal is output. In addition, the Eigen Value Spread value can be obtained as a channel prediction result using a long preamble. This Eigen Value Spread value shows the correlation of multiple antenna arrays. You can also estimate the amount of offset that is not compensated for even though it is compensated by the modem algorithm.

8 shows the overall shape of the received signal and the restoration result. Figure 1 shows the magnitudes of the I and Q channels in the time domain. Figure 2 shows the power density of the complex signal. Figure 3 shows the constellation of the finally reconstructed signal. As a result, it can be seen that the EVM performance of -29dB is caused by the distortion of the transceiver. Fig. 4 shows the channel estimate obtained with the long preamble for channel estimation. 9 shows the analysis result of the signal-to-noise ratio. Fig. 5 shows the distribution of EVM for each receiving antenna. For example, eight multi-antennas are shown. Fig. 6 shows the symbol-specific EVM values for a particular antenna. Fig. 7 shows the signal-to-noise ratio in the frequency domain. Fig. 8 shows the signal-to-noise ratio in the time domain. 10 shows the correlation of preambles for symbol synchronization. Fig. 9 shows the correlation of the short preambles, Fig. 10 shows the correlation of the long preambles, and Fig. 11 shows the product of the correlations between the short preambles and the long preambles. At this point, synchronization occurs at the point with the largest value. FIG. 11 shows estimates for carrier phase (Fig 12), sampling phase (Fig 13), amplitude (Fig 14) and carrier frequency offset (Fig 15). In this way, the error that occurs during the modulation of the transmission signal and the error that may occur during the demodulation of the received signal, the quantization noise that may occur during the analog digital conversion and the digital analog conversion, and the sampling phase noise are obtained as quantitative values. Compensation allows verification and debugging to a degree that can be compensated for later in conjunction with the modem.

The present invention relates to a design and verification method of a digital intermediate frequency (DIF) module for a giga-class high-speed wireless communication system using an orthogonal frequency division modulation scheme and multiple antennas. In previous papers or studies on the theory of wireless communication using multiple antennas, a multi-antenna system aiming at a transmission rate of hundreds of megabits per second (bps) has a bandwidth of 40 MHz and mainly uses four or less antennas. While designed, the Giga-class wireless communication system uses more than eight antennas and combines and separates multiple 40 MHz bandwidths at the DIF, processing data at 40 MHz bandwidth separated in the baseband and an integrated 40 MHz multiple at RF. (E.g., 80MHz, 120MHz, etc.) is used to transmit data in the bandwidth. It also uses dozens of high-speed interfaces between the DIF and the baseband chip to reduce the baseband pin-to-chip pin count and ensure reliable data transfer. Giga-class high-speed wireless communication system is composed of four layers. The server / application unit that displays audio and video contents on a PC or home appliances and portable video devices, and the baseband unit that receives and processes the data received from the server / application and converts and demodulates it into high-speed, reliable data. It can be divided into a DIF unit for log-converting or receiving an analog signal from an RF unit and converting it into a digital signal and an RF unit for high frequency modulation and demodulation. The base band unit may be classified into a medium access control (MAC) unit for transmitting voice and video data according to a communication protocol, and a PHY unit performing digital modulation and demodulation to reliably and rapidly process data. The signal flow of the entire system receives high-speed data from the server through the wired network, generates headers in the MAC format for protocols, attaches them to the front of the data, and attaches error code check codes for error checking. The MAC frame with the header and the error check code is transmitted to the PHY transmitter, and the scrambling unit mixes the data pattern to reduce the error caused by the PAPR, the channel coding unit for restoring the error occurring in the channel, and the continuous error in the PHY. The interleaving unit reduces the errors for the IF, the IFFT unit for high-speed and efficient data transmission, and the modulator unit to increase the data transmission rate. The filter is then passed to the digital IF unit. To signal. (For example, a signal with a 120MHz band width is raised to an 80MHz IF stage to deliver a signal to the RF stage.) The RF stage receives the signal and modulates it to a high frequency band and delivers it to the antenna. The receiving end down-converts the signal input through the antenna from the RF receiving unit to the baseband. At this time, in order to simplify the receiving RF structure, the receiving end modulates the signal into the baseband by a direct conversion method without passing through the IF. Detect and decode the signal through the FFT block through the digital front end, which handles gain adjustment and synchronization by separating the signal coming in multiples of 40MHz band from the receiving digital IF stage and making it into a plurality of 40MHz bands. The channel coded signal is then decoded. When the hardware finds that the error code is not an error, the MAC stores it in memory, extracts the header information, sends it to the application, and outputs it to the screen for video and audio for the speaker.

The transmitter receives m channel I and Q data with low operating frequency (eg 40MHz) from the modem board in LVTTL format, and transmits them through the high speed cable to the transmitting DIF board through the high speed interface board. At this time, the data input to the transmitting DIF is converted into an analog signal through a digital analog modulator (DAC) by performing signal processing such as filter, complex modulation, and gain control corresponding to each band.

The receiver receives the analog baseband signal received from the RF module through an analog digital converter (ADC) and receives the signal modulated into a digital signal from the receiving DIF board. Filters each band data to filter, NCO modulation, and gain. Signal processing such as adjustment is performed. The final signaled data is transferred from the high speed interface board to the modem via a high speed cable. At this time, the transmitted high-speed data is transferred to the m channel I and Q channels having a low operating frequency through the high speed interface board mounted in the modem.

1 is a block diagram showing the overall structure of a giga-class high-speed wireless communication system using an orthogonal frequency division modulation scheme and multiple antennas.

Claims (5)

In the high-speed wireless communication system having an orthogonal frequency division multiplexing modulation scheme and multiple antennas as shown in FIG. A method of increasing channel capacity by supporting multiple antenna technology of a modem by applying a high speed data processor and multiple DIF channels. 2 and 3, a method for designing an ultrafast interface structure between a baseband module and a DIF module for designing a giga-class high-speed wireless communication system having multiple antennas as shown in FIGS. In the high-speed wireless communication system having an orthogonal frequency division multiplexing modulation scheme and multiple antennas as shown in FIG. 4, the output of each band is added to the final filter data and output through a digital analog converter in a desired band, and the digital analog converter through fine adjustment. How to adjust the power of the output signal. As shown in FIGS. 5 and 6, a loopback test board configuration for a DIF test using a multiple antenna and a test data are generated through a flash RAM and transmitted through an SRAM, and a receive DIF output is received through a MICTOR connector. How to test. A method of compensating and demodulating a distorted received signal as shown in FIG. 7 to calculate an error value quantitatively and numerically calculating the type and degree of an uncompensated offset.

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