KR20090064709A - Parity check matrix generating apparatus and method for ldpc code, and ldpc encoding/decoding apparatus using the same - Google Patents

Abstract

An apparatus and a method for generating a parity check matrix of an LDPC code and an LDPC encoding/decoding apparatus using the same are provided to perform a super speed decoding by designing an LDPC code supporting various information lengths and a code rate applying an information shortening method and a puncturing method. A first parity check matrix generating unit(31) generates a first parity check matrix comprised of a first information block and a parity block. A q-th parity check matrix generator generates the q-th parity check matrix by adding the q-th information block to the (q-1)-th parity check matrix. An information shortening unit(36) generates at least one parity check matrix different from the first to Q parity check matrixes by applying the information shortening to at least one parity check matrix among the first to Q parity check matrixes. A puncturing unit(37) generates at least one parity check matrix different from the first to Q parity check matrixes by applying a puncturing method to at least one parity check matrix among the first to Q parity check matrixes.

Description

Parity check matrix generating apparatus and method thereof for LDPC code, and LDPC code encoding / decoding apparatus using the same {parity check matrix generating apparatus and method for LDPC code, and LDPC encoding / decoding apparatus using the same}

The present invention relates to an error correction code technology of a wired / wireless communication system, and more particularly, to low density parity check having a variable information length and a variable code rate having a simple encoding and fast decoding convergence rate. Parity Check, hereinafter referred to as " LDPC " code, a parity check matrix generating apparatus and method thereof for LDPC codes, and an LDPC code / decoding device using the same.

The present invention is derived from the research conducted as part of the IT growth engine technology development project of the Ministry of Information and Communication and the Ministry of Information and Communication Research and Development. [Task Management No .: 2006-S-002-02, Title: Development of 3Gbps 4G Wireless LAN System] ].

Transmitted signals on wired / wireless communication systems experience noise, interference, and fading on a transmission channel, which causes a receiver to demodulate the transmitted signals. It happens that you can't.

There are various techniques for reducing the error rate that increases as the transmission speed increases, but one of the typical techniques uses an error correction code. Recently, error correction codes have been applied to almost all wireless communication systems. Especially, LDPC codes have been spotlighted as error correction codes for next generation high capacity wireless communication systems in that they can implement high speed decoder with low complexity as well as excellent error correction performance. I am getting it.

As a decoding method for an LDPC code, there are a decoding method using a serial or partial parallel processing method and a decoding method using a parallel processing method. The former method (a decoding method using serial or partial parallel processing) uses a small number of common variable node processing blocks and a common check node processing block repeatedly, thereby reducing hardware size. There is an advantage, but there is a disadvantage that can not support fast decoding. On the other hand, the latter method (a decoding method using a parallel processing method) can support fast decoding by performing parallel information exchange with a variable node processing block and a check node processing block optimized for each parity check matrix. However, there is a disadvantage in that the hardware size is large, and the support of various code rates causes an increase in hardware size.

On the other hand, in order to perform a hybrid automatic repeat request (H-ARQ), or to apply a modulation and coding scheme (Modulation and Coding Scheme: hereinafter referred to as "MCS") to the channel state, The wireless communication system needs to use an error correction code having a variable information length and a variable code rate. Conventional decoding methods for supporting various MCS levels in response to these requirements, a method for separately implementing a decoder optimized for each information length and code rate, using one hardware, information shortening technique or There is a way to apply the drilling technique. However, the former method (implementing a decoder that is optimized for each information length and code rate separately) has a disadvantage in that the hardware size is increased. The latter method (using one hardware, but using information shortening or puncturing) The method of application) is disadvantageous in that random application of the information shortening technique or the parity puncturing technique causes severe degradation of the error correction performance of the LDPC code.

As described above, a parallel decoding method is advantageous for a high-speed wireless communication system requiring several gigabytes (G) of processing speed, and an excellent error correction method for effectively applying a recent adaptive modulation and coding technique. LDPC codes of variable information length and variable code rate with capability are required. In addition, the complexity of encoding / decoding of the LDPC code should be small. However, processing all the LDPC codes in parallel is not easy because of the random connection complexity between the variable node and the check node.

Therefore, there is a demand for a partial parallel processing method and apparatus having a maximum possible decoding processing speed and a complexity that can be implemented. It is an object of the present invention to solve such a demand.

Accordingly, the present invention provides an apparatus and method for generating a parity check matrix of an LDPC code, and an LDPC code for providing an LDPC code having a variable information length and a variable code rate and having a constraint condition for simple encoding and fast decoding convergence speed. The purpose is to provide a decoding / decoding device.

That is, the present invention provides an LDPC code parity check matrix generation apparatus for providing an LDPC code having a low complexity of encoding / decoding, a fast decoding convergence speed, and excellent error correction performance that supports variable information length and variable code rate. And a method thereof and an LDPC encoding / decoding device using the same.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention which are not mentioned above can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

In the parity check matrix generating apparatus of the present invention for achieving the above object, in the parity check matrix generating apparatus of a Low Density Parity Check (LDPC) code, generating a first parity check matrix composed of a first information block and a parity block Means for generating a first parity check matrix; And q-th parity check matrix generating means for generating a q-th parity check matrix by adding a q-th information block to the generated q-1 (1 <q≤Q, Q is a natural number of 2 or more) parity check matrices. .

The apparatus for generating a parity check matrix according to the present invention may be different from the first through Q parity check matrices by applying information shortening to at least one parity check matrix of the first to Q parity check matrices. And information shortening means for generating at least one parity check matrix.

The apparatus for generating a parity check matrix according to the present invention may be further configured by applying a puncturing technique to at least one parity check matrix among the first to Q th parity check matrices. Puncturing means for generating a parity check matrix of.

On the other hand, another parity check matrix generating apparatus of the present invention for achieving the above object comprises: a parity check matrix generating apparatus of an LDPC code, comprising: basic parity check matrix generating means for generating at least one basic parity check matrix; And applying row decomposition to the information block of the basic parity check matrix generated by the basic parity check matrix generating means and extending the parity block of the basic parity check matrix generated by the basic parity check matrix generating means to at least one extended parity check. Extended parity check matrix generating means for generating a matrix.

The apparatus for generating another parity check matrix according to the present invention further includes applying the information shortening to at least one of the basic parity check matrix and the extended parity check matrix to apply the basic parity check matrix and the extended parity check matrix. And information shortening means for generating at least one parity check matrix different from.

The apparatus for generating another parity check matrix according to the present invention is different from the basic parity check matrix and the extended parity check matrix by applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix. Puncturing means for generating at least one parity check matrix.

On the other hand, the LDPC coding apparatus of the present invention for achieving the above object, in the LDPC coding apparatus, a parity check matrix for selecting a parity check matrix corresponding to an input coding parameter from a plurality of parity check matrix. Selection means; And encoding means for encoding an input word based on the parity check matrix selected by the parity check matrix selecting means, wherein the plurality of parity check matrices comprise a first information block and a parity block. And a qth parity check matrix in which a q-th information block is added to the first parity check matrix and the q-1 (1 <q≤Q, Q is a natural number of 2 or more) parity check matrices.

On the other hand, another LDPC encoding apparatus of the present invention for achieving the above object, in the LDPC encoding apparatus, parity for selecting a parity check matrix corresponding to an input coding parameter from a plurality of parity check matrix. Check matrix selecting means; And encoding means for encoding an input word based on the parity check matrix selected by the parity check matrix selecting means, wherein the plurality of parity check matrices include at least one basic parity check matrix; And at least one extended parity check matrix generated by applying row decomposition to the information block of the basic parity check matrix and extending the parity block of the basic parity check matrix.

On the other hand, the LDPC decoding apparatus of the present invention for achieving the above object, in the LDPC decoding apparatus, a parity check matrix for selecting a parity check matrix corresponding to an input decoding parameter from a plurality of parity check matrix. Selection means; And decoding means for decoding a received codeword based on the parity check matrix selected by the parity check matrix selecting means, wherein the plurality of parity check matrices comprise a first information block and a parity block. And a qth parity check matrix in which a q-th information block is added to the first parity check matrix and the q-1 (1 <q≤Q, Q is a natural number of 2 or more) parity check matrices.

Meanwhile, another LDPC decoding apparatus of the present invention for achieving the above object includes a parity check for selecting a parity check matrix corresponding to an input decoding parameter among a plurality of parity check matrices in the LDPC decoding apparatus. Matrix selection means; And decoding means for decoding a received codeword based on the parity check matrix selected by the parity check matrix selecting means, wherein the plurality of parity check matrices include at least one basic parity check matrix; And at least one extended parity check matrix generated by applying row decomposition to the information block of the basic parity check matrix and extending the parity block of the basic parity check matrix.

On the other hand, the parity check matrix generation method of the present invention for achieving the above object, in the parity check matrix generation method of the LDPC code, a first parity check to generate a first parity check matrix consisting of a first information block and a parity block Matrix generation step; And a q-th parity check matrix generation step of generating a q-th parity check matrix by adding a q-th information block to the generated q-1 (1 <q≤Q, Q is a natural number of 2 or more) parity check matrices.

The parity check matrix generation method of the present invention may differ from the first through Q parity check matrices by applying information shortening to at least one parity check matrix of the first through Q parity check matrices. And an information shortening step of generating at least one parity check matrix.

The method of generating a parity check matrix according to the present invention may include applying a puncturing technique to at least one parity check matrix of the first to Q parity check matrices, and at least different from the first to Q th parity check matrix. And a puncturing step of generating one parity check matrix.

On the other hand, another method for generating a parity check matrix of the present invention for achieving the above object, the parity check matrix generation method of the LDPC code, comprising: generating a basic parity check matrix for generating at least one basic parity check matrix; And generating an at least one extended parity check matrix by applying row decomposition to the information block of the generated basic parity check matrix and extending the parity block of the generated basic parity check matrix.

The method for generating another parity check matrix according to the present invention may further include applying the information shortening to at least one of the basic parity check matrix and the extended parity check matrix. And an information shortening step of generating another at least one parity check matrix.

In addition, another parity check matrix generation method of the present invention is different from the default parity check matrix and the extended parity check matrix by applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix. The method further includes a puncturing step of generating at least one parity check matrix.

As described above, the present invention can easily implement a decoder having a variable information length and a variable code rate using only one piece of hardware in a partial parallel processing scheme, and has an effect of performing ultrafast decoding.

In addition, the present invention has the effect of generating an LDPC code supporting variable information length and variable code rate with simple encoding and fast decoding convergence speed while having excellent error correction performance.

In addition, the present invention can easily implement a high-speed LDPC decoder, there is an effect that can easily implement a hardware that performs fast decoding.

As a result, the present invention has a low complexity for encoding / decoding, and can provide a variable information length and variable code rate LDPC code with excellent error correction and detection of error performance. Can be.

The above objects, features, and advantages will become more apparent from the detailed description given hereinafter with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention pertains may share the technical idea of the present invention. It will be easy to implement. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The LDPC code is a code introduced by "Gallager". The LDPC code is defined as a parity check matrix with a very small number of elements having a value of 1 and most of the remaining elements have a value of 0.

LDPC codes are roughly divided into regular LDPC codes and irregular LDPC codes. The uniform LDPC code is an LDPC code proposed by "Gallager", and all rows in the parity check matrix have the same number of 1s as elements, and all columns have the same number of 1s as elements. In contrast, there are rows including different numbers of 1's or columns including different numbers of 1's in the parity check matrix of the non-uniform LDPC code. In general, it is known that the error correction performance of a nonuniform LDPC code is superior to a uniform LDPC code.

On the other hand, "Fossorier" is a quasi-cyclic representation of an element of the parity check matrix as an identity matrix and a zero matrix instead of 0 and 1, which are elements on GF (2). LDPC codes (“Quasi-cyclic low density parity check codes from circulant permutation matrices”, IEEE Trans. Inform. Theory, vol. 50, pp. 1788-1794, Aug. 414) have been proposed.

Hereinafter, in the embodiment of the present invention, the technical idea of the present invention will be described only when the quasi-cyclic LDPC code is used. In addition to the quasi-cyclic LDPC code, the present invention describes elements of the parity check matrix in the GF (2). Applicability to one LDPC code will be understood by those skilled in the art.

In the following embodiments of the present invention, the technical spirit of the present invention will be described by fixing the size of sub-matrix, the number of sub-matrix, the order distribution of parity check matrix, etc. Modified information length through a method of modifying the length of a sub-matrix, a method of modifying the number of submatrices used, and a modified information bit row decomposition method according to a degree distribution of a parity check matrix. And how to obtain the code rate is also within the scope of the present invention will be fully understood by those skilled in the art.

Equation 1 below illustrates 5 × 5 cyclic-permutation matrices.

As illustrated in [Equation 1], it can be seen that the sub-matrix Si is obtained by cyclic shifting the columns of the unit matrix to the right by i.

Hereinafter, in order to explain the technical idea of the present invention, a parity check matrix composed of 38 × 38 sub-matrix will be used as an example. In this case, the sub-matrix is a matrix obtained by applying cyclic shift to a 38x38 unit matrix (i.e., a cyclic permutation matrix) and a 38x38 zero matrix.

Table 1 below is a table including LDPC parity check matrices according to an embodiment of the present invention.

information length (bits) k code rate R codeword length (bits) n parity length (bits) n-k parity check matrix H 456 1/2 912 456

456 1/3 1368 912

456 1/4 1824 1368

456 1/5 2280 1824

912 2/3 1368 456

912 1/2 1824 912

912 2/5 2280 1368

912 1/3 2736 1824

1368 3/4 1824 456

1368 3/5 2280 912

1368 1/2 2736 1368

1368 3/7 3194 1824

1824 4/5 2280 456

1824 2/3 2736 912

1824 4/7 3194 1368

1824 1/2 3648 1824

2280 5/6 2736 456

2280 5/7 3194 912

2280 5/8 3648 1368

2280 5/9 434 1824

The 20 LDPC parity check matrices in the table of Table 1 are generated according to the parity check matrix generation method of the present invention, and use 456, 912, 1368, 1824, and 2280 bits as information lengths, and 456 as parity lengths. By using 912, 1368, and 1824 bits, each combination of information length and parity length can be used to implement a sub / decoder that supports variable information length and variable code rate with 20 simple encoding and fast decoding convergence rates. Can be.

FIG. 1 is a diagram for structurally explaining a relationship between parity check matrices illustrated in the table of [Table 1].

In FIG. 1, a small square is a 456 × 456 matrix, and C ⁱ _j blocks and P ⁱ blocks described in Table 1 and FIG. 1 refer to information blocks and parity blocks that form part of a parity check matrix, respectively. Description will be described later using [Equation 2] to [Equation 8] and [Equation 12].

In general, in the case of LPDC code, a parity check matrix having excellent error correction performance is generated through an optimization design for order distribution of a parity check matrix and an optimization design for cycle distribution on a factor graph. Since the parity check matrices used in the present invention are correlated with each other (to be described later), the optimization design should be performed on all parity check matrices simultaneously without performing an optimization design on each parity check matrix. do. In addition, the optimization of the parity check matrix should be performed using the constraints of the present invention having simple encoding and fast decoding convergence speed.

Equation 2 below is a formula for illustrating a parity check matrix that supports five code rates with a parity length of 456 bits, and represents H ¹ of FIG. ¹ .

Equation 3 below is a formula for illustrating the matrix P ¹ which is a parity block of the parity check matrix of Equation 2 above.

On the right side of Equation 3, "-" represents a matrix of 38 x 38, and "i" represents a cyclic permutation matrix S _i of 38x38. Parity blocks P ¹ exemplified in Equation 3 are (m, m-1) and (0, 0), (6, 0), (11, 0) positions and 1≤m≤11 while ( The m mod 38 cyclic-permutation matrix is included as an element at the positions m and m, and the zero matrix is included in the remaining positions. That is, in the case of a non-zero cyclic permutation matrix, the remaining value obtained by dividing the row value of the base matrix by 38 is included as an element of the cyclic permutation matrix. The reason for designing the parity check matrix is because the constraint is placed so that the values of the cyclic permutation matrixes that are not the same matrix of the same column of the base matrix are not equal. Such a constraint is commonly applied to a parity block or an information block, and according to this constraint, a parity check matrix having a simple encoding and fast decoding convergence rate can be obtained.

The parity check matrix designed as an example in the present invention is an example in which not only the values of the non-zero cyclic permutation matrix corresponding to the same column of the base matrix but also the remaining values divided by 19 are not equal. Such constraints can be useful when doubling the complexity and doubling the convergence speed of the decoder, or when increasing or decreasing the size of the sub-matrix by twice.

Such a parity block P ¹ is a special case of a double diagonal parity block, and can be applied to an implementation of a parallel processing LDPC encoder in units of partial blocks. When using this type of parity block, coding complexity can be minimized. That is, the parity block P ¹ is sufficient if the matrix satisfies the linearly independent condition, but in particular, as designed in the present invention, P ¹ is divided into matrices satisfying 38 independent linear independence. By using a parity block of the type illustrated in [Equation 3], a decoder having a lower complexity and a decoder having a faster decoding convergence rate can be implemented.

For a detailed description of the double diagonal parity block, see "Efficient Encoding of Low-Density Parity-Check Codes", IEEE Trans. On Inform. Theory, Vol. 47, No. 2, Feb. 411), the description thereof will be omitted here.

Equations 4 to 8 below illustrate C ¹ ₀ , C ¹ ₁ , C ¹ ₂ , C ¹ ₃ , and C ¹ _4, which are the first to fifth information blocks of Equation 2; Is a formula.

The integer largely expressed on the right side of [Equation 4] to [Equation 8] represents a cyclic permutation matrix obtained by right-circulating a unit matrix of 38 × 38 by the integer, and “-” denotes Equation 3 above. ], A matrix of 0 is 38x38. For example, in Equation 4, 37 ¹ represents a cyclic permutation matrix S ₃₇ .

In addition, the exponent on the right side of Equations 4 to 8 is row-rowed to the first to fifth information blocks of Equation 2 according to an embodiment of the present invention. splitting) is used to generate information blocks included in the parity check matrices H ² , H ³ , and H ⁴ of Equations 9 to 11 described below. Description of the row decomposition will be described later with reference to [Equation 12].

은 456비트인 정보 길이와 1/2인 부호율을 가진 LDPC 부호의 부/복호화에 사용된다.Parity check matrix consisting of C ¹ ₀ as the first information block illustrated in Equation 4 and parity block P ¹ illustrated in Equation 3 above.

Is used for encoding / decoding of LDPC codes having an information length of 456 bits and a code rate of 1/2.

은 912비트인 정보 길이와 2/3인 부호율을 가진 LDPC 부호의 부/복호화에 사용된다.Similarly, a parity check made up of C ¹ _{0 ,} C ¹ _{1 ,} which are the first and second information blocks illustrated in Equations 4 and 5 _, and parity block P ¹ illustrated in Equation 3, respectively. procession

Is used to encode / decode an LDPC code having an information length of 912 bits and a code rate of 2/3.

은 1368비트인 정보 길이와 3/4인 부호율을 가진 LDPC 부호의 부/복호화에 사용된다.Similarly, C ¹ _{0 ,} C ¹ _{1 ,} C ¹ _{2 ,} which are the first to third information blocks illustrated in Equations 4 to 6 _, and the parity block P ¹ illustrated in Equation 3 above. Parity check matrix

Is used for encoding / decoding of LDPC codes having an information length of 1368 bits and a code rate of 3/4.

은 1824비트인 정보 길이와 4/5인 부호율을 가진 LDPC 부호의 부/복호화에 사용된다.Similarly, C ¹ _{0 ,} C ¹ _{1 ,} C ¹ _{2 ,} C ¹ _{3 ,} which are the first to fourth information blocks illustrated in Equations 4 to 7 _, and Equation 3 illustrated above. Parity check matrix consisting of parity block P ¹

Is used for encoding / decoding of LDPC codes having an information length of 1824 bits and a code rate of 4/5.

은 2280비트인 정보 길이와 5/6인 부호율을 가진 LDPC 부호의 부/복호화에 사용된다.Similarly, C ¹ _{0 ,} C ¹ _{1 ,} C ¹ _{2 ,} C ¹ _{3 ,} C ¹ _{4 ,} which are the first to fifth information blocks illustrated in Equations 4 to 8 _{, respectively.} And a parity check matrix composed of parity blocks P ¹ illustrated in Equation 3 above.

Is used for encoding / decoding of LDPC codes having an information length of 2280 bits and a code rate of 5/6.

As described above, the parity check matrix designed as illustrated in Equations 4 to 8 to obtain a fast decoding convergence rate is a value of only the cyclic permutation matrix, not the zero matrix corresponding to the same column of the base matrix. Rather, the values divided by 19 are the same. Such constraints can be useful when doubling the complexity and doubling the convergence speed of the decoder, or when increasing or decreasing the size of the sub-matrix by twice.

Meanwhile, the matrixes of Equations 3 to 8 are exemplary matrices used to explain the technical idea of the present invention, and the equations 3 to 3 are optimized through optimization of order distribution and cycle distribution. It will be understood by those skilled in the art that in addition to the matrix illustrated in Equation 8, various matrices having the matrix sizes of Equations 3 to 8 can be generated.

To the [equation 9] to [expression 11] are each 912-bit, 1368-bit, 1824 bit is a formula that has a parity length illustrating a parity check matrix supporting five code rate, each of Fig. H ² 1 , H ³ and H ⁴ are shown.

Information blocks of H ² , H ³ , and H ⁴ are generated by applying the row decomposition illustrated by Equation 12 to H ¹ information blocks. That is, C ^j _i (where j = 2, 3, 4, i = 0, 1, 2, 3, 4) is obtained by applying a row decomposition to C ¹ _j . For example, C ³ ₂ in the above [Equation 10] is obtained by applying a row decomposition to C ¹ ₂ .

In addition, parity blocks of H ² , H ³ , and H ⁴ are generated by extending the parity blocks of H ¹ into the same structure. That is, parity blocks P ² of Equation 9 are (0, 0), (12, 0), (23, 0), and (m, m-1) and ( By including the m mod 38 cyclic permutation matrix as an element at the position of m, m) and the zero matrix at the remaining positions, the parity block P ¹ illustrated in [Equation 3] Has the same structure as In addition, parity block P ³ of Equation 10 is (0, 0), (18, 0), (35, 0) and (m, m-1) and (1) while 1≤m≤35. By including the m mod 38 cyclic permutation matrix as an element at the position of m, m) and the zero matrix at the remaining positions, the parity block P ¹ illustrated in [Equation 3] Has the same structure as Similarly, parity blocks P ⁴ of Equation (11) also have (m, m-1) and ((0, 0), (24, 0), (47, 0) positions and 1≤m≤47 while By including the m mod 38 cyclic permutation matrix as an element at the position of m, m) and the zero matrix at the remaining positions, the parity block P ¹ illustrated in [Equation 3] Has the same structure as

,

,

,

,

등은 상기 [표 1]에 기재된 해당 정보 길이 및 해당 부호율을 지원할 수 있다.Parity check matrix obtained through this process

,

,

,

,

Etc. can support the corresponding information length and corresponding code rate described in [Table 1].

Generating a, the [equation 4] to each information block of the formula 8 in the index by decomposing line for each information block the H ¹ parity check matrix, the parity check matrix H ^2, H ^3, H ^4, as described above It is used to The row decomposition according to one embodiment of the present invention is performed using Equation 12 below.

That is, [Equation 12] represents a formula representing the row decomposition method according to an embodiment of the present invention. In Equation 12, the value "-1" in g ^k _i (-1) = -1 represents a zero sub-matrix.

In addition, in Equation 12, c _mn (where m = 1,2, ..., M, n = 1,2, ..., N) is an information block of MN submatrices. Indicates a submatrix at position (m, n). When C in f _i (C) of Equation 12 is the information block C ¹ ₀ shown in Equation 4, M = 12, N = 12, and c ₁₂ is 27 ⁰ .

As described above, there are three embodiments of the present invention for designing an LDPC code having a variable information length and a variable code rate. The first embodiment is a method of generating a new parity check matrix different from the parity check matrix in terms of information length or code rate by adding a second information block to a parity check matrix including a first information block and a parity block. In the second embodiment, when there is a parity check matrix composed of a basic information block and a basic parity block, the extended information block is generated by applying row decomposition to the basic information block, and the basic parity block is extended to have the same structure as the basic parity block. By generating an extended parity block, a new parity check matrix is generated which is different from the basic parity check matrix in terms of information length or code rate. The third embodiment combines the first and second embodiments described above.

In the embodiment of the present invention, the information block to be subjected to row decomposition is called a basic information block, and the information block obtained as a result of the row decomposition is called an extended information block. In an embodiment of the present invention, the parity block to be extended is referred to as a basic parity block, and the parity block as a result of the expansion will be referred to as an extended parity block.

In detail, the parity check matrices are generated by expanding the information block while the parity block is fixed, and the information block is extended to generate an excellent parity check matrix in terms of order distribution and cycle distribution.

In further detail, the second embodiment generates an extended parity check matrix different from the basic parity check matrix by performing row decomposition of the information block included in the basic parity check matrix. Here, a row decomposition method is applied to generate an excellent parity check matrix in terms of order distribution and cycle distribution.

Meanwhile, in the embodiments of the present invention, the three embodiments will be described as a reference for generating a parity check matrix having a large size from a parity check matrix having a small size, but a reverse process thereof may be possible to those skilled in the art. Can be. That is, in the first embodiment, there may exist a method of generating a parity check matrix having a small size by generating a parity check matrix having a large size and then removing some information blocks from the generated parity check matrix. In addition, in the second embodiment, after generating a basic parity check matrix of a large size, a row combining, which is an inverse process of row decomposition, is applied to the information block of the generated basic parity check matrix, and the generation By applying parity part switching using only a part of the parity block of the basic parity check matrix, the reduced parity check matrix corresponding to the above-described extended parity check matrix can be generated. Here, the row combination for the information block may be expressed as parity combining of the parity part, and the parity part switching may be expressed as parity combining of the parity part. .

On the other hand, by applying the information shortening technique and puncturing technique to the method of the present invention for designing the above-described LDPC code having a variable information length and variable code rate, it is possible to design an LDPC code that supports a variety of information length and code rate.

2 is a diagram illustrating a concept of applying an information shortening technique and a puncturing technique to a parity check matrix according to the present invention.

Specifically, an example in which an information shortening by kk _eff bits and puncturing for n _p parity bits is applied to a parity check matrix having a size of k × n shown in the upper right of FIG. 2. Here, a parity check matrix of size k × n basically supports a code rate of k / n and an information length of k.

The upper left vector is an input message vector having a size of k × 1, and is composed of an information word composed of k _eff information bits and kk _eff zeros filled with information shortenings. That is, the information length according to the embodiment of the present invention is k _eff . This input message vector is multiplied by the parity check matrix to produce an n-bit codeword. Then, in the generated codeword, n _p parity bits are punctured, and the kk _eff zeros previously filled are also deleted. As a result, the length of the codeword finally becomes n-k + k _eff -n _p . Therefore, in this case, the code rate of k / n and the information length of k _eff and k _eff / (n-k + k _eff -n _p ) which are different from the code rate of k / n provided by the parity check matrix and k information length are basically provided. Can provide.

Meanwhile, although FIG. 2 illustrates a case where information shortening and puncturing for parity bits are applied, in addition to these embodiments, an embodiment using only information shortening and an embodiment using only puncturing for information bits are also possible. Effective utilization can support a wider variety of information lengths and code rates.

In addition, in the above-described embodiment, zero padding is performed before the product of the input message vector and the parity check matrix, and perforation is performed after the product of the input message vector and the parity check matrix, thereby reducing information without modifying the parity check matrix. The manner of carrying out the puncture has been described. However, in addition to this method, information reduction and puncturing is applied to the parity check matrix itself to generate a new parity check matrix of size k _effx (n-k + k _eff -n _p ) and the generated parity check matrix and information length k _effx. There is also a method of generating a codeword having a codeword length of n-k + k _eff -n _p by multiplying with an input message vector of one. The latter method k _effx (n-k + k _eff -n _p ) by removing the leftmost k _eff columns, the rightmost n _p columns, and the top k _eff rows from the parity check matrix of size k × n. A parity check matrix of magnitude is obtained.

Those who are in this field can easily perform the encoding / decoding of the LDPC codes proposed by the present invention by applying various known encoding / decoding techniques of LDPC codes. The description will be omitted.

3 is a block diagram of an apparatus for generating a parity check matrix according to an embodiment of the present invention.

As shown in FIG. 3, the apparatus for generating a parity check matrix according to the present invention includes a first parity check matrix generator 31 for generating a first parity check matrix including a first information block and a parity block, and generation. Q-th parity check matrix generators 32 to 35 for generating a q-th parity check matrix by adding the q-th information block to the received q-1 (1 <q≤Q, where Q is a natural number of 2 or more) parity check matrix It includes.

The apparatus for generating a parity check matrix according to the present invention is different from the first through Q parity check matrices by applying information shortening to at least one parity check matrix of the first through Q parity check matrices. The apparatus further includes an information shortening unit 36 for generating at least one parity check matrix.

In addition, the apparatus for generating a parity check matrix according to the present invention may apply a puncturing technique to at least one parity check matrix of the first to Q th parity check matrices, and at least different from the first to Q th parity check matrices. It further includes a perforation portion 37 for generating one parity check matrix.

Here, the q th parity check matrix generators 32 to 35 perform an optimization of constraint conditions, degree distribution, and cycle distribution for simple encoding and fast decoding convergence speed. Create a parity check matrix.

3 will be described in detail with reference to [Equation 2] to [Equation 8].

The first parity check matrix generator 31 includes a first parity check including C ¹ ₀ , which is the first information block illustrated in Equation 4, and P ¹ , which is the parity block illustrated in Equation 3; Create the matrix [C ¹ ₀ P ¹ ].

In addition, the second parity check matrix generator 32 may generate a second information block of Equation 5 in the first parity check matrix [C ¹ ₀ P ¹ ] generated by the first parity check matrix generator 31. C ¹ ₁ is added to generate a second parity check matrix [C ¹ ₁ C ¹ ₀ P ¹ ].

In addition, the third parity check matrix generator 33 adds the second parity check matrix [C ¹ ₁ C ¹ ₀ P ¹ ] generated by the second parity check matrix generator 32 to the second parity check matrix generator 33. Three information blocks C ¹ ₂ are added to generate a third parity check matrix [C ¹ ₂ C ¹ ₁ C ¹ ₀ P ¹ ].

In addition, the fourth parity check matrix generator 34 may add the third parity check matrix [C ¹ ₂ C ¹ ₁ C ¹ ₀ P ¹ ] generated by the third parity check matrix generator 33 to [Equation 7]. ] Adds a fourth information block C ¹ ₃ to generate a fourth parity check matrix [C ¹ ₃ C ¹ ₂ C ¹ ₁ C ¹ ₀ P ¹ ].

In addition, the fifth parity check matrix generator 35 may add the fourth parity check matrix [C ¹ ₃ C ¹ ₂ C ¹ ₁ C ¹ ₀ P ¹ ] to the fourth parity check matrix generator 34. The fifth information block C ¹ ₄ of Equation 8 is added to generate a fifth parity check matrix [C ¹ ₄ C ¹ ₃ C ¹ ₂ C ¹ ₁ C ¹ ₀ P ¹ ].

The information shortening unit 36 applies the information shortening to at least one parity check matrix of the first to fifth parity check matrices generated by the first to fifth parity check matrix generators 31 to 35. Generate at least one parity check matrix different from the first to fifth parity check matrices.

The puncturing unit 37 applies a puncturing technique to at least one parity check matrix of the first to fifth parity check matrices generated by the first to fifth parity check matrix generators 31 to 35 to apply the puncturing technique. Generate at least one parity check matrix different from the fifth to parity check matrices.

4 is a block diagram of an apparatus for generating a parity check matrix according to another embodiment of the present invention.

As shown in FIG. 4, the apparatus for generating a parity check matrix according to the present invention includes a basic parity check matrix generator 41 for generating at least one basic parity check matrix, and the basic parity check matrix generator 41. Apply at least one extended parity check matrix by applying a row decomposition to the information block of the basic parity check matrix generated in the &lt; RTI ID = 0.0 &gt;) and extending the parity block of the basic parity check matrix generated by the basic parity check matrix generator 41. And an extended parity check matrix generator 42 for generating.

The apparatus for generating a parity check matrix according to the present invention is different from the basic parity check matrix and the extended parity check matrix by applying information shortening to at least one of the basic parity check matrix and the extended parity check matrix. The apparatus further includes an information shortening unit 43 for generating at least one parity check matrix.

In addition, the apparatus for generating a parity check matrix according to the present invention includes applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix, and at least different from the basic parity check matrix and the extended parity check matrix. It further includes a perforation 44 for generating one parity check matrix.

Here, the basic parity check matrix generator 41 generates a first basic parity check matrix composed of a first basic information block and a basic parity block, and the generated q-1 (1 <q≤Q, Q is 2 or more natural numbers) add a q th basic information block to a basic parity check matrix to generate a q th basic parity check matrix, and the extended parity check matrix generator 42 expands the basic parity block to generate an extended parity block. And generating a q th extended information block by applying row decomposition to the q th basic information block to generate a q th extended parity check matrix composed of the extended parity block and the first to q th extended information blocks.

The extended parity check matrix generator 42 generates an extended parity block with the same structure as the basic parity block. In this case, the basic parity block and the extended parity block have a double diagonal matrix form with constraints to have a simple encoder and a fast decoding convergence speed.

In addition, the basic parity check matrix generator 41 optimizes the basic parity check matrix by optimizing constraints, degree distributions, and cycle distributions for simple encoding and fast decoding convergence speed. The extended parity check matrix generator 42 performs an optimization of an extended parity check matrix by optimizing a constraint condition, a degree distribution, and a cycle distribution for simple encoding and fast decoding convergence speed. Create

4 illustrates an example of generating H ² , H ³ , and H ⁴ of Equations 9 to 11 from H ¹ of Equation 2.

The basic parity check matrix generation unit 41 generates at least one basic parity check matrix. For convenience, the embodiment of FIG. 3 will be described on the assumption that one basic parity matrix [C ¹ P ¹ ] is generated. .

And extended parity check matrix generating unit 42 is the default parity check matrix [C ¹ P ^1] for applying a row decomposition to produce a C ^2, and the basic parity check matrix [C ¹ P ^1] in information blocks C ¹ Parity block P ¹ is extended to generate parity block P ² having the same structure as P ¹ . As a result, an extended parity check matrix [C ² P ² ] is generated.

In addition, the information shortening unit 43 applies information shortening to at least one of the basic parity check matrix [C ¹ P ¹ ] and the extended parity check matrix [C ² P ² ] to [C ¹ P ¹ ] and [C ² P ^2]. Generate at least one parity check matrix that is different from].

The puncturing unit 44 applies a puncturing technique to at least one of the basic parity check matrix [C ¹ P ¹ ] and the extended parity check matrix [C ² P ² ] to apply [C ¹ P ¹ ] and [C ² P ² ]. At least one parity check matrix is generated.

On the other hand, the basic parity check matrix generator 41 according to the embodiment of FIG. 3, the first basic parity check matrix [C ¹ ₀ P ¹ ], the second basic parity check matrix [C ¹ ₁ C ¹ ₀ P ¹ ], Third basic parity check matrix [C ¹ ₂ C ¹ ₁ C ¹ ₀ P ¹ ], fourth basic parity check matrix [C ¹ ₃ C ¹ ₂ C ¹ ₁ C ¹ ₀ P ¹ ] and fifth basic parity check matrix [ When generating C ¹ ₄ C ¹ ₃ C ¹ ₂ C ¹ ₁ C ¹ ₀ P ¹ ] (i.e., generating a plurality of basic parity check matrices), the extended parity check matrix generator 42 may include first through Extended parity check matrix from the fifth basic parity check matrix [C ² ₀ P ² ], [C ² ₁ C ² ₀ P ² ], [C ² ₂ C ² ₁ C ² ₀ P ² ], [C ² ₃ C ² ₂ C ² ₁ C ² ₀ P ² ] and [C ² ₄ C ² ₃ C ² ₂ C ² ₁ C ² ₀ P ² ].

5 is a block diagram of an LDPC encoding apparatus supporting variable information length and variable code rate having simple encoding and fast decoding convergence rate according to an embodiment of the present invention.

First, an LDPC encoding apparatus for supporting a variable information length and a variable code rate according to an embodiment of the present invention includes a parity check matrix for selecting a parity check matrix corresponding to an input coding parameter among a plurality of parity check matrices. A parity check matrix selector 51, and an encoder 52 for encoding an input information word based on the parity check matrix selected by the parity check matrix selector 51, wherein the plurality of encoders include: The parity check matrix includes a first parity check matrix consisting of a first information block and a parity block, and a q-th information block added to a q-1 (1 <q≤Q, Q is a natural number of 2 or more) parity check matrix. q contains a parity check matrix.

Here, the input encoding parameter includes a code rate and a length of the input information word.

The plurality of parity check matrices further include at least one parity check matrix generated by applying information shortening to at least one parity check matrix of the first to Q th parity check matrices.

The plurality of parity check matrices further include at least one parity check matrix generated by applying a puncturing technique to at least one parity check matrix of the first to Qth parity check matrices.

On the other hand, the LDPC coding apparatus supporting the variable information length and the variable code rate according to another embodiment of the present invention, for selecting a parity check matrix corresponding to the input coding parameter from a plurality of parity check matrix A parity check matrix selector 51, and an encoder 52 for encoding an input information word based on the parity check matrix selected by the parity check matrix selector 51, wherein the plurality of encoders include: Parity check matrix includes at least one basic parity check matrix and at least one extended parity check generated by applying a row decomposition to an information block of the basic parity check matrix and extending a parity block of the basic parity check matrix. Contains a matrix.

Here, the input encoding parameter includes a code rate and a length of the input information word.

The plurality of parity check matrices further include at least one parity check matrix generated by applying information shortening to at least one of the basic parity check matrix and the extended parity check matrix.

The plurality of parity check matrices further include at least one parity check matrix generated by applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix.

Next, each component will be described with reference to FIG. 5.

The parity check matrix selector 51 selects a parity check matrix corresponding to an input encoding parameter from a plurality of parity check matrices. Here, the plurality of parity check matrices refer to parity check matrices generated as described with reference to FIGS. 3 and 4. Here, the input encoding parameter is a parameter used to select a parity check matrix, and examples thereof include an information length and a code rate. However, the input encoding parameter is not limited to the parity check matrix.

The encoder 52 encodes an input information word based on the parity check matrix selected by the parity check matrix selector 51 and outputs a codeword.

6 is a block diagram of an LDPC decoding apparatus supporting variable information length and variable code rate having simple encoding and fast decoding convergence rate according to an embodiment of the present invention.

First, an LDPC decoding apparatus supporting a variable information length and a variable code rate according to an embodiment of the present invention includes a parity check matrix for selecting a parity check matrix corresponding to an input decoding parameter among a plurality of parity check matrices. A parity check matrix selector 61 and a decoder 62 for decoding a received codeword based on the parity check matrix selected by the parity check matrix selector 61; The parity check matrix includes a first parity check matrix consisting of a first information block and a parity block, and a q-th information block added to a q-1 (1 <q≤Q, Q is a natural number of 2 or more) parity check matrix. q contains a parity check matrix.

Here, the input decoding parameter includes a code rate and an information length of the received codeword.

The plurality of parity check matrices further include at least one parity check matrix generated by applying information shortening to at least one parity check matrix of the first to Qth parity check matrices, and wherein the decoding is performed. If the parity check matrix selected by the parity check matrix selector 61 is a matrix to which information shortening is applied, the block 62 performs decoding by setting the probability that the information shortening bit is 0.

The plurality of parity check matrices may further include at least one parity check matrix generated by applying a puncturing technique to at least one parity check matrix of the first to Q th parity check matrices. When the parity check matrix selected by the parity check matrix selector 61 is a matrix to which the puncturing technique is applied, the block 62 performs decoding by setting the probability that the punctured bit is a value of 1 to 1/2.

Meanwhile, the LDPC decoding apparatus supporting variable information length and variable code rate according to another embodiment of the present invention selects a parity check matrix corresponding to an input decoding parameter from a plurality of parity check matrices. A parity check matrix selector 61 and a decoder 62 for decoding a received codeword based on the parity check matrix selected by the parity check matrix selector 61. The plurality of parity check matrices include at least one basic parity check matrix and at least one extended parity generated by applying row decomposition to an information block of the basic parity check matrix and extending a parity block of the basic parity check matrix. Contains the check matrix.

Here, the input decoding parameter includes a code rate and an information length of the received codeword.

The plurality of parity check matrices may further include at least one parity check matrix generated by applying information shortening to at least one of the basic parity check matrix and the extended parity check matrix. If the parity check matrix selected by the parity check matrix selector 61 is a matrix to which information shortening is applied, the decoding is performed by setting the probability that the information shortening bit is 0 to 1.

The plurality of parity check matrices may further include at least one parity check matrix generated by applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix. If the parity check matrix selected by the parity check matrix selector 61 is a matrix to which the puncturing technique is applied, the decoding is performed by setting the probability that the punctured bits are 1 to 1/2.

Next, each component will be described with reference to FIG. 6.

The parity check matrix selector 61 selects a parity check matrix corresponding to an input decoding parameter from a plurality of parity check matrices. Here, the plurality of parity check matrices refer to parity check matrices generated as described with reference to FIGS. 3 and 4. Here, the input decoding parameter is a parameter used to select a parity check matrix, and examples thereof include a code rate and an information length of a received codeword. However, the input decoding parameter is not limited thereto. .

The decoder 62 decodes the received codeword based on the parity check matrix selected by the parity check matrix selector 61. An example of the decoding algorithm used at this time may be a message passing algorithm (hereinafter referred to as "MPA"). On the other hand, if the parity check matrix selected by the parity check matrix selector 61 is a matrix to which the information shortening technique is applied, the decoder 62 performs decoding by setting the probability that the information shortening bit is 0 to 1, When the parity check matrix selected by the parity check matrix selector 61 is a matrix to which a puncturing technique is applied, decoding is started by setting the probability that the punctured bits are 1 to 1 when performing MPA-based decoding for the first time. do.

7 is a flowchart illustrating a parity check matrix generation method according to an embodiment of the present invention.

Referring to FIG. 7, the parity check matrix generation method according to an embodiment of the present invention includes processes processed in time series in the parity check matrix generating apparatus of FIG. 3. Therefore, although the specific embodiment is omitted in the following description, the above description of the parity check matrix generating apparatus of FIG. 3 also applies to the parity check matrix generating method according to an embodiment of the present invention.

The embodiment of FIG. 7 will be described with reference to FIG. 3.

First, the first parity check matrix generator 31 generates a first parity check matrix composed of the first information block and the parity block (71).

Thereafter, the second parity check matrix generator 32 generates a second parity check matrix by adding a second information block to the generated first parity check matrix.

Thereafter, the third parity check matrix generator 33 adds a third information block to the generated second parity check matrix to generate a third parity check matrix (73).

Thereafter, the fourth parity check matrix generator 34 adds a fourth information block to the generated third parity check matrix to generate a fourth parity check matrix (74).

Thereafter, the fifth parity check matrix generator 35 adds a fifth information block to the generated fourth parity check matrix to generate a fifth parity check matrix (75).

Thereafter, the information shortening unit 36 may further apply information shortening to at least one parity check matrix of the generated first to fifth parity check matrices, thereby providing at least one different from the first to fifth parity check matrices. The parity check matrix is generated, and additionally, the puncturing unit 37 is different from the first to fifth parity check matrices by applying a puncture to at least one parity check matrix of the generated first to fifth parity check matrices. Generate at least one parity check matrix (76).

8 is a flowchart illustrating a parity check matrix generation method according to another embodiment of the present invention.

Referring to FIG. 8, the parity check matrix generation method according to another embodiment of the present invention includes processes processed in time series in the parity check matrix generating apparatus of FIG. 4. Therefore, although the specific embodiment is omitted in the following description, the above description of the parity check matrix generating apparatus of FIG. 4 is also applied to the parity check matrix generating method according to another embodiment of the present invention.

The embodiment of FIG. 8 will be described with reference to FIG. 4.

First, the basic parity check matrix generator 41 generates at least one basic parity check matrix (81).

Subsequently, the extended parity check matrix generator 42 generates at least one extended parity check matrix by applying row decomposition to the information block of the basic parity check matrix and extending the parity block of the basic parity check matrix. 82).

Thereafter, the information shortening unit 43 applies information shortening to at least one of the generated basic parity check matrix and extended parity check matrix, thereby checking at least one parity check different from the basic parity check matrix and the extended parity check matrix. In addition, the puncturing unit 44 may apply a puncturing to at least one of the generated basic parity check matrix and the extended parity check matrix so that at least one different from the basic parity check matrix and the extended parity check matrix is generated. A parity check matrix is generated (83).

9 is a flowchart illustrating an LDPC encoding method supporting variable information length and variable code rate having simple encoding and fast decoding convergence rate according to an embodiment of the present invention.

Referring to FIG. 9, the LDPC encoding method supporting the variable information length and the variable code rate according to the embodiment of the present invention is processed in time series in the LDPC encoding apparatus supporting the variable information length and the variable code rate of FIG. 5. It consists of processes. Therefore, although the specific embodiment is omitted in the following description, the above descriptions regarding the LDPC encoding apparatus supporting the variable information length and the variable code rate of FIG. 5 refer to the variable information length and the variable code according to the embodiment of the present invention. The same applies to an LDPC encoding method supporting rate.

The embodiment of FIG. 9 will be described with reference to FIG. 5.

First, the parity check matrix selector 51 selects a parity check matrix corresponding to an input encoding parameter from a plurality of parity check matrices (91). Here, the plurality of parity check matrices refer to parity check matrices generated as described with reference to FIGS. 3 and 4.

Subsequently, the encoder 52 encodes an input information word based on the selected parity check matrix (92).

10 is a flowchart of an LDPC decoding method supporting variable information length and variable code rate having simple encoding and fast decoding convergence rate according to an embodiment of the present invention.

Referring to FIG. 10, the LDPC decoding method supporting the variable information length and the variable code rate according to the embodiment of the present invention is processed in time series in the LDPC decoding apparatus supporting the variable information length and the variable code rate of FIG. 6. It consists of processes. Therefore, although the specific embodiment is omitted in the following description, the foregoing descriptions regarding the LDPC decoding apparatus supporting the variable information length and the variable code rate of FIG. 6 refer to the variable information length and the variable code according to the embodiment of the present invention. The same applies to an LDPC decoding method supporting rate.

The embodiment of FIG. 10 will be described with reference to FIG. 6.

First, the parity check matrix selector 61 selects a parity check matrix corresponding to an input decoding parameter from a plurality of parity check matrices (101). Here, the plurality of parity check matrices refer to parity check matrices generated as described with reference to FIGS. 3 and 4.

Thereafter, the decoder 62 decodes the received codeword based on the selected parity check matrix (102).

On the other hand, the method of the present invention as described above can be written in a computer program. And the code and code segments constituting the program can be easily inferred by a computer programmer in the art. In addition, the written program is stored in a computer-readable recording medium (information storage medium), and read and executed by a computer to implement the method of the present invention. The recording medium may include any type of computer readable recording medium.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawings.

The present invention can be used for LDPC encoding / decoding systems.

1 is a diagram for structurally explaining the relationship between parity check matrices illustrated in the table of [Table 1];

2 is a diagram for explaining a concept of applying an information shortening technique and a puncturing technique to a parity check matrix according to the present invention;

3 is a block diagram of an apparatus for generating a parity check matrix according to an embodiment of the present invention;

4 is a block diagram of an apparatus for generating a parity check matrix according to another embodiment of the present invention;

5 is a configuration diagram of an LDPC encoding apparatus supporting variable information length and variable code rate having simple encoding and fast decoding convergence rate according to an embodiment of the present invention;

6 is a block diagram of an LDPC decoding apparatus supporting variable information length and variable code rate having simple encoding and fast decoding convergence rate according to an embodiment of the present invention;

7 is a flowchart illustrating a parity check matrix generation method according to an embodiment of the present invention;

8 is a flowchart of a parity check matrix generation method according to another embodiment of the present invention;

9 is a flowchart of an LDPC encoding method supporting variable information length and variable code rate having simple encoding and fast decoding convergence rate according to an embodiment of the present invention;

10 is a flowchart of an LDPC decoding method supporting variable information length and variable code rate having simple encoding and fast decoding convergence rate according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 to 35: first to fifth parity check matrix generator

36, 43: information reduction part 37, 44: perforation part

41: basic parity check matrix generator 42: extended parity check matrix generator

51, 61: parity check matrix selector 52: encoder

62: decoder

Claims (29)

In the parity check matrix generator of a Low Density Parity Check (LDPC) code, First parity check matrix generating means for generating a first parity check matrix composed of the first information block and the parity block; And Q-parity check matrix generating means for generating a q-parity check matrix by adding a q-th information block to the generated q-1 (1 <q≤Q, where Q is a natural number of 2 or more) parity check matrix Parity check matrix generator of the LDPC code comprising a. The method of claim 1, Information shortening means for generating at least one parity check matrix different from the first through Q-parity check matrices by applying information shortening to at least one parity check matrix of the first through Q parity check matrices; Parity check matrix generation apparatus of the LDPC code further comprising. The method of claim 1, Puncturing means for generating at least one parity check matrix different from the first through Q-parity check matrices by applying a puncturing technique to at least one parity check matrix of the first through Q parity check matrices. Parity check matrix generation apparatus of the LDPC code further comprising. The method of claim 1, The qth parity check matrix generating means includes: An LDPC code characterized in that the qth parity check matrix is generated by performing optimization of constraints (limiting conditions for simple encoding and fast decoding convergence speed), degree distribution, and cycle distribution. Parity check matrix generator. In the parity check matrix generator of the LDPC code, Basic parity check matrix generating means for generating at least one basic parity check matrix; And Apply at least one extended parity check matrix by applying row decomposition to the information block of the basic parity check matrix generated by the basic parity check matrix generating means and extending the parity block of the basic parity check matrix generated by the basic parity check matrix generating means. Means for generating extended parity check matrices for generating Parity check matrix generator of the LDPC code comprising a. The method of claim 5, wherein Information shortening means for generating at least one parity check matrix different from the basic parity check matrix and the extended parity check matrix by applying information shortening to at least one of the basic parity check matrix and the extended parity check matrix. Parity check matrix generation apparatus of the LDPC code further comprising. The method of claim 5, wherein Puncturing means for generating at least one parity check matrix different from the basic parity check matrix and the extended parity check matrix by applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix. Parity check matrix generation apparatus of the LDPC code further comprising. The method of claim 5, wherein The basic parity check matrix generating means, Generate a first basic parity check matrix composed of a first basic information block and a basic parity block, and add the q basic information block to the generated q-1 (1 <q≤Q, Q is a natural number of two or more) basic parity check matrices. Add to generate the qth default parity check matrix, The extended parity check matrix generating means, An extended parity block is generated by extending the basic parity block, and a q th extended information block is generated by applying a row decomposition to the q th basic information block to generate the extended parity block and the first to q th extended information blocks. An apparatus for generating a parity check matrix of an LDPC code, characterized in that it generates a q-th extended parity check matrix. The method of claim 8, The extended parity check matrix generating means, And generating the extended parity block with the same structure as the basic parity block. The method of claim 9, The basic parity block and the extended parity block, An apparatus for generating a parity check matrix of an LDPC code, characterized in that it is in the form of a double diagonal matrix provided with a simple encoder and a fast decoding convergence speed. The method of claim 5, wherein The basic parity check matrix generating means, Generate a basic parity check matrix by optimizing the constraints (constraints for simple encoding and fast decode convergence rates), degree distributions, and cycle distributions, The extended parity check matrix generating means, Parity of the LDPC code characterized by generating an extended parity check matrix by performing optimization of constraints (constraints for simple encoding and fast decoding convergence speed), degree distribution, and cycle distribution Test matrix generator. In the LDPC encoder, Parity check matrix selecting means for selecting a parity check matrix corresponding to an input coding parameter among a plurality of parity check matrices; And And encoding means for encoding an information word based on the parity check matrix selected by the parity check matrix selecting means. In the plurality of parity check matrices, a q-th information block is added to a first parity check matrix including a first information block and a parity block and a q-1 (1 <q≤Q, Q is a natural number of 2 or more) parity check matrix. And a q-th parity check matrix. The method of claim 12, The plurality of parity check matrix, And at least one parity check matrix generated by applying information shortening to at least one parity check matrix of the first to Q parity check matrices. The method of claim 12, The plurality of parity check matrix, And at least one parity check matrix generated by applying a puncturing technique to at least one parity check matrix of the first to Q parity check matrices. In the LDPC encoder, Parity check matrix selecting means for selecting a parity check matrix corresponding to an input coding parameter from a plurality of parity check matrices; And And encoding means for encoding an information word based on the parity check matrix selected by the parity check matrix selecting means. The plurality of parity check matrices include at least one basic parity check matrix and at least one extended parity check generated by applying a row decomposition to an information block of the basic parity check matrix and extending a parity block of the basic parity check matrix. LDPC encoding apparatus comprising a matrix. The method of claim 15, The plurality of parity check matrix, And at least one parity check matrix generated by applying information shortening to at least one of the basic parity check matrix and the extended parity check matrix. The method of claim 15, The plurality of parity check matrix, And at least one parity check matrix generated by applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix. In the LDPC decoding apparatus, Parity check matrix selecting means for selecting a parity check matrix corresponding to an input decoding parameter from a plurality of parity check matrices; And A decoding means for decoding a received codeword based on the parity check matrix selected by the parity check matrix selecting means, The plurality of parity check matrices include a first parity check matrix composed of a first information block and a parity block, and a q-th information block added to a parity check matrix q-1 (where 1 <q≤Q and Q is a natural number of two or more). And a q-th parity check matrix. The method of claim 18, The plurality of parity check matrix, At least one parity check matrix generated by applying information shortening to at least one parity check matrix of the first to Q parity check matrices; And if the parity check matrix selected by the parity check matrix selecting means is a matrix to which information shortening is applied, the decoding means performs decoding by setting the probability that the information shortening bit is a value of zero to one. The method of claim 18, The plurality of parity check matrix, At least one parity check matrix generated by applying a puncturing technique to at least one parity check matrix of the first to Q parity check matrices; The decoding means, when the parity check matrix selected by the parity check matrix selection means is a matrix to which the puncturing technique is applied, sets the probability that the punctured bits are 1 to 1/2 to perform decoding. . In the LDPC decoding apparatus, Parity check matrix selecting means for selecting a parity check matrix corresponding to an input decoding parameter from a plurality of parity check matrices; And A decoding means for decoding a received codeword based on the parity check matrix selected by the parity check matrix selecting means, The plurality of parity check matrices include at least one basic parity check matrix and at least one extended parity check generated by applying a row decomposition to an information block of the basic parity check matrix and extending a parity block of the basic parity check matrix. LDPC decoding apparatus comprising a matrix. The method of claim 21, The plurality of parity check matrix, At least one parity check matrix generated by applying information shortening to at least one of the basic parity check matrix and the extended parity check matrix; And if the parity check matrix selected by the parity check matrix selecting means is a matrix to which information shortening is applied, the decoding means performs decoding by setting the probability that the information shortening bit is a value of zero to one. The method of claim 21, The plurality of parity check matrix, At least one parity check matrix generated by applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix; The decoding means, when the parity check matrix selected by the parity check matrix selection means is a matrix to which the puncturing technique is applied, sets the probability that the punctured bits are 1 to 1/2 to perform decoding. . In the parity check matrix generation method of the LDPC code, A first parity check matrix generating step of generating a first parity check matrix composed of the first information block and the parity block; And A q parity check matrix generation step of generating a q parity check matrix by adding a q-th information block to the generated q-1 (1 <q≤Q, where Q is a natural number of 2 or more) parity check matrix. Parity check matrix generation method of the LDPC code comprising a. The method of claim 24, An information shortening step of applying information shortening to at least one parity check matrix of the first to Q parity check matrices to generate at least one parity check matrix different from the first to Q th parity check matrices; Parity check matrix generation method of the LDPC code further comprising. The method of claim 24, A puncturing step of generating at least one parity check matrix different from the first to Q th parity check matrices by applying a puncturing technique to at least one parity check matrix of the first to Q parity check matrices. Parity check matrix generation method of the LDPC code further comprising. In the parity check matrix generation method of the LDPC code, A basic parity check matrix generation step of generating at least one basic parity check matrix; And An extended parity check matrix generation step of applying row decomposition to the information block of the generated basic parity check matrix and generating at least one extended parity check matrix by extending the generated parity block of the generated basic parity check matrix Parity check matrix generation method of the LDPC code comprising a. The method of claim 27, An information shortening step of applying information shortening to at least one of the basic parity check matrix and the extended parity check matrix to generate at least one parity check matrix different from the basic parity check matrix and the extended parity check matrix; Parity check matrix generation method of the LDPC code further comprising. The method of claim 27, A puncturing step of generating at least one parity check matrix different from the basic parity check matrix and the extended parity check matrix by applying a puncturing technique to at least one of the basic parity check matrix and the extended parity check matrix. Parity check matrix generation method of the LDPC code further comprising.

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