KR20090061961A - Apparatus for motion compensation - Google Patents

Abstract

A motion compensation apparatus is provided to minimize a cache line with a cache address configuration and perform motion compensation without data collision, thereby decoding clearly an image. A motion compensation apparatus comprises a cache memory, an external memory, and a motion compensation engine. The cache memory comprises a save domain and an address assigning domain composed of cache lines. The external memory is comprised of a plurality of blocks in which each cache line index is given. The external memory is made of a plurality of rows. In the external memory, data of a row of an image frame is stored within one row among the plurality of rows. The motion compensation engine stores image data, stored in each block of the external memory, in a cache line which a cache line index designates. The motion compensation engine performs motion compensation with image data stored in the designated cache line.

Description

Apparatus for motion compensation

1 is a block diagram illustrating a motion correction of the present invention.

2 is a block diagram of an external memory for motion compensation according to the present invention.

3 is an address format of a cache memory for motion compensation according to the present invention.

The present invention relates to an apparatus for compensating for motion of an image, and more particularly, to an apparatus for compensating for motion of an image applied to an H.264 / AVC decoder.

H.264 / AVC is the latest standard to adopt aggressive compression techniques, including variable block size and quarter-sample precision motion compensation. In order to obtain the motion correction of H.264 / AVC, the H.264 / AVC decoder must make a lot of data access from the reference frame memory. For example, in order to perform motion compensation of one 4x4 block, the decoder may access up to 9x9 blocks of the reference frame memory. As a result, motion compensation accounts for 75% of the memory bandwidth required to access the reference frame memory, and such excessive motion compensation memory access is a major obstacle to the performance improvement of H.264 / AVC. Is giving.

Various techniques have been proposed to reduce the memory bandwidth required to access the reference frame memory for motion compensation, and one of them is divided into integer motion compensation and fraction motion compensation. And fetching exactly the required blocks when an arbitrary motion vector points to an integer position. In this way, adjacent reference blocks are patched together when they have the same motion vectors, and any data block is stored in a register file and reused in subsequent blocks. This approach greatly reduces memory access by avoiding repetitive data access shared by adjacent blocks, but cannot be used when the motion vectors of adjacent blocks are different.

An object of the present invention is to provide a motion compensation device for reducing a memory bandwidth required for accessing an external memory in motion compensation regardless of whether the motion vectors of adjacent blocks are the same.

A feature of the present invention for this purpose is a cache memory comprising a storage area consisting of cache lines and an address allocation area; An external memory comprising a plurality of columns each of which is assigned a cache line index, wherein data of one column of an image frame is stored in one of the plurality of columns; And a motion correction engine for storing image data stored in each of the blocks of the external memory in a cache line designated by the cache line index, and performing motion compensation based on the image data stored in the designated cache line.

In the present invention, it is preferable that two cache line indices are alternately assigned to the plurality of blocks forming one column.

In addition, the address format of the address allocating area in the present announcement includes: a first tag area for classifying columns; A second tag area for identifying blocks within the same column; An index area for designating the cache line; And an offset region.

In addition, in the present invention, the index region preferably includes a first index region for designating the cache line and a second index region used for toggling.

In the present invention, the cash line is preferably 32.

In the present invention, one block of the cache line and the external memory is preferably 8 bytes.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram for motion compensation of the present invention.

In the conventional memory structure, an internal buffer is installed between the hardware motion compensation engine and the external memory to temporarily store data for motion compensation, but in FIG. 1, the cache memory 3 is provided with the motion compensation engine 1 and the external memory. Installed between (2). The cache memory 3 is more complicated and requires a larger memory capacity than a conventional buffer, but can store one block of data and can reuse them for another block, thereby reducing access to the external memory 2.

1 requires a split-index direct mapped cache described below as an access pattern of a motion compensation algorithm. In a typical video compression algorithm, one image is decomposed into blocks, and each block is processed independently. Thus, two data in the same block are likely to be accessed together. However, if two data are separated into more than one block, they cannot be accessed together. The cache configuration of the embodiment has the advantage of reducing cache access collisions.

The split-index direct map cache will now be described.

As shown in FIG. 2, data is mapped from external memory 2 to cache memory 3 for H.264 / AVC motion correction. 2, only luminance data is considered. In the external memory 2, each page (= row) has 512 bytes, and the size of each column of one image frame is larger than 512 bytes. Make it small. Therefore, each column of the image frame is stored in one page of the external memory 2, and the cache line size is 8 bytes. The external memory 2 is divided into blocks, each of which represents 1x8 byte data and is mapped to one cache line. The number of each block represents the index of the cache line to which each block is mapped. The first page of external memory (address 0) is mapped sequentially to cache lines 0 and 1. In the same way, blocks on the second page are mapped to cache lines 2 and 3, page 16 is mapped to cache lines 30 and 31, and the next page on page 16 is again mapped to cache lines 0 and 1. In this case, the 9 × 9 block is a maximum block size required for inserting a 4 × 4 block for H.264 / AVC motion correction. Therefore, 9 bytes in one column may be simultaneously stored in two cache lines. Also, since two data separated by 9 pixels or more cannot be accessed together for 9x9 data access, the same two cache lines are used for the entire page without data collision. The cache must store 9x9 blocks (81 bytes), and the number of cache lines is determined to be 32 because 32 is the smallest number of cache lines that can store 9x9 blocks, and 32 is a multiplier of two. At this time, one cache is conveniently controlled when the cache size is a multiplier of two.

As shown in FIG. 3, the address bits are allocated such that the cache mapping shown in FIG. 2 is achieved. If the size of the image size is 512 x 512, 18 bits are needed to address one frame of the image. Address segmentation can be applied to any image by changing the total number of address bits. The cache block index is address bits of 9 to 12 bits and 3 bits, denoted by A [12: 9] and A [3], respectively. Address bits [12: 9] are used to address 16 image rows, and A [3] is used to toggle 2 blocks in the same image row. Combining these 5 bits, the index can select 32 cache blocks. Address bits A [2: 0] from 0 to 2 indicate an offset in one cache block. Address bits A [13: 7] from 13 to 7 are used as cache tags labeled TAG_upper to distinguish different columns in one image. Address bits A [4: 8] from 4 to 8 are used in one image. Used as another tag, labeled TAG_low, to identify blocks within the same line. In contrast to the conventional direct mapped cache, the cache is called a split-index direct mapped cache because the index and tag bits are split. The cache configuration shown in FIGS. 2 and 3 may also apply to any external memory size that is longer than the image frame. Since the size of the chrominance samples is one quarter of the size of the luminance, the size of the cache is also reduced to 16 × 4. 3B shows the address format of a chrominance cache that allocates 256 × 256 chrominance samples to 16 bit addresses. The cache size is 16x4, 4 bits are used as an index, and 2 bits are allocated as an offset.

Experimental Example

In the experimental example, the reduced degree is compared by comparing the external memory access by the cache configuration of the present invention with the external memory access when there is no conventional cache configuration. In software, H.264 / AVC version 7.3 was used to measure the data access pattern of motion compensation with and without cache configuration. The QP, search area, and reference frame number were set to 28, 16, and 5, respectively. The first frame was encoded in I-slice and the remaining frames were encoded in P-slice. In the experimental example, 32 × 8 was applied as the split index cache. In addition, 16 × 4 was applied as the split index cache as the chrominance sample. For the experiment, memory words (32 bits) patched from external memory were measured and compared with the original H.264 / AVC without cache configuration and cache configuration of the present invention. As a result, the reduction ratio of the bandwidth was reduced by 66% on average with the split index cache.

The memory bandwidth required for accessing the external memory according to the motion compensation can be greatly reduced by the external memory and the cache configuration according to the present invention having the above object and configuration.

In addition, the cache address structure of the present invention minimizes cache lines and performs motion compensation without data collision, thereby decoding clear images.

Claims (6)

A cache memory including a storage area consisting of cache lines and an address allocation area; An external memory comprising a plurality of columns each of which is assigned a cache line index, wherein data of one column of an image frame is stored in one of the plurality of columns; And a motion correction engine storing image data stored in each block of the external memory in a cache line designated by the cache line index, and performing a motion correction based on the image data stored in the designated cache line. Compensator. The apparatus of claim 1, wherein two cache line indices are alternately assigned to the plurality of blocks forming one column. 3. The address format of claim 2, wherein the address format of the address allocation area is A first tag area for distinguishing columns; A second tag area for identifying blocks within the same column; An index area for designating the cache line; And And a offset region. 4. The motion compensation apparatus of claim 3, wherein the index area comprises a first index area for designating the cache line and a second index area used for toggling. 5. The motion compensating device according to any one of claims 1 to 4, wherein said cache line is 32. 5. The motion compensating device according to any one of claims 1 to 4, wherein one block of the cache line and the external memory is 8 bytes.

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