KR20090057529A - Nonvolatile memory device and manufacturing the same - Google Patents

Abstract

A nonvolatile memory device and a manufacturing method thereof are provided to minimize the influence of a mobile ion in a floating gate by reducing an area between a sidewall of the floating gate and a spacer by using a recess in an active region. A recess is formed in an active region of a semiconductor substrate(102). A tunnel insulating layer(104) is formed on the recess. A floating gate(106) is formed in the recess. An ion shielding layer is formed in the sidewall of the floating gate. The dielectric film is formed on the floating gate. A control gate is formed on the dielectric film. A spacer(114) is formed in the sidewall of the control gate, the dielectric film, and the protection layer.

Description

Nonvolatile memory device and manufacturing method thereof

TECHNICAL FIELD The present invention relates to a nonvolatile memory device and a method for manufacturing the same, and more particularly, to a NAND flash memory device and a method for manufacturing the same.

In general, semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), are fast memory inputs and outputs, but lose their stored data when power is lost. In contrast, nonvolatile memory devices are memory devices that retain their stored data even when their power supplies are interrupted.

Flash memory devices are a type of nonvolatile memory device that can be programmed and erased, and can be programmed and erased electrically (EPROM) and electrically programmable and erased (EEPROM). It is a highly integrated memory device developed by combining the advantages of Programmable Read Only Memory. Here, the program refers to an operation of writing data in a memory cell, and the erasing means an operation of erasing data written in the memory cell.

The NAND type nonvolatile memory device of the flash memory device includes a cell string in which a plurality of cells are connected in series. In the cell string, select transistors are disposed at both ends of the memory cells connected in series. Each is connected. Therefore, at the time of reading, a read voltage is applied to the gate of the selection transistor, and a high high voltage is applied to the remaining cell transistors so as to conduct all of them. As a result, the current flowing in the cell string is small, so that power consumption is lower than that of the NOR type nonvolatile memory device. In addition, it is easy to be highly integrated as compared to NOR-type nonvolatile memory devices, and is suitable for manufacturing a large capacity memory device. According to such a feature, a NAND type nonvolatile memory device has been widely used in recent years.

The NAND type nonvolatile memory device uses an F / N tunneling phenomenon to change the threshold voltage of a memory cell as electrons pass through a strong electric field applied to a thin tunnel oxide layer. That is, during programming, the electrons are filled in the floating gate to increase the threshold voltage, and during erasing, the electrons escape from the floating gate and the threshold voltage is lowered because holes are present in the floating gate. This allows the NAND string to provide an open circuit to the precharged bit line because the select word line voltage is lower than the threshold voltage of the select memory cell when the select memory cell is in the program state, thereby keeping the select memory cell off. do. On the other hand, when the selected memory cell is in an erased state and the selected word line voltage is greater than the threshold voltage of the selected memory cell, the precharged bit line is discharged.

However, the threshold voltage of the memory cell may vary for various reasons in addition to programming or erasing the memory cell. For example, in the NAND flash memory device, when the program operation and the erase operation are repeatedly performed, the tunnel oxide film is degraded to form a separate interface such as a charge trap layer between the tunnel oxide film and the semiconductor substrate. This charge trap layer causes the threshold voltage of the memory cell to fluctuate and affect the reliability of the NAND flash memory device operation. In addition, mobile ions around the memory cell can also change the threshold voltage of the memory cell. The threshold voltage fluctuations caused by the mobile ions are important to directly affect the reliability of the memory cell itself and the cell's threshold voltage distribution. Acts as an element

The present invention forms a recess in the active region, and then forms a memory cell on the recess and forms an ion blocking layer on the sidewall of the floating gate, thereby reducing the area where the sidewall of the floating gate faces the spacers. Minimize the influence from the mobile ions of (mobile ion).

A nonvolatile memory device according to the present invention includes a semiconductor substrate having a recess formed in an active region, a tunnel insulating film formed on the recess, a floating gate formed on the recess on which the tunnel insulating film is formed, and a semiconductor substrate. And an ion blocking layer formed on the exposed sidewalls of the floating gate, a dielectric layer formed on the floating gate, a control gate formed on the dielectric layer, and a spacer formed on sidewalls of the control gate, the dielectric layer, and the passivation layer. .

The ion barrier layer may be formed of Al ₂ O ₃ . The recess and the floating gate may have the same width.

A method of manufacturing a nonvolatile memory device according to the present invention includes forming a recess in an active region of a semiconductor substrate, forming a tunnel insulating layer on the semiconductor substrate in the active region, and forming the tunnel insulating layer. Forming a floating gate in a recess, forming an ion blocking film in the floating gate side wall exposed on the semiconductor substrate, forming a dielectric film on the floating gate, and controlling on the dielectric film Forming a gate and forming spacers on sidewalls of the control gate, the dielectric layer, and the passivation layer.

The ion barrier layer may be formed of Al ₂ O ₃ . The recess and the floating gate may be formed to have the same width.

According to the nonvolatile memory device and the manufacturing method thereof of the present invention, it is possible to improve the reliability of the memory cell operation by reducing the threshold voltage variation of the memory cell. In addition, the height of the memory cells may additionally be reduced to facilitate subsequent etching or deposition processes.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

In general, gate spacers are formed on sidewalls of memory cells of a NAND flash memory device using an insulating material. However, there are a plurality of mobile ions in the gate spacer, and these mobile ions affect the threshold voltage variation of the memory cell, which will be described in detail below.

2A to 2C are schematic diagrams illustrating memory cells of a NAND flash memory device, wherein like reference numerals denote like elements. In particular, FIGS. 2A to 2C illustrate mobile ions (reference numeral +) included in a spacer of a memory cell at each stage of a baking process performed to verify threshold voltage variations caused by mobile ions.

2A through 2C, a tunnel insulating film 204 is formed on a semiconductor substrate 202, and a floating gate 206, a dielectric film 208, and a control gate 210 are formed in an active region on the tunnel insulating film 204. Are stacked to form a memory cell. In addition, spacers 212 are formed on the sidewalls of the memory cells to protect the sidewalls of the memory cells and electrically isolate the memory cells from each other. 2B illustrates an initial state in which a memory cell does not perform a program operation or an erase operation. In this case, positively charged mobile ions such as Ca + ions and K + ions are present in the spacer 212.

In order to verify whether such mobile ions affect the threshold voltage variation of the memory cell, the threshold voltage is measured after the program operation and the erase operation of the memory cell. At this time, the bake process is performed on the memory cell after the program operation and the erase operation of the memory cell so that the mobile ions can move more easily.

To this end, in order to determine the threshold voltage variation after the program operation, the program operation is performed on the memory cell, and then the first baking process is performed on the memory cell. Then, due to the large number of electrons filled in the floating gate 206 due to the program operation, the mobile ions present in the spacer 212 are located more adjacent to the floating gate 208 as shown in FIG. 2C due to attraction.

Subsequently, in order to determine the threshold voltage variation during the program operation after the erase operation, the erase operation is performed on the memory cell, and then the program operation is performed and the secondary bake process is performed. In this case, holes that are relatively positively charged due to the extraction of electrons existing in the floating gate 206 due to the erase operation are present in the floating gate 206. However, since the program operation is performed again, due to the large number of electrons filled in the floating gate 206, the plurality of mobile ions present in the spacer 212 as shown in FIG. 2C are located more adjacent to the floating gate 208.

Lastly, in order to determine the threshold voltage variation after the program operation in the absence of mobile ions, an erase operation is performed on the memory cell, a bake process is performed, a program operation is performed, and a third bake process is performed. . In this case, the bake process is performed in a state in which electrons existing in the floating gate 206 are drawn out due to the erase operation and positive holes are present in the floating gate 206. In 212), due to repulsive force, mobile ions do not exist as shown in FIG. 2A. However, since the program operation is performed again, due to the large number of electrons filled in the floating gate 206, the plurality of mobile ions present in the spacer 212 as shown in FIG. 2C are positioned adjacent to the floating gate 208.

3 is a graph illustrating a reference value of an ideal threshold voltage when a program operation is performed on a memory cell and threshold voltage values in the first to third baking processes described above.

Referring to FIG. 3, in the above-described first to third bake process steps, because of a large number of mobile ions in the periphery of the floating gate after the program operation, the reference threshold value of the ideal threshold voltage when the program operation is performed on the memory cell is compared. The threshold voltage value is reduced. As such, the mobile ions included in the spacers formed on the sidewalls of the memory cell may adversely affect the reliability of the memory cell operation by changing the threshold voltage value of the memory cell.

In order to solve the problem of the variation of the threshold voltage due to the mobile ions included in the spacer, the nonvolatile memory device proposed by the present invention is shown in FIG. 1.

1 is a cross-sectional view illustrating a device for explaining a nonvolatile memory device according to the present invention.

Referring to FIG. 1, an active region in which a memory cell is formed in the semiconductor substrate 102 is recessed to a predetermined depth. The width to be recessed is equal to the width of the memory cell, and the depth to be recessed is less than half of the overall height of a typical memory cell.

Subsequently, a tunnel insulating film 104 is formed on the surface of the semiconductor substrate 102. In this case, the tunnel insulating layer 104 may be formed along the surface of the recess where the recess is formed. Then, the conductive film for forming the floating gate is formed on the tunnel insulating film 104, and the remaining conductive film except for the upper portion of the recess is removed and patterned to form the floating gate 106. Thus, the width of the floating gate 106 may be formed to be the same width as the recess.

In addition, an ion blocking layer 108 is formed on sidewalls of the floating gate 106 exposed on the semiconductor substrate 102. The ion blocking layer 108 may be formed of an insulating material such as Al ₂ O ₃ . Subsequently, the dielectric film 110 and the control gate 112 are formed on the floating gate 106, and spacers 114 are formed on sidewalls of the memory cell.

As described above, the nonvolatile memory device according to the present invention is formed on the recessed active region so that a part of the floating gate 106 is formed in the semiconductor substrate 102, so that the sidewall of the floating gate 106 is formed. The area facing the spacer 114 can be minimized. Therefore, even though a large number of electrons are introduced into the floating gate 106 due to the program operation of the memory cell, positively charged mobile ions, such as Ca + ions and K + ions, included in the spacer 114 are attracted to the floating gate 106. Minimize the movement around. In addition, the ion blocking layer 108 formed on the sidewall of the floating gate 106 facing the spacer 114 may further prevent mobile ions from approaching the periphery of the floating gate 106. In addition, since the memory cells are formed on the recessed regions of the semiconductor substrate 102, the overall height of the memory cells is lowered, so that subsequent etching processes and deposition processes between the memory cells can be performed more easily.

1 is a cross-sectional view illustrating a device for explaining a nonvolatile memory device according to the present invention.

2A-2C are schematic diagrams illustrating mobile ions included in a spacer of a memory cell at each bake step for verifying threshold voltage variations caused by mobile ions according to the present invention.

3 is a graph illustrating a reference value of an ideal threshold voltage when a program operation is performed on a memory cell and a threshold voltage value in the first to third bake process steps.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 104 tunnel insulating film

106: floating gate 108: ion blocking film

110 dielectric film 112 control gate

114: spacer

Claims (6)

A semiconductor substrate having a recess formed in the active region; A tunnel insulating film formed on the recess; A floating gate formed in the recess in which the tunnel insulating film is formed; An ion blocking film formed on sidewalls of the floating gate exposed on the semiconductor substrate; A dielectric film formed on the floating gate; A control gate formed on the dielectric film; And And a spacer formed on sidewalls of the control gate, the dielectric layer, and the passivation layer. The method of claim 1, The ion barrier layer is formed of Al ₂ O ₃ Non-volatile memory device. The method of claim 1, And the recess and the floating gate have the same width. Forming a recess in an active region of the semiconductor substrate; Forming a tunnel insulating film and a floating gate on the recess; Forming an ion blocking layer on sidewalls of the floating gate exposed on the semiconductor substrate; Forming a dielectric film on the floating gate; Forming a control gate on the dielectric film; And And forming spacers on sidewalls of the control gate, the dielectric layer, and the passivation layer. The method of claim 4, wherein The ion barrier layer is formed of Al ₂ O ₃ Nonvolatile memory device manufacturing method. The method of claim 4, wherein And forming the recesses and the floating gates in the same width.

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