KR20090056790A - Variable length code decoding system and decoding method thereof - Google Patents

Abstract

A system for decoding a VLC(Variable Length Code) and a decoding method thereof are provided to reduce gate count and reduce power consumption by uploading and using only the table information needed for a received frame. A CPU(100) receives a group picture and extracts a plurality of frames from the received group picture. A VLC decoder(200) decodes the frames received from the CPU. The VLC decoder stores table information, which is loaded from the CPU and is needed for decoding the frame, to an SRAM(210). The CPU included a picture layer(110) and a table manager(120). The picture layer decodes the group picture into a plurality of frames. The table manager receives the frame to be decoded and loads the table information to the SRAM.

Description

Variable length code decoding system and its decoding method {VARIABLE LENGTH CODE DECODING SYSTEM AND DECODING METHOD THEREOF}

The present invention relates to a variable length code decoding system and a decoding method thereof.

The present invention is derived from a study conducted as part of the Human Resource Development Project for IT SoC Architech of the Ministry of Information and Communication. [Task Management No.:, Title: IT SoC Core Design Manpower Training] .

In recent years, the era of multimedia that integrates audio, video and pixel values has arrived, and existing information media, namely newspapers, magazines, television, radios, telephones and other means of communicating information to people, have been in the range of recent multimedia. It has been included. In general, multimedia refers to not only letters but also graphic symbols, audio, and in particular, images that are related to each other. However, in order to include the existing information media described above in the scope of multimedia, it is shown as a necessary condition to express such information in digital form.

However, when calculating the amount of information contained in each of the above described information media in digital form, the amount of information per character is required to be 1 to 2 bytes, the audio is required to be 64 Kbits per second (telephone quality), and in case of moving pictures 100 Mbits per second (current television reception quality) is required. Therefore, it is not practical for the information media described above to handle this huge amount of information in digital form. Therefore, an information compression technique is required, and in the case of a video phone, for example, a video compression technique conforming to the H.261 and H.263 standards internationally standardized by the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T) Is used.

In general, in the coding of moving pictures, the amount of information is compressed by reducing redundancy in the direction of time and space. Therefore, in inter-screen predictive encoding to reduce temporal redundancy, motion estimation and generation of predictive images are performed in units of blocks with reference to the front or rear picture, and then the obtained predictive image and the image of the current picture to be encoded The encoding is performed at the difference value between them.

Here, "picture" is a term referring to one image. In the case of a progressive image, "picture" means a frame, and in the case of an interlaced image, a frame or field. Here, the "interlaced image" is an image of a frame consisting of two fields separated by capture time. In the encoding and decoding of interlaced images, it is possible to treat one frame as it is, to treat it as two fields, or to treat it as a frame structure or a field structure for each block in a frame. An image that is intra prediction coded without referring to any image is referred to as an I frame. A picture that is intra prediction coded with reference to only one picture is referred to as a P frame. The picture to be intra prediction coded with reference to two pictures at the same time is referred to as a B frame. The B frame is capable of referring to two pixels in which the front / rear picture can be arbitrarily combined in the display order.

The reference image (reference picture) may be designated for each block as a basic unit of encoding and decoding. The distinction between these reference pixels is achieved by calling the reference picture shown earlier in the coded bitstream as the first reference picture and calling the reference picture shown later in the bitstream as the second reference picture. Encoding and decoding these types of pictures As a condition for doing so, it is required that pictures used as a reference are previously encoded and decoded.

P frames and B frames are encoded using motion compensated inter prediction. Encoding by using motion compensated inter prediction is an encoding method using motion compensated in inter prediction encoding. Unlike the method of simply making predictions based on the pixel values of the reference picture, motion estimation estimates the amount of motion of each part in the picture (hereinafter referred to as a "motion vector"), and also makes a prediction in consideration of this amount of motion. This is a technique that can reduce the amount of data as well as improve the accuracy of prediction.

For example, the amount of data through motion compensation is estimated by estimating the motion vector of the current picture to be encoded, and then encoding the prediction error between the predicted value obtained by shifting only the amount of each motion vector and the current picture to be encoded. Can be reduced. In this technique, since motion vector information is required at the time of decoding, the motion vector is also recorded or transmitted in an encoded form. The motion vector is estimated in macroblock units. More specifically, the macroblock is fixed in advance in the current picture to be encoded, and the motion vector is estimated by finding the position of the most similar reference block of the macroblock fixed in the search area in the reference picture.

1 is a diagram illustrating a data structure of a general bitstream. Referring to FIG. 1, a bitstream includes a plurality of picture groups (hereinafter, referred to as 'GOP'). The GOP is used as a basic coding unit to perform access or to perform editing. Each GOP includes a plurality of pictures. In addition, each picture includes a plurality of slices. In addition, each slice includes a plurality of macro blocks. Each macro block also includes a plurality of blocks. On the other hand, each bitstream, GOP, picture, and slice includes a synchronization signal indicating the ending point of each unit and a header which is data common to each unit.

When data is not transmitted in the bit stream, which is a stream sequence, but in a packet or the like in pieces, the header and the data portion other than the header may be transmitted separately. In this case, the header and the data portion are not combined in the same bit stream as shown in FIG. However, in the case of a packet, even when the header and the data portion are not transmitted adjacently, the header corresponding to the data portion is transmitted in another packet. Therefore, even when the header and the data portion are not combined in the same bit stream, the concept of the coded bitstream described with reference to FIG. 1 is also applicable to a packet.

In general, variable length codes are used for various lossless data compression. Variable length codes are codes of fixed length data based on the statistical value of the data as variable length data. The variable length codes are frequently generated by the frequency of occurrence of each code included in the information source. It is indicated by the sign of. In this way, the average value of the code lengths can be reduced compared to assigning the same length to all codes. A typical variable length code is the Huffman code.

In the case of WMV9 / VC-1, when a variable length code (VLC) is decoded, a large amount of table information is required. This increases the gate count much compared to other codecs. In hardware, when the VLC decoder is implemented, the size of a ROM in which table information is stored is increased. In addition, the VLC decoder in portable products also increases power consumption due to frequent ROM access.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a variable length code decoding system and a decoding method thereof in which a gate count is reduced and power consumption is reduced.

A decoding method of a variable length code decoding system according to the present invention includes: extracting a frame from a picture group; Loading table information necessary to decode the extracted frame into the SRAM; And decoding the extracted frame using the loaded table information.

The extracting of the frame may include: receiving the picture group; And extracting a plurality of frames by decoding the input picture group.

In an embodiment, the extracting of the frame may be performed in a central processing unit.

The decoded plurality of frames may be decoded by a variable length code decoder in order.

In an exemplary embodiment, the CPU and the variable length code decoder may perform an interface on a frame basis.

The SRAM may be included in the variable length code decoder.

The loading of the table information into the SRAM may include: identifying, by the CPU, tables required for decoding the frame; And loading the grasped tables into the SRAM by the CPU.

The CPU may generate an operation signal for activating the variable length code decoder when the table information is loaded in the SRAM.

The variable length code decoder may transmit an interrupt signal to the CPU after the decoding of the extracted frame is completed.

In an exemplary embodiment, after the decoding of the extracted frame is completed, the variable length code decoder is in a waiting state until the operation signal for the next frame is transmitted from the CPU.

According to another aspect of the present invention, there is provided a variable length code decoding system comprising: a central processing unit receiving a group picture and extracting the same into a plurality of frames; And a variable length code decoder configured to receive the plurality of frames from the CPU and to decode the frames.

In an exemplary embodiment, the variable length code decoder stores table information necessary to decode a frame.

The variable length code decoder may include an SRAM for storing the table information, and the table information may be loaded from the CPU.

The CPU may include: a picture layer for decoding the group picture and extracting the extracted picture into a plurality of frames; And a table manager which receives a frame to be decoded among the extracted frames and loads table information necessary to decode the frame to be decoded into the SRAM.

The CPU may generate an operation signal for activating the variable length code decoder when the table information is loaded in the SRAM.

The variable length code decoder may include: a slice layer which decodes an input frame and extracts a plurality of slices; A macro block layer which decodes each extracted slice to extract a plurality of macro blocks; And a block layer for decoding each extracted macroblock to extract a plurality of blocks, wherein the slice layer, the macroblock layer, and the block layer use the table information stored in the SRAM when decoding. It features.

In an embodiment, when decoding of the frame is completed, the variable length code decoder sends an interrupt signal to the CPU, and the CPU prepares to decode the next frame in response to the interrupt signal. It features.

The table information may include a plurality of types of tables, and the SRAM may be divided into memories in which the plurality of types of tables are stored.

As described above, the variable length coding decoding system and its decoding method according to the present invention upload and use only table information necessary for an input frame, thereby reducing gate count and power consumption.

In addition, the variable length encoding decoding system of the present invention can be applied to a portable device with less internal memory and efficient in power consumption.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

The variable length code decoding system according to the present invention includes a variable length code (VLC) decoder that performs decoding on a frame basis. The variable length coder includes an SRAM in which only table information necessary to decode the current frame is loaded. As such, the decoding system of the present invention does not need to have all the table information in performing decoding. Therefore, the decoding system according to the present invention reduces the gate count during the decoding operation, and thus the power consumption is also reduced.

2 shows a variable length code decoding system 10 according to the present invention. Referring to FIG. 2, the variable length code decoding system 10 includes a central processing unit (CPU) 100 and a variable length code (VLC) decoder 200. The VLC decoder 200 of the present invention performs decoding on a frame basis and includes an SRAM 210 that stores table information necessary to decode the frame.

As shown in FIG. 2, the decoding system 10 uses an SRAM to store data information necessary to decode a frame. However, it will be apparent to those skilled in the art that an apparatus for storing data information necessary for decoding a frame by the decoding system of the present invention is not necessarily limited to SRAM. In the decoding system of the present invention, a volatile memory device such as a RAM may be used to store data necessary for decoding a frame.

The CPU 100 includes a picture layer 110 and a table manager 120. The picture layer 110 extracts a plurality of pictures from a group picture (hereinafter, referred to as a 'GOP'). In general, each picture is called a frame. That is, the picture layer 110 decodes the GOP and extracts a plurality of frames. Here, the plurality of frames extracted from the picture layer 110 are sequentially decoded by the VLC decoder 200. The table manager 120 receives a frame from the picture layer 110 and grasps table information necessary to decode the delivered frame. The table manager 120 loads the checked table information into the SRAM 210 of the VLC decoder 200.

On the other hand, the picture decoded from the picture layer 110, that is, the extracted frame includes the table information necessary to decode each frame. This table information depends on the type of frame. For example, when a frame is called an I frame, an CBPCY table, an AC differential table, and a DC differential table are required.

As described above, the CPU 100 performs a function of extracting a plurality of frames from the GOP and preparing the VLC decoder 200 to perform a decoding operation. That is, the central processing unit 100 transmits the frame to be decoded and table information necessary to decode the frame to the VLC decoder 200, and when loading of the table information to the SRAM 210 is completed, the VLC decoder 200. ) Transmits the operation signal DECEN. The VLC decoder 200 of the present invention performs decoding in units of frames. Thus, the CPU 100 is implemented to deliver the extracted frames to the VLC decoder 200 in turn.

The VLC decoder 200 starts decoding one frame input from the CPU 100 in response to the operation signal DECEN. Meanwhile, table information necessary to decode the frame is already loaded in the SRAM 210. The VLC decoder 200 performs a decoding operation on the input frame using the table information loaded on the SRAM 210.

The decoding operation on the frame of the VLC decoder 200 is as follows. The slice layer 220 decodes a frame input from the CPU 100 and extracts a plurality of slices. The macroblock layer 230 decodes each of the plurality of slices decoded in the slice layer 220 and extracts the plurality of macroblocks. The block layer 230 extracts each of the plurality of blocks by decoding each of the plurality of macroblocks decoded in the macroblock layer 230. The above-described process is repeated until decoding of the input frame is completed. When the decoding operation for the frame input from the CPU 100 is completed, the VLC decoder 200 transmits an interrupt signal to the CPU 100. At this time, the VLC decoder 200 is in a waiting state until receiving the next operation signal DECEN from the CPU 100.

The CPU 100 prepares a decoding operation for the next frame in response to the transmitted interrupt signal. That is, the frame to be decoded is transferred to the table manager 120, and table information corresponding to the frame to be decoded is loaded into the SRAM 210. In addition, when the loading of the table information to the SRAM 210 is completed, the CPU 100 transmits an operation signal DECEN to the VLC decoder 100. The VLC decoder 100 performs decoding on a newly input frame in response to the transferred operation signal DECEN.

In the variable length code decoding system 10 of the present invention, a picture layer 110 is included in the CPU 100. That is, the CPU 100 extracts a plurality of pictures, that is, frames, by decoding the GOP. Meanwhile, the VLC decoder 200 decodes only one frame transmitted from the CPU 100. That is, the CPU 100 and the VLC decoder 200 perform an interface on a frame basis. The variable length code decoding system 10 can significantly reduce the gate count of the VLC decoder while ensuring flexibility by using the minimum CPU performance.

3 is a diagram showing an embodiment of the SRAM 200 in the variable length code decoding system 10 of the present invention. Referring to FIG. 3, the VLC decoder 200 of the present invention includes a VLC decoder logic circuit 201 and SRAMs 212, 214, 216, and 218. Here, the VLC decoder logic circuit 201 is a portion of the VLC decoder 200 illustrated in FIG. 2 except for the SRAM 210. The SRAM 200 of the present invention includes an AC differential memory 212, an MV differential memory 214, a CBPCY memory 216, and a DC differential memory 218. The AC differential memory 212 is where the AC differential table is stored. The MV differential memory 214 is where the MV differential table is stored. CBPCY memory 216 is where the CBPCY table is stored. The DC differential memory 218 is where the DC differential table is stored. Each of the memories 212, 214, 216, 218 is loaded with tables necessary for decoding the frame to be decoded from the table manager 120 of the CPU 100.

Conventional VLC decoders have a ROM for storing all table information because decoding is performed in units of GOP. On the other hand, the VLC decoder of the present invention performs decoding on a frame basis and includes an SRAM for storing only a table necessary for decoding a frame. Thus, when considering the total table size and read / write operations, the VLC decoder of the present invention using SRAM has advantages over conventional VLC decoders in terms of gate count and power consumption.

In addition, in the case of a VLC decoder using a ROM, there is a disadvantage that an additional chip must be manufactured due to an error of the ROM data. On the other hand, VLC decoder using SRAM only has to change the data to be loaded, so there is no additional cost and the decoding time can be reduced.

As an example, the size of the SRAM of the VLC decoder of the present invention requires a memory size of at least 13.566 Kb. This memory size is only 34% of the total table size 39.532Kb used in conventional VLC decoders. The size of the SRAM memories required to implement this is shown in the table below.

SRAM Memory Types size AC differential memory  186 × 23/127 × 11/65 × 9 MV Differential Memory 72 × 14 CBCVY memory 64 × 11 DC differential memory 119 × 21/119 × 26

Here, the write operation of the SRAM 210 is controlled by the CPU 100. In addition, the VLC decoder logic circuit 201 performs only a read operation from the SRAM 210.

The SRAM 200 shown in FIG. 3 includes four memories 212, 214, 216, and 218. However, the SRAM of the present invention is not necessarily limited thereto. The SRAM of the present invention may be implemented as one memory.

4 is a flowchart illustrating a decoding method of the variable length code decoding system 10 according to the present invention. 2 to 4, a decoding method of the variable length code decoding system 10 according to the present invention is as follows.

The VLC decoder 200 of the variable length code decoding system 10 according to the present invention performs decoding on a frame basis. To this end, the CPU 100 extracts a plurality of frames from the GOP to be decoded. That is, the picture layer 110 decodes the GOP to extract a plurality of pictures, that is, a plurality of frames. Here, the plurality of frames will be decoded in the VLC decoder 200 in order (S110).

The frame extracted from the picture layer 110 is transferred to the table manager 120. The table manager 120 finds table information necessary to decode the extracted frame from the extracted frame, and loads the determined table information into the SRAM 210 (S120). When the loading of the table information to the SRAM 210 is completed, the CPU 100 transmits an operation signal DECEN to the VLC decoder 200 to start decoding the extracted frame. The VLC decoder 200 performs decoding on the extracted frame using the table information loaded on the SRAM 210 in response to the operation signal DECEN (S130). Here, the decoding operation on the frame is as shown in FIG. 2.

When decoding of the frame is completed, the VLC decoder 200 generates an interrupt signal and transmits the interrupt signal to the CPU 100. At this time, the VLC decoder 200 is in a waiting state until receiving the next operation signal DECEN. Meanwhile, the CPU 100 prepares a decoding operation for the next frame extracted in response to the interrupt signal. That is, the next frame is transferred to the table manager 120, and the table manager 120 finds out table information necessary to decode the delivered frame, and the determined table information is loaded into the SRAM 210. Thereafter, when the loading of the table information to the SRAM 210 is completed, the CPU 100 generates an operation signal DECEN and transmits the generated operation signal DECEN to the VLC decoder 200. The VLC decoder 200 performs a decoding operation on the next frame using the table information newly stored in the SRAM 210 as described above in response to the operation signal DECEN.

In the variable length code decoding system of the present invention, table information is loaded on an SRAM. However, it will be apparent to those skilled in the art that the variable length code decoding system of the present invention does not necessarily store table information in an SRAM. In the present invention, in addition to SRAM, a volatile memory device such as a DRAM or a nonvolatile memory device may be used as a memory device for storing table information.

The decoding system of the present invention is a system applied to the WMW9 / VC-1 reference decoder. However, it will be apparent to those skilled in the art that the decoding system of the present invention is not limited to the WMW9 / VC-1 reference decoder.

The variable length code decoding system of the present invention can be used for PMP, Mobile TV (DVB-H), Mobile Phone, and 4G terminal. In particular, since it uses less internal memory and is efficient in power consumption, it can be used in portable devices.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a diagram illustrating a data structure of a general bitstream.

2 is a diagram illustrating a variable length code decoding system according to the present invention.

3 is a diagram illustrating an embodiment of an SRAM in the variable length code decoding system according to the present invention.

4 is a flowchart illustrating a decoding method of a variable length code decoding system according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: variable length code decoding system

100: central processing unit 200: VLC decoder

110: picture layer 120: table manager

210: SRAM 220: slice layer

230: macroblock layer 240: block layer

212,214,216,218: SRAM

Claims (18)

In the decoding method of a variable length code decoding system: Extracting a frame from a picture group; Loading table information necessary for decoding the extracted frame into the volatile memory device; And And decoding the extracted frame by using the loaded table information. The method of claim 1, Extracting the frame, Receiving the picture group; And extracting a plurality of frames by decoding an input picture group. The method of claim 2, And extracting the frame is performed in a central processing unit. The method of claim 3, wherein And a plurality of decoded frames are sequentially decoded by a variable length code decoder. The method of claim 4, wherein And the central processing unit and the variable length code decoder perform an interface on a frame basis. The method of claim 4, wherein The volatile memory device is a variable length code decoding method, characterized in that the SRAM. The method of claim 6, The step of loading the table information on the SRAM, Identifying, by the central processing unit, tables necessary for decoding the frame; And And loading the determined tables by the CPU into the SRAM. The method of claim 7, wherein And when the table information is loaded into the SRAM, the CPU generates an operation signal for activating the variable length code decoder. The method of claim 8, And after the decoding of the extracted frame is completed, the variable length code decoder transmits an interrupt signal to the CPU. The method of claim 9, And after the decoding of the extracted frame is completed, the variable length code decoder is in a waiting state until the operation signal for the next frame is transmitted from the CPU. A CPU for receiving a group picture and extracting the group picture into a plurality of frames; And And a variable length code decoder configured to receive the plurality of frames from the CPU in units of frames and perform decoding. The method of claim 11, And the variable length code decoder stores table information necessary to decode a frame. The method of claim 12, The variable length code decoder includes an SRAM for storing the table information. And the table information is loaded from the CPU. The method of claim 13, The central processing unit, A picture layer for decoding the group picture and extracting the extracted picture into a plurality of frames; And And a table manager which receives a frame to be decoded among the extracted frames and loads table information necessary to decode the frame to be decoded into the SRAM. The method of claim 13, And the central processing unit generates an operation signal for activating the variable length code decoder when the table information is loaded into the SRAM. The method of claim 13, The variable length code decoder, A slice layer for decoding the input frame and extracting a plurality of slices; A macro block layer which decodes each extracted slice to extract a plurality of macro blocks; And It includes a block layer for extracting a plurality of blocks by decoding each extracted macro block, And the slice layer, the macro block layer, and the block layer use the table information stored in the SRAM when decoding. The method of claim 16, When decoding of the frame is completed, the variable length code decoder transmits an interrupt signal to the CPU, And the CPU prepares to decode a next frame in response to the interrupt signal. The method of claim 11, The table information includes a plurality of types of tables, And the SRAMs are divided into memories in which the plurality of types of tables are stored, respectively.

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