KR20090056286A - Voltage generator - Google Patents

Abstract

A voltage generator is provided to generate a stable voltage while reducing a ripple by controlling an oscillation period trough a link with a power voltage level. A high voltage level detector(100) detects the level of a high voltage outputted from a pumping area, and an oscillator(110) outputs a plurality of generation signals which have different periods each other and default signals. A power voltage level detection unit(120) is activated by an enable signal and outputs a plurality of detection signals. A power voltage driving unit(140) is controlled by the enable signal and output a plurality of driving signals by detecting a plurality of diction signals. An oscillation control unit(150) generates one of the plural generation signals according to a plurality of driving signals.

Description

Voltage generating device {VOLTAGE GENERATOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generator, and more particularly, a technique capable of generating a stable high voltage by reducing ripple by adjusting an oscillation period in conjunction with a power supply voltage level.

In the case of a semiconductor memory device, as the external power supply voltage is lowered and high speed operation is required, the word line voltage is boosted to secure a low voltage margin and improve the speed of sensing data from the memory cell.

For example, in a DRAM in which a memory cell is composed of one transistor and one capacitor, the cell transistor is composed of an NMOS transistor that occupies a smaller area than a PMOS transistor.

However, the NMOS transistor quickly transfers data '0', but in the case of data '1', the NMOS transistor drops as much as the threshold voltage Vth. Therefore, in order to read / write the complete external power supply voltage VDD into the cell without losing the threshold voltage, the high voltage VPP, which is a voltage larger than the threshold voltage of the cell transistor, is greater than the external power supply voltage VDD. use.

Since the high voltage VPP must maintain a potential higher than the external power supply voltage VDD, the semiconductor memory device boosts and uses the external power supply voltage VDD. In most DRAMs, a high voltage (VPP) is generated by using a charge pump method.

1 is a block diagram showing a conventional voltage generator.

The conventional voltage generator includes a level detector 10, an oscillator 20, a controller 30, and a charge pump 40.

The level detector 10 compares the high voltage output from the charge pump 40 with a preset reference voltage and outputs an enable signal to the oscillator 20 when the high voltage is smaller than the reference voltage.

The oscillator 20 performs an oscillation operation according to the enable signal, and the controller 30 receives an output of the oscillator 20 and outputs a control signal for performing a pumping operation. Then, the charge pump 40 performs a pumping operation according to the control signal to output a high voltage.

However, in the conventional voltage generator, when the level of the power supply voltage is low, the oscillation period of the oscillator 20 is increased, and when the level of the power supply voltage is high, the oscillation period is reduced. In particular, when the level of the power supply voltage is high, the peak-to-peak value of the high voltage is increased. That is, there is a problem that the high voltage does not maintain a stable level due to an increase in ripple voltage.

The present invention has been made to solve the above problems, and the purpose is to reduce the ripple to generate a stable high voltage by adjusting the oscillation period in conjunction with the power supply voltage level.

The voltage generating device according to the present invention comprises: an oscillator for outputting a plurality of oscillation signals having different periods; An enable unit for outputting an enable signal according to a preset signal and a test mode signal; A power supply voltage level detection unit activated by the enable signal and detecting a level of the power supply voltage and outputting a plurality of detection signals; A power supply voltage driver controlled by an enable signal and configured to drive a plurality of detection signals to output a plurality of driving signals; An oscillation controller for outputting any one of a plurality of oscillation signals as an oscillation control signal according to the plurality of driving signals; And a pumping unit configured to output a high voltage by performing a pumping operation according to the oscillation control signal.

The present invention provides an effect that can generate a stable high voltage by reducing the ripple by adjusting the oscillation period in conjunction with the power supply voltage level.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a block diagram showing a voltage generator according to the present invention.

The voltage generator of the present invention includes a high voltage level detector 100, an oscillator 110, a power voltage level detector 120, an enabler 130, a power voltage driver 140, an oscillation controller 150, and a controller 160. ) And charge pump 170.

The high voltage level detector 100 detects the level of the high voltage output from the charge pump 170 and outputs a signal for enabling the oscillator 110 when the high voltage is smaller than a desired level.

The oscillator 110 performs an oscillation operation according to the output of the high voltage level detector 100 to output a default signal OSC_DEFAULT, an oscillation signal OSC10, an oscillation signal OSC20, and an oscillation signal OSC30 having different periods. Here, the oscillation signal OSC10 has a shorter period than the default signal OSC_DEFAULT, the oscillation signal OSC20 and the oscillation signal OSC30, and the oscillation signal OSC30 preferably has a longer period than the default signal OSC_DEFAULT, the oscillation signal OSC10 and the oscillation signal OSC20. The oscillation signal OSC20 preferably has a period longer than the period of the oscillation signal OSC10 and shorter than the period of the oscillation signal OSC30. In addition, the default signal OSC_DEFAULT preferably has the same period as the oscillation signal OSC20.

The power supply voltage level detection unit 120 detects the level of the power supply voltage input from the outside according to the enable signal TDISVDET_OUT and outputs a detection signal DVDD16, a detection signal DVDD18, and a detection signal DVDD20 that interlock with the power supply voltage.

Here, the detection signal DVDD16 is a signal that is enabled as 'low' when the power supply voltage is 1.6V or more, and the detection signal DVDD18 is a signal enabled as 'low' when the power supply voltage is 1.8V or more. The detection signal DVDD20 is a signal that is enabled as 'low' when the power supply voltage is 2.0V or more.

The enable unit 130 outputs the enable signal TDISVET_OUT according to whether the fuse is cut or not and the test mode signal TDISVDET. Here, the test mode signal TDISVDET is a signal that is enabled at a high level during wafer or package test.

The power supply voltage driver 140 drives the detection signal DVDD16, the detection signal DVDD18, and the detection signal DVDD20 according to the enable signal TDISVDET_OUT to output the driving signal DVD16, the driving signal DVD18, and the driving signal DVD20.

The oscillation controller 150 outputs any one of a default signal OSC_DEFAULT, an oscillation signal OSC10, an oscillation signal OSC20, and an oscillation signal OSCCTRL according to the driving signal DVD16, the driving signal DVD18, and the driving signal DVD20 as an oscillation control signal OSCCTRL.

The controller 160 outputs a signal for controlling the pumping operation according to the oscillation control signal OSCCTRL. In addition, the charge pump 170 performs a pumping operation according to the output of the controller 160 to output a high voltage.

3 is a detailed circuit diagram of the enable unit 130 shown in FIG. 2.

The enable unit 130 includes a discharge unit 132, a precharge unit 134, and an output unit 136.

The discharge unit 132 includes NMOS transistors N1 and N2. The NMOS transistor N1 and the NMOS transistor N2 are connected in series between the node A and the ground voltage VSS applying terminal. The NMOS transistor N1 applies a pulse enable signal PUPB1 to the gate terminal. The NMOS transistor N2 operates as a constant current source by applying a power supply voltage VDD to a gate terminal. Each bulk terminal of the NMOS transistors N1 and N2 is connected to a ground voltage VSS applying terminal. Here, the pulse enable signal PUPB1 is a pulse signal enabled at a voltage level of 1V to 1.1V during initial operation.

The precharge unit 134 includes a PMOS transistor P1 and a fuse F1. The PMOS transistor P1 and the fuse F1 are connected in series between the supply voltage VDD applying end and the node A. The PMOS transistor P1 operates as a constant current source by receiving the ground voltage VSS through the gate terminal. The bulk terminal of the PMOS transistor P1 is connected to the supply voltage VDD application terminal.

The output unit 136 includes NMOS transistors N3, inverters IV1, IV2 and NOR gate NOR1. The NMOS transistor N3 is connected between the node A and the ground voltage VSS applying terminal to receive the output of the inverter IV1 through the gate terminal. The bulk terminal of the NMOS transistor N3 is connected to the ground voltage VSS application terminal.

The inverter IV1 is driven by the power supply voltage VDD and the ground voltage VSS to invert the voltage of the node A. Here, inverter IV1 and NMOS transistor N3 operate as latching means for latching the potential of node A. As shown in FIG.

The inverter IV2 is driven by the power supply voltage VDD and the ground voltage VSS, and inverts the output of the NOR gate NOR1 to output the enable signal TDISVDET_OUT. In addition, the NOR gate NOR1 performs a NOR operation by receiving the output of the inverter IV1 and the test mode signal TDISVDET.

Here, the operation of the enable unit 130 will be described.

First, when the pulse enable signal PUPB1 is applied as a high pulse during the initial operation, the NMOS transistor N1 is turned on. At this time, the NMOS transistor N2 is turned on by the power supply voltage VDD. As a result, the node A is discharged to the ground voltage VSS level.

Then, when the fuse F1 is not cut, the node A is precharged to the power supply voltage VDD level by the PMOS transistor P1. Then, the output of the inverter IV1 becomes the ground voltage VSS level, so that the NMOS transistor N3 remains turned off.

Then, the state of the enable signal TDISVDET_OUT is determined according to the state of the test mode signal TDISVDET. That is, when the test mode signal TDISVDET is enabled at a high level, the enable signal TDISVDET_OUT is enabled at a high level, and when the test mode signal TDISVDET is disabled at a low level, the enable signal TDISVDET_OUT is disabled at a low level.

On the other hand, when fuse F1 is cut, node A maintains the ground voltage VSS level. Then, the output of the inverter IV1 becomes the power supply voltage VDD level, and the NMOS transistor N3 is turned on. Accordingly, the enable signal TDISVDET_OUT is enabled to a high level regardless of the state of the test mode signal TDISVDET.

4 is a detailed circuit diagram of the power supply voltage level detector 120 of FIG. 2.

The power supply voltage level detector 120 includes a detection voltage generator 121, differential amplifiers 122, 124, and 126, and drivers 123, 125, and 127.

The detection voltage generator 121 includes resistors R1 to R5. The resistor R1 and the resistor R2 are connected in series between the supply voltage VDD applying stage and the detection voltage TVDIV <2> output terminal, and the resistor R3 is connected between the detection voltage TVDIV <2> output terminal and the detection voltage TVDIV <1> output terminal. The resistor R4 is connected between the detection voltage TVDIV <1> output terminal and the detection voltage TVDIV <0> output terminal. The resistor R5 is connected between the detection voltage TVDIV <0> output terminal and the ground voltage VSS application terminal.

The differential amplifier 122 includes PMOS transistors P2 and P3 and NMOS transistors N4 to N7. The source terminals of the PMOS transistors P2 and P3 are commonly connected to the supply voltage VDD applying terminal, and each gate terminal is commonly connected to the drain terminal of the PMOS transistor P2.

The NMOS transistor N4 is connected between the drain terminal of the PMOS transistor P2 and the drain terminal of the NMOS transistor N6 to receive the reference voltage VFREI1 through the gate terminal. The NMOS transistor N5 is connected between the drain terminal of the PMOS transistor P3 and the drain terminal of the NMOS transistor N6 to receive the detection voltage TVDIV <2> through the gate terminal.

 The NMOS transistors N6 and NMOS transistor N7 are connected in series between the common source terminal of the NMOS transistor N4 and the NMOS transistor N5 and the ground voltage VSS applying terminal. The NMOS transistor N6 receives a bias voltage VLNG at its gate terminal, and the NMOS transistor N7 receives an enable signal TDISVDET_OUT at its gate terminal.

Here, the reference voltage VREFI1 and the bias voltage VLNG preferably have a constant voltage level irrespective of changes in process, voltage, and temperature (PVT). For example, the reference voltage VREFI1 has a level of 0.75V, and the bias voltage VLNG has a level of 0.83V.

The driver 123 includes inverters IV3 and IV4. The inverter IV3 is driven by the power supply voltage VDD and the ground voltage VSS to invert the output OUT2 of the differential amplifier 122. The inverter IV4 is driven by the power supply voltage VDD and the ground voltage VSS, and inverts the output of the inverter IV2 to output the detection signal DVDD16.

The differential amplifier 124 includes PMOS transistors P4 and P5 and NMOS transistors N8 to N11. The source terminals of the PMOS transistors P4 and P5 are commonly connected to the supply voltage VDD applying terminal, and each gate terminal is commonly connected to the drain terminal of the PMOS transistor P4.

The NMOS transistor N8 is connected between the drain terminal of the PMOS transistor P4 and the drain terminal of the NMOS transistor N10 to receive the reference voltage VFREI1 through the gate terminal. The NMOS transistor N9 is connected between the drain terminal of the PMOS transistor P5 and the drain terminal of the NMOS transistor N10 to receive the detection voltage TVDIV <1> through the gate terminal.

 The NMOS transistors N10 and NMOS transistor N11 are connected in series between the common source terminal of the NMOS transistor N8 and the NMOS transistor N9 and the ground voltage VSS applying terminal. The NMOS transistor N10 receives a bias voltage VLNG at its gate terminal, and the NMOS transistor N11 receives an enable signal TDISVDET_OUT at its gate terminal.

The driver 125 includes inverters IV5 and IV6. The inverter IV5 is driven by the power supply voltage VDD and the ground voltage VSS to invert the output OUT1 of the differential amplifier 124. The inverter IV6 is driven by the power supply voltage VDD and the ground voltage VSS, and inverts the output of the inverter IV5 to output the detection signal DVDD18.

The differential amplifier 126 includes PMOS transistors P6 and P7 and NMOS transistors N12 to N15. The source terminals of the PMOS transistors P6 and P7 are commonly connected to the supply voltage VDD applying terminal, and each gate terminal is commonly connected to the drain terminal of the PMOS transistor P6.

The NMOS transistor N12 is connected between the drain terminal of the PMOS transistor P6 and the drain terminal of the NMOS transistor N14 to receive the reference voltage VFREI1 through the gate terminal. The NMOS transistor N13 is connected between the drain terminal of the PMOS transistor P7 and the drain terminal of the NMOS transistor N14 to receive the detection voltage TVDIV <0> through the gate terminal.

 The NMOS transistors N14 and NMOS transistor N15 are connected in series between the common source terminal of the NMOS transistor N12 and the NMOS transistor N13 and the ground voltage VSS applying terminal. The NMOS transistor N14 receives a bias voltage VLNG at its gate terminal, and the NMOS transistor N15 receives an enable signal TDISVDET_OUT at its gate terminal.

The driver 127 includes inverters IV7 and IV8. The inverter IV7 is driven by the power supply voltage VDD and the ground voltage VSS to invert the output OUT0 of the differential amplifier 126. The inverter IV8 is driven by the power supply voltage VDD and the ground voltage VSS, and inverts the output of the inverter IV7 to output the detection signal DVDD20.

Here, the operation of the power supply voltage level detector 120 will be described.

First, the power supply voltage VDD is divided by resistance and the detection voltages TVDIV <0: 2> are respectively output. At this time, the detection voltage TVDIV <2> has a voltage level of {(R3 + R4 + R5) / (R1 + R2 + R3 + R4 + R5)} × VDD, and the detection voltage TVDIV <1> is {(R4 + R5). ) / (R1 + R2 + R3 + R4 + R5)} × VDD}. The detection voltage TVDIV <0> has a voltage level of {(R5) / (R1 + R2 + R3 + R4 + R5)} × VDD}. That is, the level of the detection voltage TVDIV <0: 2> changes in conjunction with the power supply voltage VDD.

The differential amplifiers 122, 124, and 126 are then enabled by the enable signal TDISVDET_OUT and the bias voltage VLNG to compare and amplify the voltage levels of the reference voltage VREFI1 and the detection voltage TVDIV <0: 2>, respectively. That is, if the voltage level of the detection voltage TVDIV <0: 2> is lower than the reference voltage VREFI1, the output signal OUT2 is output at a high level. If the voltage level of the detection voltage TVDIV <0: 2> is higher than the reference voltage VREFI1, the output signal OUT is higher. <0: 2> is output at the low level.

For example, when the power supply voltage VDD becomes a level (low region) of 1.6 V or more, the detection voltage TVDIV <2> is first higher than the reference voltage VREFI1 so that the output signal OUT2 is output at a low level. At this time, since the detection voltage TVDIV <0: 1> is at a level lower than the reference voltage VREFI1 due to resistance distribution, the output signal OUT1 and the output signal OUT0 are output at a high level.

When the power supply voltage VDD is at a level of 1.8V or more (normal region), the detection voltage TVDIV <1> is next higher than the reference voltage VREFI1 and the output signal OUT1 is output at a low level. At this time, since the detection voltage TVDIV <2> is higher than the reference voltage VREFI1, the output signal OUT2 maintains a low level, and the output signal OUT0 maintains a high level.

When the power supply voltage VDD reaches a level of 2.0V or more (high region), the detection voltage TVDIV <0> is finally higher than the reference voltage VREFI1 so that the output signal OUT0 is output at a low level. That is, when the power supply voltage VDD level is increased, the detection signal DVDD16, the detection signal DVDD18, and the detection signal DVDD20 are enabled in the order. When the power supply voltage VDD level is lowered, it is enabled in the reverse order.

5 is a detailed circuit diagram of the power supply voltage driver 140 shown in FIG. 2.

The power supply voltage driver 140 includes a first driving signal generator 142, a second driving signal generator 144, and a third driving signal generator 146.

The first driving signal generator 142 includes inverters IV9 to IV11 and NOR gate NOR2. Inverter IV9 is driven by supply voltage VDD and ground voltage VSS to invert the enable signal TDISVDET_OUT. Inverter IV10 is driven by supply voltage VDD and ground voltage VSS to invert the output of NOR gate NOR2. The inverter IV11 is driven by the power supply voltage VDD and the ground voltage VSS, and inverts the output of the inverter IV10 to output the drive signal DVD16. The NOR gate NOR2 receives the output of the detection signal DVDD16 and the inverter IV9 to perform a NOR operation.

The second driving signal generator 144 includes inverters IV12 to IV14 and a NOR gate NOR3. Inverter IV12 is driven by supply voltage VDD and ground voltage VSS to invert the enable signal TDISVDET_OUT. Inverter IV13 is driven by supply voltage VDD and ground voltage VSS to invert the output of NOR gate NOR3. The inverter IV14 is driven by the power supply voltage VDD and the ground voltage VSS, and inverts the output of the inverter IV13 to output the drive signal DVD18. The NOR gate NOR3 receives the output of the detection signal DVDD18 and the inverter IV12 to perform a NOR operation.

The third driving signal generator 146 includes inverters IV15 to IV17 and NOR gate NOR4. Inverter IV15 is driven by supply voltage VDD and ground voltage VSS to invert the enable signal TDISVDET_OUT. Inverter IV16 is driven by supply voltage VDD and ground voltage VSS to invert the output of NOR gate NOR4. The inverter IV17 is driven by the power supply voltage VDD and the ground voltage VSS, and inverts the output of the inverter IV16 to output the drive signal DVD20. The NOR gate NOR4 receives the output of the detection signal DVDD20 and the inverter IV15 to perform NOR operation.

Here, the operation of the power voltage driver 140 will be described.

When the test mode signal TDISVDET_OUT is enabled at a high level, the states of the drive signals DVD16, DVD18, DVD20 are determined according to the states of the detection signals DVDD16, DVDD18, and DVDD20. For example, when the detection signal DVDD16 is enabled at the low level, the driving signal DVD16 is enabled at the high level through the NOR gates NOR2, the inverters IV10, and IV11.

On the other hand, when the test mode signal TDISVDET_OUT is disabled at the low level, the driving signals DVD16, DVD18, and DVD20 are disabled at the low level irrespective of the detection signals DVDD16, DVDD18, and DVDD20.

FIG. 6 is a detailed circuit diagram of the oscillation controller 150 shown in FIG. 2.

The oscillation controller 150 includes a transfer unit 151, 152, 153, an oscillation signal selector 154, and a selection signal generator 155.

The transfer unit 151 includes inverters IV18 and IV19 and transmission gates TG1 and TG2. The inverter IV18 is driven by the power supply voltage VDD and the ground voltage VSS to invert the drive signal DVD16. The inverter IV19 is driven by the power supply voltage VDD and the ground voltage VSS to invert the drive signal DVD18. The transfer gate TG1 outputs the oscillation signal OSC10 in accordance with the output of the drive signal DVD16 and inverter IV18. The transfer gate TG2 outputs the output of the transfer gate TG1 to the output terminal B in accordance with the outputs of the drive signals DVD18 and inverter IV19.

The transfer unit 152 includes inverters IV20 and IV21 and transmission gates TG3 and TG4. The inverter IV20 is driven by the power supply voltage VDD and the ground voltage VSS to invert the drive signal DVD18. The inverter IV21 is driven by the power supply voltage VDD and the ground voltage VSS to invert the drive signal DVD20. The transfer gate TG3 outputs the oscillation signal OSC20 in accordance with the output of the drive signal DVD18 and inverter IV20. The transfer gate TG4 outputs the output of the transfer gate TG3 to the output terminal B in accordance with the outputs of the drive signals DVD20 and inverter IV21.

The transfer unit 153 includes an inverter IV22 and a transmission gate TG5. The inverter IV22 is driven by the power supply voltage VDD and the ground voltage VSS to invert the drive signal DVD20. The transfer gate TG5 outputs the oscillation signal OSC30 to the output terminal B in accordance with the outputs of the drive signals DVD20 and inverter IV22.

The oscillation signal selector 154 includes an AND gate AND and a NOR gate NOR5 and NOR6. The AND gate AND performs an AND operation by applying the potential of the node B and the selection signal DVD. The NOR gate NOR5 is driven by the power supply voltage VDD and the ground voltage VSS, and is subjected to the NOA operation by receiving the default signal OSC_DEFAULT and the selection signal DVD. The NOR gate NOR6 is driven by the power supply voltage VDD and the ground voltage VSS, and is subjected to NOR operation by applying the output of the AND gate AND and the output of the NOA gate NOR5 to output the oscillation control signal OSCCTRL.

The selection signal generator 155 includes a NOR gate NOR7 and an inverter IV23. The NOR gate NOR7 is driven by the power supply voltage VDD and the ground voltage VSS, and is subjected to the NOA operation by receiving the driving signal DVD16, the driving signal DVD18, and the driving signal DVD20. The inverter IV23 is driven by the power supply voltage VDD and the ground voltage VSS, and inverts the output of the NOR gate NOR7 to output the selection signal DVD.

Here, the operation of the oscillation controller 150 will be described.

First, when the drive signal DVD16 is enabled at a high level, the transfer gate TG1 is turned on. At this time, the drive signal DVD18 and the drive signal DVD20 are disabled at a low level. Accordingly, the transfer gate TG2 and the transfer gate TG4 are turned on, and the transfer gate TG3 and the transfer gate TG5 remain turned off.

Then, the oscillation signal OSC10 is output to the output terminal B via the transfer gates TG1, TG2 and TG4. At this time, the selection signal generator 155 outputs the selection signal DVD at a high level. Therefore, oscillation signal OSC10 is output as oscillation control signal OSCCTRL.

On the other hand, when the driving signals DVD16, DVD18, and DVD20 are all disabled at the low level, the transfer gates TG1 to TG5 are all turned off. The selection signal DVD is output at a low level. Therefore, the default signal OSC_DEFAULT is output as the oscillation control signal OSCCTRL.

Referring to the overall operation of the present invention having the configuration as described above are as follows.

First, when the high voltage output from the charge pump 170 does not reach a desired voltage level, the high voltage level detector 100 enables the oscillator 110. Next, the oscillator 110 performs an oscillation operation and outputs oscillation signals OSC_DEFAULT, OSC10, OSC20, and OSC30.

In this state, when the test mode signal TDISVDET is enabled at the high level, the enable unit 130 enables the enable signal TDISVDET_OUT at the high level.

Then, the power supply voltage level detection unit 120 is enabled to selectively enable the detection signals DVDD16, DVDD18, and DVDD20 that interlock with the level of the power supply voltage VDD. Hereinafter, the case where the detection signal DVDD16 is enabled will be described as an example.

Then, the power supply voltage driver 140 drives the detection signal DVDD16 to output the driving signal DVD16. The oscillation controller 150 then outputs the oscillation signal OSC10 as the oscillation control signal OSCCTRL by the drive signal DVD16. Then, the controller 160 pumps the charge pump 170 according to the oscillation control signal OSCCTRL.

That is, in the present invention, when the power supply voltage VDD is 1.6 V or more, the detection signal DVDD16 is enabled to perform the pumping operation by the oscillation signal OSC10 having a short period. When the power supply voltage VDD is 2.0 V or more, the detection signal DVDD20 is enabled to perform the pumping operation by the oscillation signal OSC20 having a long cycle. Therefore, high voltage VPP can be generated at a stable level.

Meanwhile, when the test mode signal TDISVDET is disabled at a low level, the enable unit 130 disables the enable signal TDISVDET_OUT at a low level. Then, the oscillation controller 150 outputs the oscillation signal OSC_DEFAULT as the oscillation control signal OSCCTRL.

Accordingly, the present invention reduces the oscillation period in the region where the power supply voltage VDD level is low, and increases the oscillation period in the region where the power supply voltage VDD level is high, thereby increasing the peak-to-peak value of the high voltage. The phenomenon can be prevented. That is, the ripple voltage can be reduced to generate a high level of stable voltage.

1 is a block diagram showing a conventional voltage generator.

2 is a block diagram showing a voltage generating device according to the present invention;

3 is a detailed circuit diagram of an enable unit illustrated in FIG. 2.

4 is a detailed circuit diagram of a power supply voltage level detector shown in FIG. 2;

5 is a detailed circuit diagram of the power supply voltage driver shown in FIG. 2;

FIG. 6 is a detailed circuit diagram of the oscillation controller shown in FIG. 2. FIG.

Claims (18)

A high voltage level detector for detecting a level of the high voltage output from the pumping unit; An oscillator for outputting a plurality of oscillation signals and default signals having different periods according to the output of the high voltage level detector; An enable unit for outputting an enable signal according to a preset signal and a test mode signal; A power supply voltage level detector activated by the enable signal and configured to detect a level of the power supply voltage and output a plurality of detection signals; A power supply voltage driver controlled by the enable signal and configured to drive the plurality of detection signals to output a plurality of driving signals; An oscillation controller for outputting any one of the plurality of oscillation signals as an oscillation control signal according to the plurality of driving signals; And The pumping unit for outputting the high voltage by performing a pumping operation in accordance with the oscillation control signal Voltage generating device comprising a. The voltage generator of claim 1, wherein the predetermined signal is a signal set by fuse cutting. The method of claim 2, wherein the enable portion A discharge unit configured to discharge the first node to a ground voltage according to a pulse enable signal; A precharge unit configured to precharge the first node to the power supply voltage according to whether the fuse is cut; And An output unit configured to logically combine the test mode signal and the potential of the first node to output the enable signal Voltage generating device comprising a. 4. The voltage generator of claim 3, wherein the discharge unit further comprises a first constant current source. 4. The voltage generating device of claim 3, wherein the precharge unit further comprises a second constant current source. 4. The voltage generating device of claim 3, wherein the output unit further comprises latching means for latching a potential of the first node. The apparatus of claim 3, wherein the enable unit activates the enable signal when the test mode signal is activated or the fuse is cut. The method of claim 1, wherein the power supply voltage level detector A detection voltage generator for distributing resistance of the power supply voltage to output a plurality of detection voltages interlocked with the power supply voltage; A plurality of differential amplifiers for comparing and amplifying a reference voltage and the plurality of detection voltages according to the enable signal, respectively; And A plurality of driving units for outputting the plurality of detection signals by driving the output of the plurality of differential amplifiers, respectively Voltage generating device comprising a. 9. The voltage generator of claim 8, wherein the plurality of detection voltages have different levels. 9. The voltage generating device of claim 8, wherein the plurality of driving units each include a first buffer means. The apparatus of claim 1, wherein the power supply voltage driver comprises a plurality of driving signal generators configured to logically combine the enable signal and the plurality of detection signals to generate the plurality of driving signals. The voltage generator of claim 11, wherein the plurality of driving signal generators activates the driving signal when the detection signal is activated while the enable signal is activated. 12. The voltage generator of claim 11, wherein each of the plurality of driving signal generators further includes a second buffer means at an output terminal. The method of claim 1, wherein the oscillation control unit A transfer unit configured to output any one of the plurality of oscillation signals according to the plurality of detection signals; A selection signal generator for outputting a selection signal by logically combining the plurality of detection signals; And An oscillation signal selection unit outputting the output of the transfer unit or the default signal as the oscillation control signal according to the selection signal Voltage generating device comprising a. 15. The voltage generator of claim 14, wherein the transfer unit comprises a plurality of transmission means for selectively transmitting the plurality of oscillation signals, respectively, according to the plurality of detection signals. 15. The voltage generator of claim 14, wherein the selection signal generator activates the selection signal when all of the plurality of detection signals are activated. 15. The apparatus of claim 14, wherein the oscillation signal selection unit outputs the output of the transfer unit as the oscillation control signal when the selection signal is activated, and outputs the default signal as the oscillation control signal when the selection signal is inactivated. Voltage generator. The voltage generator of claim 1, further comprising a control unit for controlling the charge pump according to the oscillation control signal.

Images