KR100734321B1 - Semiconductor memory device and driving method thereof - Google Patents

Abstract

A semiconductor memory device and a driving method thereof are provided to perform a stable equalizing operation at a lower external voltage, by driving a low level of a bit line equalizing signal controlling a bit line equalizer circuit with a body bias voltage having a negative voltage value. A first and a second memory block(510,520) include a number of memory cells storing data. A sense amplifier is shared between the first and the second memory block, and writes or reads data to or from the memory cell through a bit line pair. A bit line equalizing signal generation part(530) generates a bit line equalizing signal. A bit line equalizer circuit(512,522) precharges the bit line pair with a bit line precharge voltage in response to the bit line equalizing signal. The bit line equalizer circuit includes PMOS transistors and the bit line equalizing signal has a negative voltage value.

Description

Semiconductor memory device and driving method thereof

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a memory device having a general shared sense amplifier structure.

2 is an operation waveform diagram of a conventional low voltage semiconductor memory device.

3 is a circuit diagram illustrating a bit line equalizing circuit in a semiconductor memory device according to the present invention.

FIG. 4 is an operational waveform diagram of the semiconductor memory device of the present invention having the bit line equalizing circuit shown in FIG. 3.

5 is a diagram illustrating a semiconductor memory device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a driving method for efficiently equalizing a pair of bit lines and complementary bit lines, and a memory device using the same.

Among semiconductor memory devices, a DRAM senses and amplifies data stored in a memory cell using a sense amplifier. The sense amplifier is connected to the bit line of the memory cell to determine the memory cell data by comparing the bit level precharge voltage with the voltage level charged to the bit line. The sense amplifier block may be connected to one memory block to sense memory cells in the memory block, but may be shared to two memory blocks and selectively connected to one memory block to sense memory cells in the selected memory block. have.

1 is a diagram illustrating a memory device having a general shared sense amplifier structure. Referring to this, the shared sense amplifier structure includes a bit line equalizer circuits 112 and 122, bit line isolation circuits 116 and 126, a sense amplifier circuit between two memory blocks 110 and 120. 129, and the column select circuit 140 is arranged. The bit line equalizer circuits 112 and 122 perform bit line precharge on the bit lines BL and / BL in the first memory block 110 and the second memory block 120 before the sensing operation of the memory cell data. Precharge to voltage VBL. When the first bit line isolation circuit 116 senses memory cell data in the first memory block 110, the first bit line isolation circuit 116 detects the bit lines BL and / BL of the first memory block 110. Connect with In this case, the second bit line isolation circuit 126 cuts off the connection between the sense amplifier circuit 129 and the bit lines BL and / BL of the second memory block 120. On the contrary, when the second bit line isolation circuit 126 connects the bit lines BL and / BL of the second memory block 120 and the sense amplifier circuit 129, the first bit line isolation circuit 116 may be used. ) Disconnects the bit lines BL and / BL of the first memory block 110 from the sense amplifier circuit 129. The column select circuit 140 transfers memory cell data in the first or second memory blocks 110 and 120 sensed by the sense amplifier circuit 129 to the data input / output lines IO and IOB.

In the shared sense amplifier structure, a process of sensing the memory cell MC0 data in the first memory block 110 and sensing the memory cell MC1 in the second memory block 120 will be described below. First, the signal controller 131 receives an address signal and a bit line equalizer enable signal and receives a control signal through the first node N1 to select the first or second memory blocks 110 and 120. The signal holding unit 133 outputs the control signal to the level shifter 137 through an even number of inverters so that the received control signal is transferred in a circular manner. After setting the high and low discrimination criteria through the level shifter 137, the output signal of the level shifter 137 input to the signal driver 135 passes through the second node N2, and then the first and second bit line equalizing signals. It is applied as (PEQi, PEQj).

If the first and second bit line equalizing signals PEQi and PEQj are at a high level of the external voltage VEXT level, the bit line BL and the complementary bit line / BL are at the bit line precharge voltage VBL level. To be precharged. Thereafter, in order to sense the memory cell MC0 in the first memory block 110, the first bit line equalizing signal PEQi becomes a low level at the ground voltage VSS level and the first bit line isolation signal. PISOi becomes the high level of the boosted voltage VPP level, word line WLn-1 of the memory cell MC0 is enabled to the boosted voltage VPP level, and the memory cell MC0 data becomes the bit line. Charge sharing is performed through the BL to the sense amplifier circuit 129. The sense amplifier circuit 129 compares the voltage level of the charged share bit line BL with the bit line precharge voltage VBL of the complementary bit line / BL to determine memory cell data.

Next, in order to sense the memory cell MC1 in the second memory block 120, the second bit line equalizing signal PEQj becomes a low level of the ground voltage VSS level, and the word line WL1 is boosted. Enabled to the voltage VPP level, the second bit line isolation signal PISOj becomes the high level of the boosted voltage VPP level, so that memory cell MC1 data is charged share via the bit line BL. The ring is transmitted to the sense amplifier circuit 129. At this time, the first bit line equalizing signal PEQi is at the high level of the external voltage VEXT level, thereby converting the bit lines BL and / BL in the first memory block 110 into the bit line precharge voltage VBL. Precharge with).

Here, the first bit line equalizing signal PEQi is raised from the low level of the ground voltage VSS level to the high level of the external voltage VEXT level so that the bit lines BL and / BL are bit line precharged. The rate of precharging with the voltage VBL is related to the gate-source voltage Vgs of the first equalizer transistor 113 and the second equalizer transistor 114. The first equalizer transistor 113 and the second equalizer transistor 114 are composed of NMOS transistors.

In order to satisfy the low voltage operation of the DRAM, the external voltage VEXT level is gradually lowered, for example, about 1.0V, and the internal voltage VINT level is about 1.0V along the external voltage VEXT level, and bit line precharge is performed. Assume that the voltage VBL is set to about 0.5V corresponding to half the level of the internal voltage VINT. Then, the gate-source voltage Vgs of the first and second equalizer transistors 113 and 114 is about 0.5V. If the threshold voltages of the first and second equalizer transistors 113 and 114 are 0.5 V or more, the first and second equalizer transistors 113 and 114 are not sufficiently turned on, as shown in FIG. 2. In the precharge region, the bit lines BL and / BL are not precharged to the same level. Therefore, the bit line equalizer signals PEQi and PEQj applied to the gates of the first and second equalizer transistors 113 and 114 should have a voltage level greater than or equal to the external voltage VEXT.

In order to solve this problem, a method of pumping the bit line equalizer signals PEQi and PEQj above the external voltage VEXT level when the DRAM is in a low voltage operation has been provided. In this case, although the DRAM is in a low voltage operation mode for satisfying low power consumption, the DRAM has a problem in that a large current is consumed due to an increase in pumping current.

In addition, a method of lowering the threshold voltage of the NMOS transistor has been proposed. This is because lowering the threshold voltage tends to increase the current when the transistor is turned off, resulting in better precharge operation. However, while the precharge operation is well performed, an off current flows to the first equalizer transistor 113 when the cell capacitor and the bit line perform the charge sharing operation or the bit line sensing operation, thereby causing the bit line sensing fail. A failure occurs and even if the sensing is successful, a ground node and a DC path are generated, and a large amount of current is generated. In particular, equalizer transistors generally use a narrow width for layout area problems. In this case, the low current process tends to increase the off current.

Accordingly, an object of the present invention is to provide a semiconductor memory device having an equalizer capable of stably performing an equalizing operation even at low power consumption.

Another object of the present invention is to provide a method of driving a semiconductor memory device capable of stably performing an equalizing operation even at low power consumption.

In order to achieve the above technical problem, the present invention provides a PMOS type equalizer circuit in place of the existing NMOS type bit line equalizer circuit, and provides an equalizing signal generator capable of controlling the PMOS type equalizer circuit more efficiently. .

More specifically, the semiconductor memory device according to the present invention for achieving the above technical problem, the first and second memory blocks including a plurality of memory cells for storing data, between the first and second memory blocks A sense amplifier that writes and reads data into and reads data from the memory cells through a pair of bit lines, a bit line equalizing signal generator for generating a bit line equalizing signal, and the bit line in response to the bit line equalizing signal And a bit line equalizer circuit for precharging the pair to a bit line precharge voltage, in particular said bit line equalizer circuit comprising PMOS transistors and said bit line equalizing signal having a negative voltage value. It is done.

According to a preferred embodiment, the bit line equalizing signal generator is a signal controller for receiving an address signal and an equalizing enable signal and generating a predetermined control signal, and maintaining the control signal for receiving and transmitting the control signal without loss. A level shifter for shifting a low level of an output signal of the signal retainer to the negative voltage value; And a signal driver configured to receive an output signal of the level shifter and provide the bit line equalizing signal to the equalizer circuit.

The bit line equalizing signal generating unit may further include an inverting unit connected between the signal holding unit and the level shifter and inverting a phase of an output signal of the signal holding unit and outputting the inverted phase to the level shifter.

According to another aspect of the present invention, there is provided a method of driving a semiconductor memory device, the method comprising: generating a control signal by receiving an address signal and an equalizing enable signal, and maintaining the level of the control signal using an even number of inverters Adjusting the low level of the held control signal to a body bias voltage having a negative voltage value, and providing the adjusted control signal to the bit line equalizer circuit as a bit line equalizing signal. It features.

The driving method of the semiconductor memory device according to the present invention may further include inverting a phase of the held control signal before the adjusting.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a circuit diagram illustrating a bit line equalizing circuit in a semiconductor memory device according to the present invention. The bit line equalizing circuit shown in FIG. 3 is a PMOS type bit line equalizer and includes first, second, and third PMOS equalizer transistors 310, 320, and 330. When the equalizing signal PEQi is applied to the PMOS bit line equalizer at a high level during a sensing operation and a low level during a precharge operation, the first, second, and third PMOS equalizer transistors 310, 320, The transistor having the lowest gate-source voltage Vgs among the 330 becomes the third PMOS transistor 330. For example, when the threshold voltage VTH of the PMOS transistor is 0.7 V, 1.5 V is applied as the bit line equalizing signal PEQi during sensing, and a negative voltage value, that is, VBB (−) during precharge operation, is applied. 0.7V), the Vgs value of the third PMOS transistor 330 having the lowest Vgs is a voltage sufficient to turn on to 1.3V.

4 is an operation waveform diagram of a semiconductor memory device according to the present invention having the bit line equalizing circuit shown in FIG. 3. Referring to FIG. 4, in the semiconductor memory device according to the present invention, a sensing operation is performed when the equalizing signal PEQi is at a high level, that is, a power voltage VEXT level applied from the outside, and a low level, that is, a negative voltage value VBB), the precharge operation is performed.

5 is a diagram illustrating a semiconductor memory device in detail according to an embodiment of the present invention.

Referring to FIG. 5, a semiconductor memory device according to an embodiment of the present invention may include bit line equalizer circuits 512 and 522 and bit line isolation circuits 516 between two memory blocks 510 and 520. 526, a sense amplifier circuit 529, a column select circuit 540, and a bit line equalizing signal generator 530 are arranged. The bit line equalizer circuits 512 and 522 may respond to the signals PEQi and PEQj received from the bit line equalizing signal generator 530 before the sensing operation of the memory cell data. The bit lines BL and / BL in the memory block 520 are precharged to the bit line precharge voltage VBL.

When the first bit line isolation circuit 516 senses memory cell data in the first memory block 510, the first bit line isolation circuit 516 senses the bit lines BL and / BL of the first memory block 510. Connect with In this case, the second bit line isolation circuit 526 cuts off the connection between the sense amplifier circuit 529 and the bit lines BL and / BL of the second memory block 520. Conversely, when the second bit line isolation circuit 526 connects the bit lines BL and / BL of the second memory block 520 and the sense amplifier circuit 529, the first bit line isolation circuit 516 may be used. ) Disconnects the bit lines BL and / BL of the first memory block 510 from the sense amplifier circuit 529. The column select circuit 540 transfers memory cell data in the first or second memory blocks 510 and 520 sensed by the sense amplifier circuit 529 to the data input / output lines IO and IOB.

Specifically, the bit line isolation circuits 516 and 526 share the first and second memory blocks 510 and 520 in response to the first and second bit line isolation signals PISOi and PISOj, respectively. Selective connection with amplifier The bit line equalizer circuits 512 and 522 composed of the PMOS transistors 513 to 515 block the bit lines BL and / BL in the first and second memory blocks 510 and 520. Each of the bit line precharge voltages VBL is precharged in response to the bit line equalizing signals PEQi and PEQj.

The equalizing signal generator 530 includes a signal controller 531, a signal holding unit 533, a signal inverting unit 534, a level shifter 537, and a signal driver 535. The signal controller 531, the signal holding unit 533, and the signal inverting unit 534 use the internal voltage VINT generated inside the memory device as the high level power supply and the ground voltage VSS as the low level power supply. do. On the other hand, the level shifter 537 and the signal driver 535 use an external voltage VEXT applied from the outside as a high level power source, and a negative voltage value, that is, a body bias voltage VBB generator, as the low level power source ( The body bias voltage VBB generated at 539 is used.

The signal controller 531 receives an address signal and an equalizing enable signal and outputs a predetermined control signal to the signal holding unit 533. The signal holding unit 533 is provided with an even number of inverters to transfer the received control signal without loss and maintains the control signal. The inverting unit 534 inverts the phase of the output signal of the signal holding unit 533 and outputs it to the level shifter 537. The level shifter 537 applies a low level voltage to a negative voltage value, that is, body bias. It serves to lower the voltage (VBB).

Since the body bias voltage VBB may use the body bias voltage VBB generated by the body bias voltage VBB generator 539 to hold the NMOS bulk bias of the memory array, an additional additional body bias voltage may be used. It does not require a (VBB) generation circuit. The signal driver 535 receives the output signal of the level shifter 537 and generates the first or second PMOS bit line equalizing signals PEQi and PEQj to generate the first or second bit line equalizer circuits 512 and 522. Is applied. The low level of the first or second PMOS bit line equalizing signals PEQi and PEQj has a negative voltage value, that is, the body bias voltage VBB.

In other words, the signal controller 531 receives an address signal and a bit line equalizer enable signal, outputs a control signal to select the first or second memory block, and the signal controller 533 receives a circular control signal. The signal is output to the level shifter 537 through an even number of inverters so as to be transmitted as it is. After setting the high and low discrimination criteria through the level shifter, the signal input to the signal driver 535 is applied as the first and second bit line equalizing signals PEQi and PEQj through the fourth node N4. The phase of the signal at the third node N3 and the phase of the bit line equalizing signal PEQi at the fourth node N4 are opposite to each other.

When the first and second bit line equalizing signals PEQi and PEQj are at a high level of the external voltage VEXT level, the bit line BL and the complementary bit line / BL are bit line precharge voltages VBL. Precharged to level. Thereafter, in order to sense the memory cell MC0 in the first memory block 510, the first bit line equalizing signal PEQi becomes a high level, which is an externally applied voltage VEXT level, so that the PMOS transistor of the bit line equalizer is provided. Turn off fields 513-515. The first bit line isolation signal PISOi becomes the high level of the boosted voltage VPP level, the word line WLn-1 of the memory cell MC0 is enabled to the boosted voltage VPP level, and thus the memory cell. The data MC0 is charged to the sense amplifier circuit 529 while being charged and shared through the bit line BL. The sense amplifier circuit 529 compares the voltage level of the charged share bit line BL with the bit line precharge voltage VBL of the complementary bit line / BL to determine memory cell data.

Next, in order to sense the memory cell MC1 in the second memory block 520, the second bit line equalizing signal PEQj becomes a high level of the externally applied voltage VEXT level, and the word line WL1 is formed. Enabled to the boosted voltage VPP level, the second bit line isolation signal PISOj becomes the high level of the boosted voltage VPP level, and the memory cell MC1 data is charged through the bit line BL. As it is shared, it is transferred to the sense amplifier circuit 529. At this time, the first bit line equalizing signal PEQi becomes a low level of the body bias voltage VBB level, thereby turning on the PMOS transistors 513-515 of the bit line equalizer to turn on the bits in the first memory block 510. The lines BL and / BL are precharged to the bit line precharge voltage VBL.

In the above description and the best embodiments have been described in the specification. Herein, specific terms have been used, but they are used only for the purpose of illustrating the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, the scope of the present invention should be defined by the technical spirit of the appended claims.

As described above, in the semiconductor memory device according to the present invention, a body bias voltage (VBB) in which the bit line equalizer circuit is composed of PMOS transistors and the low level of the bit line equalizing signal controlling the bit line equalizer circuit is a negative voltage value. To drive. Therefore, the equalizing operation can be stably performed even at a lower external applied voltage VEXT.

Claims (11)

First and second memory blocks including a plurality of memory cells for storing data; A sense amplifier which is shared between the first and second memory blocks and writes data to or reads data from the memory cells through pairs of bit lines; A bit line equalizing signal generator for generating a bit line equalizing signal; And And a bit line equalizer circuit for precharging the pair of bit lines to a bit line precharge voltage in response to the bit line equalizing signal, And the bit line equalizer circuit comprises PMOS transistors and the bit line equalizing signal has a negative voltage value. The method of claim 1, wherein the bit line equalizing signal generator, A signal controller configured to receive an address signal and an equalizing enable signal and generate a predetermined control signal; A signal holding unit for holding the control signal in order to receive the control signal and transmit the same without loss; And And a level shifter for shifting the low level of the output signal of the signal holding portion to the negative voltage value. The method of claim 2, wherein the bit line equalizing signal generator, And an inverting portion connected between the signal holding portion and the level shifter and inverting a phase of an output signal of the signal holding portion and outputting the inverted phase to the level shifter. The method of claim 2, wherein the bit line equalizing signal generator, And a signal driver configured to receive the output signal of the level shifter and provide the bit line equalizing signal to the equalizer circuit. The semiconductor memory device according to claim 4, wherein the level shifter and the signal driver use an external voltage applied from the outside as a high level power source and use the negative voltage value as a low level power source. 6. The semiconductor memory device of claim 5, wherein a body bias voltage generated to hold an NMOS bulk bias in the memory blocks is used as the negative voltage value. 2. The semiconductor memory device of claim 1, wherein the bit line equalizer circuit is disabled when the bit line equalizing signal is high and enabled when low. A method of driving a semiconductor memory device having a bit line equalizer circuit for precharging a pair of bit lines in response to a bit line equalizing signal, the method comprising: Generating a control signal by receiving an address signal and an equalizing enable signal; Maintaining a level of the control signal; Adjusting the low level of the maintained control signal to a body bias voltage having a negative voltage value; And And providing the adjusted control signal to the bit line equalizer circuit as the bit line equalizing signal. The method of claim 8, And inverting the phase of the held control signal prior to the adjusting step. The method of claim 8, wherein the maintaining step, A method of driving a semiconductor memory device, characterized by maintaining the level of the control signal by using an even number of inverters. 10. The method of claim 8, wherein the body bias voltage having the negative voltage value is a voltage generated to hold a bulk bias in the memory blocks in the semiconductor memory device.

Images