KR20090055810A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

A semiconductor memory device and a manufacturing method thereof are provided to prevent a dopant from being diffused to interface of a tunnel film and a floating gate. A turner insulating layer(113) is formed on a semiconductor substrate(101), and a floating gate including an undoped polysilicon layer(116) on the turner insulating layer, a diffusion barrier(117), and doped polysilicon film are formed. A dielectric film is formed on the floating gate, and a control gate is formed on the dielectric film. The undoped polysilicon film is formed at lowest part of the floating gate, and the diffusion barrier having oxidation poly-silicon is formed at the lower part of the doped polysilicon film.

Description

Semiconductor memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device and a method of manufacturing the same, which can improve a phenomenon in which a dopant is aggregated at an interface between a tunnel insulating film and a floating gate.

A semiconductor memory device is a memory device that stores data and can be read out when needed. The semiconductor memory device may be largely divided into a random access memory (RAM) and a read only memory (ROM).

RAM is a volatile memory device that loses stored data when power is lost. A ROM is a non-volatile memory device in which stored data does not disappear even when a power supply is cut off.

The nonvolatile memory device may include a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EPEPROM), a flash memory device, and the like. Flash memory devices are generally divided into NAND and NOA types. Among these, NAND flash memory devices are actively developed due to advantages of higher integration and lower manufacturing cost than Noah flash memory devices.

Such NAND flash memory devices can be electrically programmed and erased using Fowler Nordheim (FN) tunneling. To this end, the flash memory device includes a gate pattern in which a tunnel insulating layer, a floating gate, a dielectric pattern, and a control gate are sequentially stacked.

The program state is a state in which charges in the channel region are charged to the floating gate to store information. The charges in the channel region are charged to the floating gate when a high voltage is applied to the control gate.

The erase state is a state in which charges charged in the floating gate exit to the source region or the substrate. The charges charged to the floating gate exit to the source region or the substrate by FN tunneling when a high voltage is applied to the bulk region (eg, P well).

As such, the floating gate, which is a charge charging region in the NAND flash memory device, includes a polysilicon film. The polysilicon film is implanted with a dopant for imparting electrical characteristics to the floating gate.

The grain size of the polysilicon film is formed to 1000 mW to form a floating gate of a predetermined thickness, and may be formed up to 2000 mW. Such grain boundaries vary widely from cell to cell when the floating gate is patterned. In recent years, the area of the floating gate is reduced due to the integration of semiconductor memory devices, and thus the boundary of the lane tends to be irregularly distributed from cell to cell. In addition, the tunnel insulating film in contact with the boundary facing the edges of the grain is formed thicker than the other portion. That is, the iron portion is formed in the tunnel insulating film included in each cell. As a result, when the grain boundary is irregularly formed in each cell, the iron portions of the tunnel insulating film are irregularly formed. That is, when grain boundaries are irregularly formed in each cell, the thickness of the tunnel insulating film is also irregularly formed in each cell.

The uniformity of the tunnel insulation layer is an important factor in determining the threshold voltage. If the tunnel insulation layer is not formed uniformly in each cell, there is a problem in that the distribution characteristic of the threshold voltage is deteriorated. Accordingly, grains of the polysilicon film need to be densely and uniformly formed in each cell. However, even when grains are densely and uniformly formed, grain boundaries are bound to occur in each cell. At the grain boundary, the tunnel insulating film is formed thick, and the dopant is aggregated. Regions in which the dopant is aggregated cause a fast program or deteriorate cycling characteristics. In order to alleviate this phenomenon, reducing the concentration of the dopant included in the polysilicon film is a problem because abnormally programmed cells are generated.

The present invention provides a semiconductor memory device and a method of manufacturing the same, which can improve a phenomenon in which a dopant is aggregated at an interface between grains of a floating gate and a tunnel insulating layer by forming a diffusion barrier in the floating gate.

A semiconductor memory device according to the present invention includes a tunnel insulating film formed on a semiconductor substrate; A floating gate including an undoped polysilicon film, a diffusion barrier film, and a doped polysilicon film formed on the tunnel insulating film; A dielectric film formed on the floating gate; And a control gate formed on the dielectric film.

The undoped polysilicon film and the diffusion barrier film are formed of a plurality of layers and alternately stacked with each other.

An undoped polysilicon film is formed at the bottom of the floating gate.

The diffusion barrier is formed under the doped polysilicon film.

A method of manufacturing a semiconductor memory device according to a first embodiment of the present invention includes the steps of providing a semiconductor substrate having a device isolation film protruding from the upper portion in the device isolation region; Forming a tunnel insulating film on the semiconductor substrate between the device isolation films; Forming a lower layer including an undoped polysilicon layer and a diffusion barrier layer on the tunnel insulating layer; Forming a doped polysilicon film on the lower film; Patterning the undoped polysilicon film, the diffusion barrier film, and the doped polysilicon film; Forming a dielectric film on the semiconductor substrate including the conductive film for the floating gate; And forming a conductive film for the control gate on the dielectric film.

A method of manufacturing a semiconductor memory device according to a second embodiment of the present invention includes forming a tunnel insulating film on a semiconductor substrate; Forming a lower layer including an undoped polysilicon layer and a diffusion barrier layer on the tunnel insulating layer; Etching the diffusion barrier layer, the undoped polysilicon layer, the tunnel insulation layer, and the semiconductor substrate to form a trench; Forming an isolation layer in the region where the trench is formed; Forming a doped polysilicon film on the semiconductor substrate including an isolation layer; Patterning the doped polysilicon film to be separated with the device isolation film therebetween; Forming a dielectric film on the semiconductor substrate including the doped polysilicon film; And forming a conductive film for the control gate on the dielectric film.

The undoped polysilicon film and the diffusion barrier film are formed of a plurality of layers and alternately stacked with each other.

An undoped polysilicon film is formed on the lowermost layer of the lower film.

Forming the underlayer includes depositing undoped polysilicon on the tunnel insulator; And oxidizing the surface of the undoped polysilicon.

The thickness of the undoped polysilicon is 50 kPa to 150 kPa.

Undoped polysilicon includes grains of columnar or polycrystalline structure.

The average diameter of the grains is 50 kPa to 150 kPa.

The undoped polysilicon is formed at a temperature of 480 ° C to 750 ° C.

The undoped polysilicon is formed by LP-CVD at 0.1torr to 500torr pressure.

Gas injected in LP-CVD method is SiH ₄ gas , SiH ₄ gas + H ₂ gas, SiH ₄ gas + NH ₃ gas, and SiH ₄ gas At least one of + N ₂ O gas.

SiH ₄ gas + NH ₃ gas or SiH ₄ gas + N ₂ O gas is injected at a flow rate of 0.1 sccm to 200 sccm.

In the step of oxidizing the surface of the undoped polysilicon, N ₂ O gas is injected at a flow rate of 0.1 sccm to 2000 sccm.

The present invention can prevent diffusion of dopants from the doped polysilicon film into the interface between the tunnel insulating film and the floating gate by forming a diffusion barrier in the floating gate, thereby improving the phenomenon of dopant aggregation at the interface between the tunnel insulating film and the floating gate. can do.

In addition, since the diffusion barrier layer is stacked on the undoped polysilicon on the tunnel insulation layer, the diffusion barrier layer may play a role of controlling the grains constituting the undoped polysilicon layer to no longer grow. Accordingly, the present invention not only makes the surface state of the tunnel insulation film uniform by forming grains small so that grain boundaries in contact with the tunnel insulation film can be uniformly distributed for each cell, but also controls the growth of grain with the diffusion barrier to provide uniformity. Can be maintained.

As a result, the present invention can uniformize the surface state of the tunnel insulating film in contact with the grain boundary for each cell, thereby improving the threshold voltage distribution and increasing the concentration of the dopant included in the doped polysilicon film. The phenomenon in which the dopant is enlarged at the boundary of the polysilicon film can be improved.

In addition, the present invention forms a plurality of layers of the undoped polysilicon film and the diffusion barrier layer and alternately stacks the undoped polysilicon film crystal lattice included in the floating gate to have various orientations. It is more difficult to penetrate into the boundary of the loft polysilicon film, and the stability of the semiconductor memory device is further improved.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

The semiconductor memory device according to the embodiment of the present invention includes a plurality of cells for storing data. Each cell includes a gate pattern in which a tunnel insulating film, a floating gate, a dielectric film, and a control gate are stacked.

1A through 1H are cross-sectional views illustrating a method of forming a gate pattern in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, a hard mask film 106 is formed on a semiconductor substrate 101. The hard mask film 106 may be formed by stacking the pad oxide film 103 and the pad nitride film 105 on the semiconductor substrate 101. Thereafter, the photoresist pattern 107 is formed on the hard mask film 106. Since the hard mask layer 106 determines the height at which the device isolation layer to be formed in the subsequent process is projected onto the semiconductor substrate 101, the thickness of the hard mask layer 106 is determined in consideration of this. The photoresist pattern 107 exposes the hard mask film 106 of the portion where the trench is to be formed.

Referring to FIG. 1B, the hard mask layer 106 exposed by the photoresist pattern 107 is etched to form the trench hard mask pattern 106a. The semiconductor substrate 101 exposed by the trench hard mask pattern 106a is etched to form the trench 109 in the device isolation region. Thereafter, the photoresist pattern 107 is removed, and the insulating material layer 111 is formed on the semiconductor substrate 101 to completely fill the trench 109. Thereafter, the insulating material layer 111 on the trench hard mask pattern 106a is subjected to chemical mechanical polishing (hereinafter, referred to as "CMP") process so that the insulating material layer 111 remains only in the device isolation region. Remove In this case, the insulating material layer 111 may be formed of high density plasma oxide (High Density Plasma Oxide).

Referring to FIG. 1C, the trench hard mask pattern 106a is removed and the active region of the semiconductor substrate 101 is exposed. As a result, the device isolation layer 111 protruding to the upper portion of the semiconductor substrate 101 is exposed. Thereafter, the protrusion 111a of the device isolation layer is further etched. Thereby, the space | interval between the element isolation film protrusion 111a becomes wider.

Referring to FIG. 1D, a tunnel insulating layer 113 is formed on the semiconductor substrate 101 between the device isolation layers 111a.

Referring to FIG. 1E, after the tunnel insulation layer 113 is formed, an undoped polysilicon layer 116 and a diffusion barrier layer 117 are stacked on the surfaces of the tunnel insulation layer 113 and the device isolation layer 111a. The lower layer 115 is formed. The undoped polysilicon layer 116 and the diffusion barrier 117 may be formed of a plurality of layers that are alternately stacked with each other. At this time, it is preferable that the undoped polysilicon film 116 is formed at the lowermost portion of the lower film 115 (that is, at the portion in contact with the tunnel insulating film 113). The diffusion barrier 117 is preferably formed to prevent diffusion of the dopant but to facilitate tunneling of electrons. The lower film 115 having such a structure is formed by forming the undoped polysilicon film 116 and then oxidizing the surface of the undoped polysilicon film 116. That is, the diffusion prevention film 117 is formed by oxidizing the surface of the undoped polysilicon film 116.

In more detail, the undoped polysilicon film 116 is formed to have a grain size of less than 150 microns. To this end, the undoped polysilicon film 116 is deposited at a temperature of 480 ℃ to 750 ℃. In addition, the undoped polysilicon layer 116 may be deposited by LP-CVD using SiH ₄ as a source gas. In this case, at least one of H ₂ gas, NH ₃ gas, and N ₂ O gas may be further injected into the gas to be injected, in addition to SiH ₄ gas, which is a source gas. SiH ₄ Gas and NH ₃ gas are injected together or SiH ₄ When the gas and the N ₂ O gas are injected together, the flow rate of the deposition gas is preferably 0.1 sccm to 200 sccm. In the undoped polysilicon deposition, the pressure condition is preferably 0.1torr to 500torr.

Under such conditions, the grains of the undoped polysilicon film 116 may grow to an average of 150 GPa or less. Here, the minimum size of the grains may vary depending on each condition, but is generally 50 kPa or more. The shape of the grain is formed into a columnar structure or a polycrystal structure such as a sphere. Grain has the property to grow isotropically, if the height is formed 50 ~ 150Å, the width is also formed 50 ~ 150Å.

The deposition thickness of the undoped polysilicon film 116 is 50 kV equal to the grain size to equalize the surface roughness of the undoped polysilicon film 116 and to limit the charge storage region of the floating gate to the bottom of the floating gate. To 150 kPa.

As such, when the grains of the undoped polysilicon film 116 in contact with the tunnel insulating film 113 are densely formed to be 150 kV or less, the grain boundaries included in each cell are equalized even when the floating gate is patterned in a subsequent process. do.

The diffusion barrier 117 deposits the undoped polysilicon layer 116 and injects N ₂ O gas at a flow rate of 0.1 sccm to 2000 sccm at a high temperature of 700 ° C. or higher to oxidize the surface of the undoped polysilicon layer 116. It is formed by. The diffusion barrier 117 prevents the dopant included in the doped polysilicon layer formed in a subsequent process from being diffused into the tunnel insulating layer 113. In addition, the diffusion barrier 117 prevents the grain of the undoped polysilicon layer 116 from contacting the tunnel insulation layer 113 from growing to 150 kV or more. Accordingly, the diffusion barrier 117 not only prevents the dopant from agglomerating in the tunnel insulation layer 113, but also prevents the grains of the undoped polysilicon layer 116 contacting the tunnel insulation layer 113 from growing dense. Keep shape.

The undoped polysilicon film 116 and the diffusion barrier 117 may be formed of a plurality of layers alternately stacked with each other by repeating the above-described deposition and oxidation processes. If the undoped polysilicon film 116 is formed of a plurality of layers, the crystal lattice direction of each layer may vary, so that the dopant of the undoped polysilicon film formed in a subsequent process is the tunnel insulating film 113 and the undoped polysilicon film. It is more difficult to penetrate to the boundary of 116, which further improves the stability of the semiconductor memory device.

Referring to FIG. 1F, a doped polysilicon film 119 is formed on the lower film 115. The doped polysilicon film 119 is formed to a thickness of 500 kV to 2000 kV in consideration of the coupling ratio between the floating gate and the control gate to be formed in a subsequent process. The doped polysilicon film 119 is preferably deposited by LP-CVD at a temperature of 480 ° C to 620 ° C and a low pressure of 0.1torr to 3torr. SiH ₄ together with PH ₃ gas during deposition of the doped polysilicon layer 119 Alternatively, any one of Si ₂ H ₆ is implanted to form a polysilicon film implanted with phosphorus (P). The concentration of phosphorus (P) contained in the deposition gas is preferably 1.0E19 to 1.0E21 (atoms / cc).

Referring to FIG. 1G, the lower layer 115 and the doped polysilicon layer 119 are removed to expose the upper portion of the device isolation layer 111 by a CMP process to form a conductive film for a floating gate. Thereafter, some device isolation layers 111 are removed to secure the charge capacity of the floating gate formed in a subsequent process.

Referring to FIG. 1H, a dielectric film and a control gate conductive film are stacked on the semiconductor substrate 101 on which the device isolation layer 111 and the floating gate conductive film are formed. Thereafter, the control gate 125, the dielectric layer 123, and the floating gate 121 are patterned by an etching process using a hard mask pattern. Accordingly, the lower layer 115 of the floating gate 121 is formed in a “凹” shape on the tunnel insulating film 113, and the doped polysilicon film 119 is filled in the internal space provided in the “凹” shape. It is formed to. The conductive film for the control gate may be formed of at least one of doped polysilicon, tungsten silicide (WSi), and tungsten (W).

As described above, the floating gate 121 according to the first embodiment of the present invention includes an undoped polysilicon layer 116, a diffusion barrier 117, and a doped polysilicon layer 119. The diffusion barrier 117 may prevent the dopant included in the doped polysilicon layer 119 from diffusing into the tunnel insulating layer 113. In addition, the diffusion barrier 117 may prevent the grains of the undoped polysilicon layer 116 in contact with the tunnel insulation layer 113 from growing to a size of 150 kPa or more. Accordingly, the present invention can control the grain of the undoped polysilicon layer 116 so that it no longer grows, thereby maintaining the uniformity of the surface of the tunnel insulating layer 113 in contact with the grain for each cell.

2A through 2F are cross-sectional views illustrating a method of forming a gate pattern according to a second exemplary embodiment of the present invention.

Referring to FIG. 2A, a tunnel insulating film 213, a lower film 215, and a hard mask film 205 are deposited on the semiconductor substrate 201. The lower layer 215 is formed by stacking the undoped polysilicon layer 216 and the diffusion barrier layer 217 as described above with reference to FIG. 1E. The undoped polysilicon film 216 according to the second embodiment of the present invention is formed in the same manner as described above with reference to FIG.

As such, when the grains of the undoped polysilicon film 216 in contact with the tunnel insulating film 213 are densely formed to be 150 kV or less, the grain boundaries included in each cell are uniformed even when the floating gate is patterned in a subsequent process. .

The diffusion barrier 217 not only prevents the dopant from agglomerating in the tunnel insulating layer 213, but also maintains a dense shape of grains of the undoped polysilicon layer 216.

Referring to FIG. 2B, after the hard mask layer 205 is patterned using the photoresist pattern, the trench hard mask pattern 205a is formed. The trench hard mask pattern 205a exposes the lower layer 215 of the portion where the trench is to be formed. The exposed lower layer 215, the tunnel insulating layer 213 underneath, and the semiconductor substrate 201 are etched to form trenches 209 in the device isolation region. Next, after the insulating material layer is formed to completely fill the trench 209, the insulating material layer on the trench hard mask pattern 205a is removed by a CMP process so that the insulating material layer remains only in the device isolation region. As a result, an isolation layer 211 is formed in the trench 209. In this case, the insulating material layer may be formed of high density plasma oxide (High Density Plasma Oxide).

Referring to FIG. 2C, the isolation layer 211 is formed to protrude beyond the surface of the lower layer 215 by removing the trench hard mask pattern 205a.

Referring to FIG. 2D, a doped polysilicon film 219 is deposited on surfaces of the lower film 215 and the device isolation film 211.

The doped polysilicon film 219 is formed in the same manner as described above in Fig. 1F.

Referring to FIG. 2E, after forming the doped polysilicon layer 219, the doped polysilicon layer 219 is patterned by an etching process using a hard mask pattern. Accordingly, the doped polysilicon film 219 is separated with the device isolation film 211 interposed therebetween.

Referring to FIG. 2F, a dielectric film and a conductive film for a control gate are stacked on the surfaces of the device isolation film 211 and the doped polysilicon film 219. Thereafter, the control gate 225, the dielectric layer 223, and the floating gate 221 are patterned by an etching process using a hard mask pattern. The conductive film for the control gate may be formed of at least one of doped polysilicon, tungsten silicide (WSi), and tungsten (W).

As described above, the floating gate 221 according to the second embodiment of the present invention may also have the undoped polysilicon film 216, the diffusion barrier film 217, and the doped polysilicon film 219 as in the first embodiment. It includes a laminated structure. The diffusion barrier 217 may prevent the dopant included in the doped polysilicon layer 219 from being diffused into the tunnel insulating layer 213. In addition, the diffusion barrier 217 may prevent the grains of the undoped polysilicon layer 216 in contact with the tunnel insulation layer 213 from growing to a size of 150 kPa or more. Accordingly, according to the present invention, the grains of the undoped polysilicon layer 216 can be controlled to no longer grow, thereby maintaining the surface uniformity of the tunnel insulating layer 213 in contact with the grains in each cell.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1H are cross-sectional views illustrating a method of forming a gate pattern of a semiconductor memory device according to a first embodiment of the present invention.

2A through 2F are cross-sectional views illustrating a method of forming a gate pattern of a semiconductor memory device according to a second embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

101, 201: semiconductor substrate 111, 121: device isolation film

113, 213: tunnel insulating film 121, 221: floating gate

115, 215: lower film 116, 117: undoped polysilicon film

117 and 217: diffusion barrier 119 and 219: doped polysilicon film

123 and 223 dielectric films 125 and 225 control gates

Claims (23)

A tunnel insulating film formed on the semiconductor substrate; A floating gate including an undoped polysilicon film, a diffusion barrier film, and a doped polysilicon film formed on the tunnel insulating film; A dielectric film formed on the floating gate; And And a control gate formed on the dielectric layer. The method of claim 1, The undoped polysilicon layer and the diffusion barrier layer are formed of a plurality of layers and alternately stacked with each other. The method of claim 1, And the undoped polysilicon layer formed on a lowermost portion of the floating gate. The method of claim 1, The diffusion barrier is formed under the doped polysilicon layer. The method of claim 1, The diffusion barrier layer is a semiconductor memory device containing polysilicon oxide. The method of claim 1, The undoped polysilicon film and the diffusion barrier are formed in a "凹" shape, The doped polysilicon layer is filled in the internal space provided in the "凹" form. The method of claim 1, A device isolation layer formed to protrude from the semiconductor substrate; The undoped polysilicon layer and the diffusion barrier are formed between the device isolation layer. The method of claim 1, The undoped polysilicon film has a thickness of 50 kV to 150 kV. The method of claim 1, The undoped polysilicon film includes grains of columnar or polycrystalline structure. The method of claim 9, And a mean diameter of the grains of 50 kV to 150 kV. Providing a semiconductor substrate having a device isolation film protruding therefrom in the device isolation region; Forming a tunnel insulating film on the semiconductor substrate between the device isolation layers; Forming a lower layer including an undoped polysilicon layer and a diffusion barrier layer on the tunnel insulating layer; Forming a doped polysilicon film on the lower film; Patterning the undoped polysilicon film, the diffusion barrier film, and the doped polysilicon film; Forming a dielectric film on the semiconductor substrate including the floating gate conductive film; And Forming a control gate conductive film on the dielectric film. Forming a tunnel insulating film on the semiconductor substrate; Forming a lower layer including an undoped polysilicon layer and a diffusion barrier layer on the tunnel insulating layer; Etching the diffusion barrier layer, the undoped polysilicon layer, the tunnel insulation layer, and the semiconductor substrate to form a trench; Forming an isolation layer in the region where the trench is formed; Forming a doped polysilicon film on the semiconductor substrate including the device isolation film; Patterning the doped polysilicon layer so as to be separated with the device isolation layer therebetween; Forming a dielectric film on the semiconductor substrate including the doped polysilicon film; And Forming a control gate conductive film on the dielectric film. The method according to claim 11 or 12, The undoped polysilicon film and the diffusion barrier layer are formed of a plurality of layers and stacked alternately with each other. The method according to claim 11 or 12, The undoped polysilicon film is formed on the lowermost layer of the lower film. The method according to claim 11 or 12, Forming the lower layer Depositing undoped poly silicon on the tunnel insulating film; And And oxidizing a surface of the undoped polysilicon. The method of claim 15, The undoped polysilicon has a thickness of 50 kV to 150 kV. The method of claim 15, And the undoped polysilicon comprises a columnar structure or grains of polycrystalline structure. The method of claim 17, A method of manufacturing a semiconductor memory device, wherein the grain has an average diameter of 50 kV to 150 kV. The method of claim 18, The undoped polysilicon is a method of manufacturing a semiconductor memory device is formed at a temperature of 480 ℃ to 750 ℃. The method of claim 18, The undoped polysilicon is a method of manufacturing a semiconductor memory device formed by LP-CVD at a pressure of 0.1torr to 500torr. The method of claim 20, The gas injected in the LP-CVD method is SiH ₄ gas , SiH ₄ gas + H ₂ gas, SiH ₄ gas + NH ₃ gas, and SiH ₄ gas + A method for manufacturing a semiconductor memory device comprising at least one of N ₂ O gas. The method of claim 21, The SiH ₄ gas + NH ₃ gas or SiH ₄ gas + N ₂ O gas is injected at a flow rate of 0.1sccm to 200sccm. The method of claim 15, In the step of oxidizing the surface of the undoped polysilicon N ₂ O gas is injected at a flow rate of 0.1sccm to 2000sccm.

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