KR20090054648A - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

An array panel for a liquid crystal display and a manufacturing method thereof are provided to equip a thin film transistor having a short channel domain of a size smaller than 4mum which is a limit of patterning, thereby improving the property of the thin film transistor and lowering a driving voltage of the transistor to reduce final power consumption. An array panel(101) comprises as follows. An insulating pattern(112) is formed on the panel with an upper side thereof having a first width. A drain electrode is contacted with one side and the other side as exposing an upper side of the insulating pattern on the panel, and is formed as being separated from each other. An ohmic contact layer is separated at an interval of the insulating pattern, as exposing the upper side of the insulating pattern to an upper part of source and drain electrodes. An active layer is formed in an upper part of the ohmic contact layer and the insulating pattern separated from each other. A gate insulating film is formed while covering an active layer. The gate electrode is formed integrally while overlapping with the insulating pattern, and the source and drain electrodes to an upper part of the gate insulating film.

Description

Array substrate for liquid crystal display device and method of fabricating the same}

The present invention relates to a liquid crystal display device, and more particularly, to a structure of a thin film transistor formed in each pixel region of an array substrate for a liquid crystal display device and a method of manufacturing the same.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the best resolution and video performance. I am getting it.

Referring to FIG. 1, which is an exploded perspective view of a general liquid crystal display device, a structure of a liquid crystal display device will be described. As illustrated, the array substrate 10 and the color filter substrate 20 are disposed with the liquid crystal layer 30 therebetween. In this case, the bottom substrate array substrate 10 is vertically intersected with the upper surface of the transparent substrate 12 to define a plurality of pixel regions P and a plurality of gate wirings 14 and data wirings 16. A thin film transistor Tr is provided at an intersection point of the two wires 14 and 16 and is connected one-to-one with the pixel electrode 18 provided in each pixel region P.

In addition, the upper color filter substrate 20 facing the array substrate may cover a non-display area such as the gate line 14, the data line 16, and the thin film transistor Tr on the rear surface of the transparent substrate 22. Grid-like black matrix 25 is formed so as to border each pixel region P, and the red, green, and blue color filter layers 26 are sequentially arranged to correspond to each pixel region P in the grid. ) Is formed, and a transparent common electrode 28 is provided over the entire surface of the color filter layer 26 including the black matrix 25 and the red, green, and blue color filter patterns 26a, 26b, and 26c. .

Although not shown in the drawings, these two substrates 10 and 20 are sealed with a sealant or the like along the edges to prevent leakage of the liquid crystal layer 30 interposed therebetween. In the boundary portion of each substrate (10, 20) and the liquid crystal layer 30 is interposed upper and lower alignment layer that provides reliability in the molecular alignment direction of the liquid crystal, and at least one outer surface of each substrate (10, 20) A polarizing plate is provided.

In addition, a back-light is provided on the outer surface of the array substrate to supply light, and the on / off signal of the thin film transistor Tr is sequentially scanned to the gate wiring 14. When the image signal of the data wiring 16 is transmitted to the pixel electrode 18 of the pixel region P applied and selected, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the light transmittance is changed. Branch images can be displayed.

In the liquid crystal display having the above structure, the most important component is a thin film transistor which is formed for each pixel region and is connected to the gate and data lines and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode. Can be.

The cross-sectional structure of the thin film transistor, which serves as such a switching element, will be described with reference to FIG.

FIG. 2 is a cross-sectional view of one pixel area including a partial switching area in which a thin film transistor is formed in an array substrate of a conventional liquid crystal display.

The gate electrode 60 is formed on the transparent insulating substrate 59, and the gate insulating layer 68 is formed on the entire surface of the gate electrode 60. The semiconductor layer 70 includes an active layer 70a made of pure amorphous silicon on the gate insulating layer, and an ohmic contact layer 70b made of amorphous silicon containing impurities in a form spaced apart from each other. ) Is formed.

In addition, the ohmic contact layer 70b formed to expose the active layer 70a below and spaced apart from each other is in contact with the ohmic contact layer 70b and is spaced apart from each other to correspond to the gate electrode 60. The source electrode 76 and the drain electrode 78 are formed while exposing the layer 70a.

The thin film transistor Tr includes the gate electrode 60, the gate insulating film 68, and the source and drain electrodes 76 and 78 spaced apart from each other, and are sequentially stacked on the substrate 59. To achieve.

A passivation layer 86 having a drain contact hole 80 exposing a part of the drain electrode 78 is formed on the front surface of the thin film transistor Tr having such a structure, and each passivation layer 86 is formed on the passivation layer 86. A pixel electrode 88 is formed in each pixel region P to contact the drain electrode 78 through the drain contact hole 80, and the gate electrode 60 is formed on the same layer on which the gate electrode 60 is formed. ) And a data line (not shown) connected to the source electrode 76 is further formed on the same layer on which the source and drain electrodes 76 and 78 are formed. )

On the other hand, in the array substrate 59 having such a configuration, the thin film transistor Tr selectively controls the signal voltage when the signal voltage is applied to the pixel electrode 88 of each pixel region P. In this case, the thin film transistor Tr The image quality is greatly affected by the characteristic of (Tr).

The characteristics of the thin film transistor Tr are determined by the implementation of the semiconductor layer 70 having excellent channel characteristics. In the case of the thin film transistor Tr having a semiconductor material of amorphous silicon as the active layer 70a, the channel length That is, the smaller the spaced distance d between the source and drain electrodes 76 and 78, that is, the short channel region is implemented, the better the thin film transistor (Tr) characteristics. Since the thin film transistor having such a short channel can be driven at a low voltage due to a low driving voltage, it has an excellent advantage in terms of power consumption.

However, due to the manufacturing process characteristics of the array substrate for a liquid crystal display device, the pattern or pattern spacing between patterns to be formed using the exposure process should be at least 4 μm or more, and the pattern or pattern having a size smaller than that should be formed. This is a situation in which the error range is large and a stable manufacturing process cannot be performed due to the nature of the manufacturing process to be repeatedly implemented.

Accordingly, the thin film transistor Tr implemented on the conventional array substrate 59 for a liquid crystal display device has a spacing d of the source and drain electrodes 76 and 78 more than 4 μm, more precisely, for its process stability. It forms so that it may become about 5 micrometers-6 micrometers.

This is because the length of the channel does not maximize the characteristics of the thin film transistor, and due to the limitation of patterning, the thin film transistor is inevitably formed by the opening ratio and luminance due to the large area occupied by the thin film transistor in the pixel region. It is causing the problem of degradation.

In order to solve the above problems, the present invention provides a thin film transistor having a short channel region having a size smaller than 4 μm, which is the limit of patterning, and an array substrate for a liquid crystal display device having the same. It is an object to reduce the final power consumption by lowering the transistor driving voltage.

Further, it is another object to reduce the size of the channel region to reduce the size of the thin film transistor, thereby improving the aperture ratio and luminance characteristics of the liquid crystal display device.

An array substrate according to the present invention comprises: an insulating pattern formed on a substrate with an upper surface thereof having a first width; Source and drain electrodes formed on the substrate to be in contact with one side and the other side and spaced apart from each other while exposing an upper surface of the insulating pattern; An ohmic contact layer formed on the source and drain electrodes to expose an upper surface of the insulating pattern and spaced apart from each other with the insulating pattern interposed therebetween; An ohmic contact layer spaced apart from each other and an active layer formed on the insulating pattern; A gate insulating film covering the active layer; A gate electrode integrally formed on the gate insulating layer and overlapping the insulating pattern and the source and drain electrodes; A protective layer having a drain contact hole for covering the gate electrode and exposing the drain electrode; And a pixel electrode formed on the passivation layer and in contact with the drain electrode through the drain contact hole.

The first width is characterized in that 1㎛ to 3㎛.

A data line connected to the source electrode on the substrate and extending in one direction and a data pad electrode connected to one end of the data line; A gate line electrode connected to the gate electrode over the gate insulating layer and defining a pixel region crossing the data line, and a gate pad electrode connected to one end of the gate line, wherein the pixel electrode includes a gate in front of the pixel region. It is characterized by overlapping wiring.

In addition, the insulating pattern is characterized in that the cross-sectional structure of the tapered shape.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including: forming an insulating pattern having a first width at an upper surface thereof on a substrate; A source and drain electrode contacting one side surface and the other side surface of the insulating pattern and exposing the top surface of the insulating pattern and spaced apart from each other, and an ohmic contact spaced apart from each other by exposing the top surface of the insulating pattern to the source and drain electrodes. Forming a layer, an active layer integrated over the insulating pattern and the ohmic contact layer; Forming a gate insulating film over the active layer; Forming a gate electrode on the gate insulating layer, the gate electrode overlapping the insulating pattern and both ends of the gate insulating layer respectively overlapping the source and drain electrodes; Forming a protective layer having a drain contact hole exposing the drain electrode over the gate electrode; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer.

The forming of the insulating pattern may include forming an insulating layer on the entire surface of the substrate; Forming a first photoresist pattern having a second width greater than the first width over the insulating layer; Subjecting the first photoresist pattern having the second width to a third width smaller than a second width and larger than the first width; Dry etching the insulating layer exposed to the outside of the first photoresist pattern having the third width to form the insulating pattern to have an undercut shape under the first photoresist pattern, wherein The insulating pattern is characterized in that the side surface is formed with an angle of 30 degrees to 60 degrees to form a tapered shape of the cross section.

Forming source and drain electrodes spaced apart from each other on both sides, including both sides of the insulating pattern, the ohmic contact layer spaced apart from each other, and the active layer formed on the insulating pattern and the ohmic contact layer, Forming a first metal layer on the entire surface of the substrate over the first photoresist pattern on the insulating pattern; Forming an impurity amorphous silicon layer over the first metal layer; Exposing an upper surface of the insulating pattern by removing the first photoresist pattern, the first metal layer and the impurity amorphous silicon layer formed thereon; Forming a pure amorphous silicon layer over the non-removed impurity amorphous silicon layer including an upper portion of the exposed insulating pattern; Successively patterning the pure amorphous silicon layer, an impurity amorphous silicon layer below it, and the first metal layer.

The first width is characterized in that 1㎛ to 3㎛.

The forming of the source and drain electrodes may include forming a data line connected to the source electrode and extending in one direction on the substrate, and a data pad electrode connected to one end of the data line.

The forming of the gate electrode may include forming a gate wiring connected to the gate electrode over the gate insulating layer and defining a pixel area crossing the data wiring, and a gate pad electrode connected to one end of the gate wiring. The forming of the protective layer having the drain contact hole may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode.

The forming of the pixel electrode may include a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole, and a data auxiliary pad electrode contacting the data pad electrode through the data pad contact hole. Forming a step.

The present invention provides a method for manufacturing an array substrate for a liquid crystal display device having a size of about 1 μm to 3 μm in which a length of a channel region formed in an active layer in a thin film transistor, which is a switching element, is smaller than 4 μm required for stable patterning process characteristics. It is effective to provide.

By enabling the short channel configuration having a channel length of 4 μm or less, the characteristics of the thin film transistor can be improved, and the driving voltage of the thin film transistor can be reduced, thereby reducing power consumption.

In addition, since the size of the thin film transistor itself can be reduced by the short channel configuration, the area occupied by the thin film transistor in the pixel area becomes small, thereby improving the aperture ratio and luminance characteristics of the liquid crystal display.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>

3A to 3I are cross-sectional views illustrating manufacturing steps of one pixel region P including a thin film transistor and a storage capacitor of an array substrate for a liquid crystal display according to a first embodiment of the present invention. Process sectional view of the gate pad part GPA of the array substrate for a liquid crystal display device according to the first embodiment of the present invention, Figures 5a to 5i is an array substrate for a liquid crystal display device according to a first embodiment of the present invention Step-by-step process cross-sectional view of the data pad portion (DPA) of the. For convenience of description, an area where the thin film transistor is formed is a switching area TrA, an area where a storage capacitor is formed is a storage area StgA, and an area where the gate and data pad electrodes are formed is respectively a gate pad part GPA. And a data pad unit DPA.

First, as shown in FIGS. 3A, 4A, and 5A, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the transparent insulating substrate 101 to form the insulating layer 110. Form. At this time, the insulating layer 110 is a material layer for forming a partition, which is a characteristic part of the present invention, it is preferable to form the thickness so as to be about 1㎛ to 2㎛. Subsequently, a photoresist, which is a photosensitive material, is coated on the insulating layer 110 to form a first photoresist layer (not shown), which is exposed and developed to correspond to a central portion of the switching region TrA. The first photoresist pattern 181 having a size of about 4 μm to 6 μm may be formed through the exposure process and the developing process.

Next, as shown in FIGS. 3B, 4B, and 5B, an isotropic ashing of the first photoresist pattern 181 having a width d1 of about 4 μm to 6 μm for patterning stability is formed. By appropriately reducing the side and thickness of the first photoresist pattern 181 to form a second photoresist pattern 182 having a width d2 of about 3 μm to 4 μm. Because of the isotropic ashing characteristic, the first photoresist pattern 181 is reduced in thickness by approximately the same ratio as the upper surface and the side surface thereof, so that both sides of the first photoresist pattern 181 are adjusted to the ashing time appropriately, respectively, about 0.5 μm to 1 μm. When the ashing is stopped while the thickness is reduced, the second photoresist pattern 182 having a width d2 of about 3 μm to 4 μm is described.

3C, 4C, and 5C, the insulating layer (FIGS. 3B and 4B) using the second photoresist pattern 182 having a width d2 of about 3 μm to 4 μm as an etching mask. And dry etching to remove 110 of 5b. At this time, the dry etching is a side surface of the insulating pattern 112 which is left under the second photoresist pattern 182 by adjusting the flow rate, the degree of vacuum, etc. of the reaction gas in the chamber to perform the substrate 101 It can be formed to have a taper shape having an inclination in the range of 30 degrees to 60 degrees with respect to the surface, by using this process characteristic the width of the insulating pattern 112 of the 3㎛ to 4㎛ (d2) By appropriately performing the dry etching to have an undercut shape under the second photoresist pattern 182 having a width d3 of the upper surface of 1 μm to 2 μm, the width of the lower surface ( It is formed so that it may become a taper shape which becomes 2 micrometers-about 3 micrometers.

Next, as shown in FIGS. 3D, 4D, and 5D, the second photoresist pattern 182 remains on the insulating pad 112 turn having a width d3 of the upper surface of 1 μm to 2 μm. In the present state, a metal material such as molybdenum (Mo) or molybdenum alloy (MoTi) is deposited on the entire surface of the substrate 101 on the second photoresist pattern 182 to form the first metal layer 120, and continuously Amorphous silicon is deposited to form an impurity amorphous silicon layer 127. In this case, the first metal layer 120 and the impurity amorphous silicon layer 127 may be formed to the side surface of the insulating pattern 112. In this case, the first metal layer 120 and the impurity amorphous silicon layer 127 are not formed on a part of the bottom surface of the second photoresist pattern 182 exposed to the outside of the insulating pattern 112 by the undercut shape. The portion formed on the second photoresist pattern 182 and the first metal layer 120 and the impurity amorphous silicon layer 127 formed on the substrate 101 are separated from each other.

3E, 4E, and 5E, the substrate 101, on which the first metal layer 120 and the impurity amorphous silicon layer 127 is formed, is exposed to a stripping solution to expose the second photoresist pattern (FIG. 182 of 3d is removed to the substrate 101 along with the first metal layer 120 and the impurity amorphous silicon layer 127 thereon. In this case, the strip liquid penetrates into the bottom surface of the second photoresist pattern 182 of FIG. 3D, so that the strip liquid is separated from the insulating pattern 182 more precisely. 182 is removed to expose the top surface of the insulating pattern 112 having a width d3 of 1 μm to 2 μm.

3F, 4F, and 5F, pure amorphous silicon is deposited on the substrate 101 on which the upper surface of the insulating pattern 112 is exposed to the outside of the impurity amorphous silicon layer 127. Forming an amorphous silicon layer 130, and subsequently applying a photoresist on the pure amorphous silicon layer 130 to form a second photoresist layer (not shown) and patterning it by the switch region (TrA) and data The third photoresist pattern 185 is formed to correspond to the pad part DPA, respectively. At this time, all of the third photoresist patterns 185 formed have a size of 5 μm or more in which the width thereof is stable. In this case, the third photoresist pattern 185 may be formed in the switching region TrA to correspond to the entire switching region TrA.

Next, as shown in FIGS. 3G, 4G, and 5G, the pure amorphous silicon layer 130 (FIGS. 3F and 5F) exposed to the outside of the third photoresist pattern (185 of FIGS. 3F and 5F) and its The upper rotor in the switching region TrA by removing the impurity amorphous silicon layer (127 in FIGS. 3F and 5F) and the first metal layer (120 in FIGS. 3F and 5F) located below by dry etching. An active layer 131 of pure amorphous silicon below, an ohmic contact layer 128 of impurity amorphous silicon spaced apart from one side and the other side of the insulating pattern 112, and the respective ohmic contact layers 128 Source and drain electrodes 122 and 124 are formed below. In this case, a distance between the source and drain electrodes 122 and 124 for determining the length of the channel in the active layer 131 is about 1 μm to 3 μm, the width d3 of the upper surface of the insulating pattern 112. It can be seen that significantly reduced compared to the conventional channel length (d of FIG. 2).

Meanwhile, also in the data pad part DPA, portions covered by the third photoresist pattern 185 of FIG. 5F include the pure amorphous silicon layer 130 (FIGS. 3F and 5F) and the impurity amorphous silicon layer (FIGS. 3F and 3F). 5F and 127 of FIG. 5F and the first metal layer 120 (FIGS. 3F and 5F) are not removed, and these unremoved portions are formed on the data pad electrode 126 and the upper portion of the first pattern of impurity amorphous silicon. 129 and a second pattern 132 of pure amorphous silicon form a semiconductor pattern 135.

Although not shown in the drawing, a data line (not shown) connected to the source electrode 122 and extending in one direction is formed on the substrate 101. In this case, a semiconductor pattern formed in the same manner as the first pattern 129 and the second pattern 132 of the data pad part DPA is formed on the data line (not shown).

Next, a gate insulating layer 140 is formed by depositing an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the entire surface of the substrate 101 on the active layer 131 and the semiconductor pattern 135. A second metal layer having a single layer or a double layer structure is deposited on the gate insulating layer 140 by depositing one or two materials selected from a metal material, particularly aluminum, aluminum alloy, copper, copper alloy, and molybdenum having low resistance properties. 150). In this case, the figure shows a single layer. In addition, a gate wiring line defining a pixel region P by crossing the center portion of the switching region TrA, the storage region StgA, and the data line (not shown) on the second metal layer 150. A fourth photoresist pattern 187 is formed to correspond to a portion where a portion of the gate pad electrode GPA is to be formed and a portion where a gate pad electrode (not shown) of the gate pad portion GPA is to be formed.

Next, as shown in FIGS. 3H, 4H, and 5H, the second metal layer (150 of FIGS. 3G, 4G, and 5G) exposed to the outside of the fourth photoresist pattern (187 of FIGS. 3G and 4G) is removed. As a result, the switching region TrA has a wider width than the insulating pattern 112 on the gate insulating layer 140, and overlaps the source and drain electrodes 122 and 124, respectively. The gate electrode 155 is formed, and at the same time, a gate wiring 152 connected to the gate electrode 155 and intersecting with the data wiring (not shown) is formed. At this time, the gate pad electrode 157 is formed in the gate pad part GPA. In this case, the gate electrode 155, the gate wiring 152, and the gate pad electrode 157 are all illustrated as having a single layer structure. However, when the second metal layer is formed as a double layer, the gate electrode 155, the gate line 152, and the gate pad electrode 157 may be formed to have a double layer structure. .

Thereafter, an inorganic insulating material such as silicon oxide (SiO 2) or silicon nitride (SiN x) is deposited on the entire surface of the substrate 101 on which the gate electrode 155, the gate wiring 152, and the gate pad electrode 157 are formed. Forming a protective layer 160, and successively patterning the protective layer 160, the lower gate insulating layer 140, the active layer 131, and the ohmic contact layer 128. Forming a drain contact hole 162 exposing the drain electrode 124, and simultaneously forming a data pad contact hole 166 exposing the data pad electrode 126 in the data pad portion DPA. do. In this case, in the gate pad part GPA, the protective layer 160 is removed to form a gate pad contact hole 164 exposing the gate pad electrode 157.

Next, as shown in FIGS. 3I, 4I, and 5I, an example of a transparent conductive material is formed on the front surface of the protective layer 160 including the drain contact hole 162 and the gate and data pad contact holes 164 and 166. For example, an indium tin oxide (ITO) or an indium zinc oxide (IZO) may be deposited to form a transparent conductive material layer (not shown), and patterned to form the drain contact hole 162 in the switching region TrA. The pixel electrode 170 is formed in contact with the drain electrode 124 and overlaps the gate line 142 at the front end to form a storage capacitor StgC. In the gate pad part GPA, the gate electrode is formed. A gate auxiliary pad electrode 172 in contact with the gate pad electrode 157 through a pad contact hole 164, and the data pad through the data pad contact hole 166 in the data pad part DPA. Day in contact with electrode 126 By forming the auxiliary pad electrode 174 may complete the array substrate for a liquid crystal display device 101 according to the first embodiment of the present invention.

The array substrate for a liquid crystal display device manufactured through the above-described process stably forms the source and drain electrodes having a spaced interval of 1 μm to 3 μm to describe the length of the channel region formed in the active layer between these electrodes. Since it can be configured to have a width of about 1㎛ to 3㎛, it is possible to improve the characteristics of the thin film transistor by forming a short channel, thin film transistor having such a short channel can lower the driving voltage, consumption It has the effect of reducing power.

Second Embodiment

6A through 6D are cross-sectional views illustrating manufacturing processes of one pixel region P including a thin film transistor and a storage capacitor of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention. 8 is a cross-sectional view illustrating a process of manufacturing a gate pad part GPA of an array substrate for a liquid crystal display device according to a second embodiment of the present invention, and FIGS. 8A to 8D illustrate an array substrate for a liquid crystal display device according to a second embodiment of the present invention. Step-by-step process cross-sectional view of the data pad portion (DPA) of the. In this case, for the convenience of description, the same components are added by adding 100 to the reference numerals given to the first embodiment. In addition, the part which advances the process similar to 1st Example was abbreviate | omitted.

First, as shown in FIGS. 6A, 7A, and 8A, the transparent insulating substrate 201 proceeds in the same manner as the method shown by FIGS. 3A to 3C, 4A to 4C, and 5A to 5C of the first embodiment. In the switching region TrA, an insulating pattern 212 whose upper surface has a width d3 of 1 µm to 2 µm is formed. In this case, a second photoresist pattern 282 having a width d2 of about 3 μm to about 4 μm is formed on the insulating pattern 212 through ashing or the like to form the same.

Next, as shown in FIGS. 6B, 7B and 8B, the second photoresist pattern 282 of FIG. 6A is stripped and removed to leave only the insulating pattern 212 on the substrate 201. Thereafter, a metal material, for example, molybdenum (Mo) or molybdenum alloy (MoTi), is deposited on the entire surface of the substrate 201 over the insulating pattern 212 to form the first metal layer 220, and subsequently, impurity amorphous silicon is deposited. The impurity amorphous silicon layer 227 is formed.

Thereafter, a photoresist is applied onto the impurity amorphous silicon layer 227 to form a second photoresist layer 283. In this case, the photoresist layer 283 has a first thickness t1 corresponding to a portion where the insulating pattern 212 is formed, and a second thickness t2 thicker than the first thickness t1 corresponding to other regions. It is characterized in that it is formed to have.

Next, as shown in Figs. 6C, 7C and 8C, the photoresist layer (283 in Figs. 6B, 7B and 8B) formed with the first and second thicknesses (t1 and t2 in Figs. 6B, 7B and 8B) is formed. Ashing is performed to reduce the thickness of the photoresist layer (FIGS. 6B and 7B) completely on the top of the insulating pattern 212 having the first thickness (t1 in FIG. 8B). And the surface of the photoresist layer (283 of FIGS. 6B, 7B and 8B) formed in a region other than the insulating pattern 212 is formed by removing 283 of 8B and appropriately adjusting the ashing time. The ashing is stopped at a time point to coincide with the surface of the insulating pattern 212. In this case, although in the region other than the insulating pattern 212 is formed, the second photoresist layer 284 is formed by covering the impurity amorphous silicon layer 227 and having the third thickness t3 although it is reduced. On the other hand, the impurity amorphous silicon layer 227 is exposed to correspond to the insulating pattern 212.

Next, as shown in FIGS. 6D, 7D, and 8D, the impurity amorphous silicon layer 227 exposed to the outside of the second photoresist layer 284 of FIGS. 6C, 7C, and 8C by performing dry etching. ) And the lower first metal layer 220 are removed to expose the insulating pattern 212. In this case, the impurity amorphous silicon layer 227 and the lower first metal layer 220 may be spaced apart from each other with the insulating pattern 212 interposed therebetween. In this case, the impurity amorphous silicon layer 227 may be formed to be spaced apart only by about 1 μm to 2 μm, the width d3 of the upper surface of the insulating pattern 212, and may be formed in an active layer (not shown). It can be seen that the channel region can be formed in a length of about 1 ㎛ to 2 ㎛.

Subsequently, the process may be performed in the same manner as the processes illustrated in FIGS. 3F to 3I, 4F to 4I, and 5F to 5I of the first embodiment, thereby completing the array substrate for the liquid crystal display device according to the second embodiment of the present invention. have.

1 is an exploded perspective view of a general liquid crystal display device.

2 is a cross-sectional view of a portion including a thin film transistor in one pixel area of an array substrate of a conventional liquid crystal display device.

3A to 3I are cross-sectional views illustrating manufacturing processes of one pixel area including a thin film transistor and a storage capacitor of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

4A to 4I are cross-sectional views illustrating manufacturing steps of a gate pad portion of an array substrate for a liquid crystal display device according to a first embodiment of the present invention.

5A to 5I are cross-sectional views illustrating manufacturing steps of a data pad unit of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

6A through 6D are cross-sectional views illustrating manufacturing steps of one pixel area including a thin film transistor and a storage capacitor of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

7A to 7D are cross-sectional views illustrating manufacturing steps of a gate pad portion of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8A through 8D are cross-sectional views illustrating manufacturing steps of a data pad unit of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

101: substrate 112: insulating pattern

120: first metal layer 127: impurity amorphous silicon layer

182: first photoresist pattern d2: width of first photoresist pattern

d3: width of the upper surface of the insulating pattern StgA: storage area

TrA: Switching Area

Claims (14)

An insulating pattern formed on the substrate with a first width at an upper surface thereof; Source and drain electrodes formed on the substrate to be in contact with one side and the other side and spaced apart from each other while exposing an upper surface of the insulating pattern; An ohmic contact layer formed on the source and drain electrodes to expose an upper surface of the insulating pattern and spaced apart from each other with the insulating pattern interposed therebetween; An ohmic contact layer spaced apart from each other and an active layer formed on the insulating pattern; A gate insulating film covering the active layer; A gate electrode integrally formed on the gate insulating layer and overlapping the insulating pattern and the source and drain electrodes; A protective layer having a drain contact hole for covering the gate electrode and exposing the drain electrode; A pixel electrode formed in contact with the drain electrode through the drain contact hole on the protective layer; Array substrate comprising a. The method of claim 1, And the first width is 1 μm to 3 μm. The method of claim 1, A data line connected to the source electrode on the substrate and extending in one direction and a data pad electrode connected to one end of the data line; A gate line connected to the gate electrode over the gate insulating layer and defining a pixel area crossing the data line and a gate pad electrode connected to one end of the gate line; Array substrate comprising a. The method of claim 3, wherein And the pixel electrode is formed to overlap the gate wiring of the front end of the pixel region. The method of claim 1, And the insulating pattern has a tapered shape in cross section. Forming an insulating pattern on the substrate, the insulating pattern having an upper surface thereof at a first width; A source and drain electrode contacting one side surface and the other side surface of the insulating pattern and exposing the top surface of the insulating pattern and spaced apart from each other, and an ohmic contact spaced apart from each other by exposing the top surface of the insulating pattern to the source and drain electrodes. Forming a layer, an active layer integrated over the insulating pattern and the ohmic contact layer; Forming a gate insulating film over the active layer; Forming a gate electrode on the gate insulating layer, the gate electrode overlapping the insulating pattern and both ends of the gate insulating layer respectively overlapping the source and drain electrodes; Forming a protective layer having a drain contact hole exposing the drain electrode over the gate electrode; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer; Method of manufacturing an array substrate comprising a. The method of claim 6, Forming the insulating pattern, Forming an insulating layer on the entire surface of the substrate; Forming a first photoresist pattern having a second width greater than the first width over the insulating layer; Subjecting the first photoresist pattern having the second width to a third width smaller than a second width and larger than the first width; Performing dry etching on the insulating layer exposed to the outside of the first photoresist pattern having the third width to form the insulating pattern to have an undercut shape under the first photoresist pattern. Method of manufacturing an array substrate comprising a. The method of claim 7, wherein The insulating pattern is a method of manufacturing an array substrate, characterized in that the side surface is formed with an angle of 30 to 60 degrees to form a tapered form of the cross-section. The method of claim 7, wherein Forming source and drain electrodes spaced apart from each other on both sides, including both sides of the insulating pattern, the ohmic contact layer spaced apart from each other, and the active layer formed on the insulating pattern and the ohmic contact layer, Forming a first metal layer on the entire surface of the substrate over the first photoresist pattern on the insulating pattern; Forming an impurity amorphous silicon layer over the first metal layer; Exposing an upper surface of the insulating pattern by removing the first photoresist pattern, the first metal layer and the impurity amorphous silicon layer formed thereon; Forming a pure amorphous silicon layer over the non-removed impurity amorphous silicon layer including an upper portion of the exposed insulating pattern; Successively patterning the pure amorphous silicon layer, an impurity amorphous silicon layer below it, and the first metal layer Method of manufacturing an array substrate comprising a. The method of claim 6, The first width is 1㎛ 3㎛ manufacturing method of the array substrate. The method of claim 6, Forming the source and drain electrodes, Forming a data line connected to the source electrode and extending in one direction on the substrate, and a data pad electrode connected to one end of the data line. The method of claim 11, Forming the gate electrode, Forming a gate line connected to the gate electrode and defining a pixel area on the gate insulating layer and crossing the data line, and a gate pad electrode connected to one end of the gate line. The method of claim 12, Forming the protective layer having the drain contact hole, Forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. The method of claim 13, Forming the pixel electrode, Forming a gate auxiliary pad electrode in contact with the gate pad electrode through the gate pad contact hole, and a data auxiliary pad electrode in contact with the data pad electrode through the data pad contact hole. Way.

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