KR20090053309A - Method for preventing kirkendall void formation for packages fabricated by joining an electronic component finished with electroplated cu to solder and electronic packages fabricated by using the same - Google Patents

Method for preventing kirkendall void formation for packages fabricated by joining an electronic component finished with electroplated cu to solder and electronic packages fabricated by using the same Download PDF

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KR20090053309A
KR20090053309A KR1020070120103A KR20070120103A KR20090053309A KR 20090053309 A KR20090053309 A KR 20090053309A KR 1020070120103 A KR1020070120103 A KR 1020070120103A KR 20070120103 A KR20070120103 A KR 20070120103A KR 20090053309 A KR20090053309 A KR 20090053309A
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solder
electronic component
electronic
lead
copper
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KR1020070120103A
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KR100922891B1 (en
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유진
김종연
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한국과학기술원
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Priority to PCT/KR2007/006241 priority patent/WO2009066825A1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/268—Pb as the principal constituent
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01—ELECTRIC ELEMENTS
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    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
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    • B23K2103/00—Materials to be soldered, welded or cut
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

본 발명은 접합되는 납을 함유하는 솔더 및 무연솔더에 황화물 형성원소를 첨가함으로써, 구리층 위에 형성되는 Cu3Sn 금속간 화합물의 내부 또는 Cu와 Cu3Sn의 계면에서 발생되는 커켄달 간극(Kirkendall void)의 형성을 억제하여 패키지의 신뢰성을 향상시키는 방법에 관한 것으로, 본 발명에 의한 방법에 의하면, 전자패키지의 솔더 접합부에서 빈번히 발생하는 커켄달 간극의 형성을 억제하여 전자부품의 전기적, 기계적, 열적 신뢰성을 향상시킬 수 있다.According to the present invention, the addition of sulfide-forming elements to solder and lead-free solder to be bonded lead, the Kirkendall (Kirkendall) generated inside the Cu 3 Sn intermetallic compound formed on the copper layer or at the interface between Cu and Cu 3 Sn The present invention relates to a method for improving the reliability of a package by suppressing the formation of voids). According to the method of the present invention, the electrical, mechanical, and electrical Thermal reliability can be improved.

커켄달 간극, 구리, 솔더, 황화물 형성원소, 접합, 전자부품 Kirkendal Gap, Copper, Solder, Sulfide Forming Elements, Bonding, Electronic Components

Description

전해도금 구리로 표면처리된 전자부품과 솔더의 접합시에 발생하는 커켄달 간극의 억제방법 및 이에 의해 제조된 전자패키지{Method for preventing Kirkendall void formation for packages fabricated by joining an electronic component finished with electroplated Cu to solder and electronic packages fabricated by using the same}Method for preventing Kirkendall void formation for packages fabricated by joining an electronic component finished with electroplated Cu to solder and electronic packages fabricated by using the same}

본 발명은 전해도금 구리로 표면처리된 전자부품과 솔더의 접합시에 발생하는 커켄달 간극의 억제방법 및 이에 의해 제조된 전자패키지에 관한 것으로, 좀더 상세하게는, 접합되는 납을 함유하는 솔더 및 무연솔더에 황화물 형성원소를 첨가함으로써, 구리층 위에 형성되는 Cu3Sn 금속간 화합물의 내부 또는 Cu와 Cu3Sn의 계면에서 발생되는 커켄달 간극(Kirkendall void)의 형성을 억제하여 패키지의 신뢰성을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for suppressing a Kerkendal gap generated during bonding of an electronic component and a solder surface-treated with electroplating copper, and an electronic package manufactured by the solder. By adding sulfide-forming elements to the lead-free solder, it is possible to suppress the formation of Kirkendall voids generated in the Cu 3 Sn intermetallic compound formed on the copper layer or at the interface between Cu and Cu 3 Sn, thereby improving package reliability. It is about how to improve.

전자소자의 패키지 공정에서 플립칩이나 BGA(ball gird array) 패키지와 같 이 솔더를 이용한 접속방법은 기존의 와이어 본딩, TAB(tape automated bonding), 리드프레임을 이용한 접속방법에 비해 접속밀도가 훨씬 높기 때문에, 효율성이 높고 짧은 접속거리를 가지므로 고주파대역에서도 전기적 신호의 손실이 작은 관계로 현재 또는 미래의 패키지 기술로 각광받고 있다. In the packaging process of electronic devices, the connection method using solder, such as flip chip or ball gird array (BGA) package, has a much higher connection density than the conventional connection method using wire bonding, tape automated bonding (TAB), and lead frame. Because of the high efficiency and short connection distance, the loss of the electrical signal is high in the high frequency band.

솔더를 이용한 접합에서 가장 중요한 사항은 솔더와 하부 금속층 (under bump metallization; UBM) 사이에서 안정한 금속간 화합물을 형성하여 열적, 기계적, 전기적 신뢰성을 보장하는 것이다. The most important aspect of solder joints is the formation of stable intermetallic compounds between the solder and the under bump metallization (UBM) to ensure thermal, mechanical and electrical reliability.

납-주석 합금은 대표적인 솔더재료로 사용되어 왔지만, 납의 유해성으로 인하여 전자부품에서 납의 사용이 규제 및 금지되고 있다. 따라서 납을 함유하지 않는 무연솔더의 개발이 지속적으로 이루어지고 있고, 현재 Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Zn, Sn-Zn-Bi 계열의 무연솔더들이 Pb-Sn을 대체하고 있다. Although lead-tin alloys have been used as a representative solder material, the use of lead in electronic components is regulated and prohibited due to the harmfulness of lead. Therefore, lead-free solders that do not contain lead are continuously being developed, and lead-free solders of Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Zn, and Sn-Zn-Bi series have been developed. It is replacing.

한편, 솔더와 접합시에 사용되는 금속층은 전해 니켈, 무전해 니켈, OSP (Organic solderability preservative) 처리된 전해 구리 등이 주로 사용되고 있으며, 현재 칩, BGA 패키지 및 인쇄회로 기판에 적용되고 있다. 특히, 전해구리는 솔더와 젖음성이 매우 우수하고 공정비용이 저렴하기 때문에, 전자패키지 접속에 가장 광범위하게 적용되고 있다. On the other hand, as the metal layer used for soldering and bonding, electrolytic nickel, electroless nickel, organic solderability preservative (OSP) electrolytic copper, and the like are mainly used, and are currently applied to chips, BGA packages, and printed circuit boards. In particular, electrolytic copper is most widely applied to electronic package connection because of its excellent solder and wettability and low process cost.

전해구리와 솔더의 반응을 살펴보면, 접합을 위한 리플로우 공정에서 구리와 솔더의 계면에 Cu6Sn5 금속간 화합물이 발생한다. 그리고 솔더의 용융점 이하에서 열처리를 하면 Cu6Sn5 아래에 Cu3Sn이 발생하여 성장하는데, Cu3Sn의 내부 또는 Cu3Sn과 Cu의 계면에서 커켄달 간극이 형성되어 성장하게 된다. Looking at the reaction between copper and solder, Cu 6 Sn 5 intermetallic compounds are generated at the interface between copper and solder in the reflow process for bonding. And when the heat treatment at the melting point or less of the solder to grow the Cu 3 Sn occurs under the Cu 6 Sn 5, it is greater growth this Kendall gap is formed at the interface of the Cu 3 Sn Cu 3 Sn and Cu or inside of.

상기 커켄달 간극은 전해구리를 사용하는 경우 심각하게 발생되는 것으로 알려져 있는데, 이는 전자부품을 전기적, 기계적으로 매우 취약하게 하기 때문에, 이를 해결하기 위한 연구가 요청되고 있다. The Kerkendal gap is known to occur seriously when using electrolytic copper, which makes electronic parts very vulnerable electrically and mechanically, and therefore, research for solving the problem is required.

특히, 고성능, 고기능화, 초소형화되고 있는 휴대용 전자기기에 솔더를 이용한 접속기술이 보편화되면서, 전기적, 기계적 충격에 강한 패키지 기술이 요구되므로 전해구리와 솔더의 접합공정에서 커켄달 간극의 발생을 억제하여 신뢰성을 향상시키기 위한 방안이 절실히 요구되고 있다. In particular, as connection technology using solder is becoming popular in portable electronic devices that are highly efficient, highly functionalized, and miniaturized, package technology that is resistant to electrical and mechanical shocks is required. There is an urgent need for measures to improve reliability.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 전해도금 구리로 표면처리된 전자부품과 솔더의 접합후, 솔더조인트에서 발생하는 커켄달 간극의 형성을 억제하여 패키지의 신뢰성을 향상시킬 수 있는 방법을 제공하는 것이다.The present invention has been made to solve the above problems of the prior art, an object of the present invention is to suppress the formation of the kekendal gap generated in the solder joint after the bonding of the electronic component and the solder surface-treated with electroplating copper. This is to provide a way to improve the reliability of the package.

본 발명의 다른 목적은 상기의 방법을 이용하여 전해도금 구리로 표면처리된 전자부품과 솔더를 접합시킨 접합부를 포함하는 전자 패키지를 제공하는 것이다.Another object of the present invention is to provide an electronic package including a joint portion in which an electronic component and a solder are bonded to each other by using the above-described method.

본 발명은 상기의 목적을 달성하기 위하여, 전해도금 구리로 표면처리된 전자부품과 솔더의 접합시에 발생하는 커켄달 간극(Kirkendall void)의 형성을 억제하는 방법에 있어서, 황화물 형성원소를 첨가한 솔더를 이용하여 전자부품과 솔더의 접합부를 형성하는 단계를 포함하는 것을 특징으로 하는 전해도금 구리로 표면처리된 전자부품과 솔더의 접합시에 발생하는 커켄달 간극의 억제방법을 제공한다.In order to achieve the above object, the present invention provides a method for suppressing the formation of Kirkendall voids generated at the time of joining an electronic component and solder surface-treated with electroplating copper, and adding sulfide forming elements. It provides a method of suppressing the kekendal gap that occurs during the bonding of the solder and the electronic component surface-treated with electroplating copper, characterized in that it comprises the step of forming a junction of the electronic component and the solder using the solder.

또한, 본발명은 전해도금 구리로 표면처리된 전자부품과 솔더를 상기의 방법에 의해 접합시킨 접합부를 포함하는 전자 패키지를 제공한다.The present invention also provides an electronic package including a junction portion in which an electronic component surface-treated with electroplating copper and a solder are joined by the above method.

본 발명에 의한 방법에 의하면, 전자패키지의 솔더 접합부에서 빈번히 발생하는 커켄달 간극의 형성을 억제하여 전자부품의 전기적, 기계적, 열적 신뢰성을 향상시킬 수 있다.According to the method of the present invention, it is possible to suppress the formation of the kekendal gap frequently occurring at the solder joint of the electronic package, thereby improving the electrical, mechanical and thermal reliability of the electronic component.

본 발명의 일 태양은, 전해도금 구리로 표면처리된 전자부품과 솔더의 접합시에 발생하는 커켄달 간극(Kirkendall void)의 형성을 억제하는 방법에 있어서, 황화물 형성원소를 첨가한 솔더를 이용하여 전자부품과 솔더의 접합부를 형성하는 단계를 포함하는 것을 특징으로 하는 전해도금 구리로 표면처리된 전자부품과 솔더의 접합시에 발생하는 커켄달 간극의 억제방법에 관한 것이다.One aspect of the present invention is a method of suppressing the formation of Kirkendall voids generated at the time of joining an electronic component and solder surface-treated with electroplating copper, using a solder containing a sulfide-forming element. The present invention relates to a method for suppressing a kekendal gap generated during bonding of an electronic component and a solder surface-treated with electroplating copper, characterized by forming a joint portion of the electronic component and the solder.

전해도금 구리와 솔더의 접합시 발생하는 커켄달 간극은 전해구리의 내부에 함유되어 있는 황에 의해 형성 및 성장하게 되는데, 황화물 형성원소를 첨가한 솔더를 이용하여 전자부품과 솔더의 접합부를 형성할 경우, 전해도금 구리와 솔더 재료의 금속간 화합물의 계면에 집적되는 황의 함량이 낮아지기 때문에, 커켄달 간극의 형성을 억제할 수 있게 된다.The kekendal gap generated during electroplating copper and solder bonding is formed and grown by the sulfur contained in the electrolytic copper, and the solder joint containing the sulfide forming element is used to form the junction between the electronic component and the solder. In this case, since the content of sulfur accumulated at the interface between the electroplated copper and the intermetallic compound of the solder material is lowered, it is possible to suppress the formation of the Kerkendal gap.

본 발명에 의한 커켄달 간극의 억제방법에 사용되는 상기 황화물 형성원소로는 Mn, Zn, Mg, V, Na, Cr, Fe, W, Mo, Co 및 Ni로 이루어진 군에서 선택된 1종 이상인 것이 바람직하나, 이에 한정되는 것은 아니다. The sulfide forming element used in the method for suppressing the kekendal gap according to the present invention is preferably at least one selected from the group consisting of Mn, Zn, Mg, V, Na, Cr, Fe, W, Mo, Co and Ni. However, the present invention is not limited thereto.

본 발명에 의한 커켄달 간극의 억제방법은, 솔더에 소량의 황화물 형성원소의 첨가에 의해 전해도금 구리와 Cu3Sn 금속간 화합물의 계면에 집적되는 황이 급격히 줄어든다는 점에서 솔더에 상기 황화물 형성원소를 0.01~5 중량%, 바람직하게는 0.1~4 중량%, 보다 바람직하게는 0.1~ 1 중량% 첨가하는 것이 좋다.The method of suppressing the Kerkendal gap according to the present invention is that the sulfide forming element in the solder is rapidly reduced in the amount of sulfur accumulated at the interface between the electroplated copper and the Cu 3 Sn metal compound by the addition of a small amount of sulfide forming element to the solder. 0.01 to 5% by weight, preferably 0.1 to 4% by weight, more preferably 0.1 to 1% by weight.

본 발명에 의한 커켄달 간극의 억제방법이 적용될 수 있는 상기 솔더로는 납(Pb)을 함유하거나 납을 함유하지 않은 무연솔더 모두에 적용될 수 있다.The solder to which the method of suppressing the Kirkendal gap according to the present invention may be applied may be applied to both lead-free solder containing Pb or no lead.

상기 납을 함유하는 솔더의 재료의 예로는 Pb-Sn를 들 수 있으나, 반도체 칩과 패키지 부품의 접합공정, 패키지 부품과 인쇄회로 기판의 접합공정, 반초체 칩과 인쇄회로 기판의 접합공정과 같이 전자부품 상호간의 접합공정에 사용되는 솔더라면 제한없이 적용될 수 있다. Examples of the material of the solder containing lead include Pb-Sn, but the bonding process of the semiconductor chip and the package part, the bonding process of the package part and the printed circuit board, and the bonding process of the semi-super chip and the printed circuit board. Any solder used for the bonding process between electronic components can be applied without limitation.

상기 무연솔더의 재료로는 Sn, Sn-Ag, Sn-Ag-Cu, Sn-Cu, Sn-Bi 및 Sn-In으로 이루어진 군에서 선택된 1종 이상을 예로 들 수 있으나, 반도체 칩과 패키지 부품의 접합공정, 패키지 부품과 인쇄회로 기판의 접합공정, 반초체 칩과 인쇄회로 기판의 접합공정과 같이 전자부품 상호간의 접합공정에 사용되는 솔더라면 제한없이 적용될 수 있다. The lead-free solder may include at least one selected from the group consisting of Sn, Sn-Ag, Sn-Ag-Cu, Sn-Cu, Sn-Bi, and Sn-In. Any solder used for the bonding process between electronic components such as a bonding process, a bonding process between a package part and a printed circuit board, and a bonding process between a semi-super chip and a printed circuit board may be applied without limitation.

본 발명에 의한 커켄달 간극의 억제방법은 상기 황화물 형성원소를 첨가한 솔더를 이용하여 형성된 전자부품과 솔더의 접합부를 열처리하는 단계를 더 포함할 수 있다. The method of suppressing the kekendal gap according to the present invention may further include heat treating a junction between the electronic component and the solder formed using the solder to which the sulfide forming element is added.

본 발명에 의한 방법에 의하면, 상기 열처리 후, 구리 금속 위에 Cu6Sn5 와 Cu3Sn 두가지의 금속간 화합물이 형성되는데, Cu3Sn 내부 또는 Cu3Sn과 Cu 계면의 커켄달 간극의 발생을 상당량 억제할 수 있다.According to the method of the present invention, after the heat treatment, there is on the copper metal is Cu 6 Sn 5 and Cu 3 Sn two kinds of intermetallic compound formed, the Cu 3 Sn within or Cu 3 Sn, and the generation of large Kendall gap of Cu interface A considerable amount can be suppressed.

본 발명에 의한 방법이 적용될 수 있는 전자부품으로는 전해도금 구리로 표면처리된 전자부품과 솔더를 상기의 방법에 의해 접합시킨 접합부를 포함하는 전자 패키지에 관한 것이다. The electronic component to which the method according to the present invention can be applied relates to an electronic package including a junction portion in which an electronic component surface-treated with electroplating copper and a solder are joined by the above method.

상기 전자패키지의 예로는 칩, BGA 패키지, 인쇄회로 기판 등을 예로 들 수 있으나, 이에 한정되는 것은 아니며 전해도금 구리와 솔더 재료를 사용하는 접속공정 및 표면처리 공정에 제한없이 적용될 수 있다.Examples of the electronic package may include a chip, a BGA package, a printed circuit board, and the like, but are not limited thereto. The electronic package may be applied without limitation to a connection process and a surface treatment process using electroplating copper and a solder material.

이하 본 발명의 내용을 실시예 및 시험예를 통하여 구체적으로 설명한다. 그러나, 이들은 본 발명을 보다 상세하게 설명하기 위한 것으로 본 발명의 권리범위가 이들에 의해 한정되는 것은 아니다. Hereinafter, the content of the present invention will be described in detail through examples and test examples. However, these are intended to explain the present invention in more detail, and the scope of the present invention is not limited thereto.

실시예 1 (Mn이 첨가된 솔더와 황이 함유된 전해도금 구리를 이용한 패키지 부품의 접합)Example 1 Bonding of Package Components Using Solder Added Mn and Electroplated Copper Containing Sulfur

본 실시예에서는 0.5 중량% Mn이 함유되어 있는 Sn-3.5Ag-0.5Mn 솔더와 황이 함유된 전해도금 구리로 표면처리된 인쇄회로 기판을 260℃에서 1분 동안 리플로 후, 패키지 부품을 제조하였다. In this embodiment, the printed circuit board surface-treated with Sn-3.5Ag-0.5Mn solder containing 0.5 wt% Mn and electroplating copper containing sulfur was reflowed at 260 ° C. for 1 minute, and then a package part was manufactured. .

도 1은 상기 실시예 1에 의해 형성된 Sn-3.5Ag-0.5Mn 무연솔더와 황이 함유된 전해구리로 표면처리된 인쇄회로 기판을 접합 후, 150℃에서 960시간 열처리한 접속부위의 단면을 나타낸 주사전자현미경 사진이다.       FIG. 1 is a cross-sectional view of a connection portion of a Sn-3.5Ag-0.5Mn lead-free solder formed by Example 1 and a bonded circuit board surface-treated with sulfur-containing electrolytic copper after heat treatment at 150 ° C. for 960 hours. Electron micrograph.

상기 도 1을 참조하면, 전해도금 구리(10)와 Sn-3.5Ag-0.5Mn(12)의 계면에 Cu6Sn5(16)와 Cu3Sn(18) 두가지 금속간 화합물이 형성되어 있는 것을 알 수 있는데, Cu3Sn의 내부를 살펴보면, 커켄달 간극(20)의 형성이 억제되어 있음을 확인할 수 있다. Referring to FIG. 1, two intermetallic compounds of Cu 6 Sn 5 (16) and Cu 3 Sn (18) are formed at the interface between the electroplated copper 10 and Sn-3.5Ag-0.5Mn (12). As can be seen, the inside of the Cu 3 Sn, it can be seen that the formation of the Kirkendal gap 20 is suppressed.

실시예 2 (Zn이 첨가된 솔더와 황이 함유된 전해도금 구리를 이용한 패키지 부품의 접합)Example 2 Bonding of Package Components Using Solder Added Zn and Electroplated Copper Containing Sulfur

황화물 형성원소로 Mn 대신에 Zn을 0.1 중량% 첨가하고, 실시예 1과 동일하게 열처리하여 Zn이 첨가된 솔더와 황이 함유된 전해도금 구리로 표면처리된 인쇄회로 기판을 260℃에서 1분 동안 리플로 후, 패키지 부품을 제조하였다. 0.1 wt% Zn was added instead of Mn as a sulfide forming element, and the same heat treatment was performed as in Example 1 to ripple the printed circuit board surface-treated with electroplated copper containing Zn and solder containing sulfur for 1 minute at 260 ° C. After, the package parts were manufactured.

도 2는 상기 실시예 2에 의해 형성된 Sn-3.5Ag-0.1Zn 무연솔더와 황이 함유된 전해구리로 표면처리된 인쇄회로 기판을 접합 후, 150℃에서 960시간 열처리한 접속부위의 단면을 나타낸 주사전자현미경 사진이다.       FIG. 2 is a cross-sectional view of a connection portion of a Sn-3.5Ag-0.1Zn lead-free solder formed by Example 2 and a bonded circuit board surface-treated with sulfur-containing electrolytic copper after heat treatment at 150 ° C. for 960 hours. Electron micrograph.

상기 도 2을 참조하면, Mn이 첨가된 것과 유사하게 전해도금 구리(10)와 Sn-3.5Ag-0.1Zn(12)의 계면에 커켄달 간극(20)의 형성이 억제되어 있음을 확인할 수 있다. Referring to FIG. 2, it can be seen that the formation of the kekendal gap 20 is suppressed at the interface between the electroplated copper 10 and the Sn-3.5Ag-0.1Zn 12 similarly to the addition of Mn. .

비교예 (Sn-3.5Ag 솔더와 황이 함유된 전해도금 구리를 이용한 패키지 부품의 접합)) Comparative Example (junction of package parts using Sn-3.5Ag solder and electroplated copper containing sulfur)

솔더로 황화물 형성원소가 첨가되지 않은 Sn-3.5Ag(14)를 사용하고, 전해구리의 접합 후 열처리 조건을 150℃에서 120시간으로 한 것을 제외하고는 실시예 1과 동일하게 실시하여 황화물 형성원소가 첨가되지 않은 솔더와 황이 함유된 전해도금 구리로 표면처리된 인쇄회로 기판을 접합하여 패키지 부품을 제조하였다. A sulfide forming element was prepared in the same manner as in Example 1 except that Sn-3.5Ag (14) having no sulfide forming element added thereto was used as a solder, and the heat treatment condition after joining the electrolytic copper was 120 hours at 150 ° C. A package part was manufactured by bonding a printed circuit board surface-treated with an electroless plated copper containing sulfur and a solder without addition.

도 3은 상기 비교예에 의해 형성된 전해도금 구리로 표면처리된 인쇄회로 기 판을 Sn-3.5Ag 솔더와 접합 후, 150℃에서 120시간 동안 열처리한 접속부위의 단면을 나타낸 주사전자현미경 사진이다.      FIG. 3 is a scanning electron micrograph showing a cross section of a connection part of a printed circuit board surface-treated with electroplated copper formed by the comparative example after Sn-3.5Ag solder and heat-treated at 150 ° C. for 120 hours.

상기 도 3을 참조하면, 짧은 시간에도 불구하고 커켄달 간극(20)이 전해도금 구리(10)와 Cu3Sn(18)의 계면에 형성되어 있음을 알 수 있다. Referring to FIG. 3, it can be seen that the Kerkendal gap 20 is formed at the interface between the electroplated copper 10 and the Cu 3 Sn 18 despite a short time.

이상으로부터, 상기 커켄달 간극은 전해구리의 내부에 함유되어 있는 황으로 인하여 발생 및 성장하지만, 황화물을 형성하면 전해도금 구리와 Cu3Sn 계면에 집적되는 황의 함량이 떨어지기 때문에, 커켄달 간극의 형성을 억제할 수 있음을 알 수 있다. From the above, the Kerkendal gap is generated and grown due to the sulfur contained in the electrolytic copper, but when sulfides are formed, the content of sulfur accumulated at the electroplated copper and Cu 3 Sn interfaces decreases. It can be seen that formation can be suppressed.

시험예 (기계적 신뢰성 측정) Test Example (Measurement of Mechanical Reliability)

상기 실시예 2 및 비교예에서 제조한 접합부를 포함하는 BGA 패키지의 기계적 신뢰성을 측정하기 위하여 충격시험을 실시하였다. An impact test was performed to measure the mechanical reliability of the BGA package including the joint prepared in Example 2 and Comparative Example.

도 4는 상기 시험예에 따라, 열처리 시간의 증가에 따른 충격시험 동안의 파괴횟수를 나타내는 그래프이다. 4 is a graph showing the number of breaks during the impact test with increasing heat treatment time according to the test example.

상기 도 4를 참조하면, 커켄달 간극은 충격신뢰성을 급격히 떨어뜨리는 원인이 되지만, 황화물 형성원소인 Zn이 커켄달 간극의 형성을 억제함으로써 보다 우수한 충격신뢰성을 보임을 알 수 있다.Referring to FIG. 4, the Kerkendal gap causes a sharp drop in impact reliability. However, Zn, a sulfide forming element, shows better impact reliability by suppressing formation of the Kerkendal gap.

상술한 바와 같이, 본 발명의 바람직한 실시예를 참조하여 설명하였지만 해 당 기술 분야의 숙련된 당업자라면 하기의 특허청구범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다. As described above, although described with reference to the preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

본 발명에 의한 방법은 반도체 칩과 패키지 부품을 접합하거나, 패키지 부품과 인쇄회로 기판을 접합할 때 혹은 반도체 칩과 인쇄회로 기판을 플립칩 형태로 직접 접합할 때 사용되는 솔더에 적용가능하다. The method according to the present invention is applicable to solders used when bonding semiconductor chips and package parts, bonding package parts and printed circuit boards, or direct bonding of semiconductor chips and printed circuit boards in the form of flip chips.

도 1은 실시예 1에 따라, 전해도금 구리로 표면처리된 인쇄회로 기판을 Sn-3.5wt%Ag-0.5wt%Mn 솔더와 접합 후, 150°C에서 960시간 동안 열처리한 솔더조인트의 단면을 나타낸 주사전자현미경 사진,1 is a cross-sectional view of a solder joint heat-treated at 150 ° C for 960 hours after bonding a printed circuit board surface-treated with electroplated copper with Sn-3.5wt% Ag-0.5wt% Mn solder according to Example 1 Scanning electron micrograph,

도 2는 실시예 2에 따라, 전해도금 구리로 표면처리된 인쇄회로 기판을 Sn-3.5wt%Ag-0.1wt%Zn 솔더와 접합 후, 150°C에서 960시간 동안 열처리한 솔더조인트의 단면을 나타낸 주사전자현미경 사진, 2 is a cross-sectional view of a solder joint heat-treated at 150 ° C. for 960 hours after bonding a printed circuit board surface-treated with electroplated copper with Sn-3.5 wt% Ag-0.1 wt% Zn solder according to Example 2; Scanning electron micrograph,

도 3은 비교예에 따라, 전해도금 구리로 표면처리된 인쇄회로 기판을 Sn-3.5wt%Ag 솔더와 접합 후, 150°C에서 120시간 동안 열처리한 솔더조인트의 단면을 나타낸 주사전자현미경 사진,3 is a scanning electron micrograph showing a cross section of a solder joint heat-treated at 150 ° C for 120 hours after bonding a printed circuit board surface-treated with electroplated copper with Sn-3.5wt% Ag solder according to a comparative example,

도 4는 시험예에 따라, 열처리 시간의 증가에 따른 충격시험 동안의 파괴횟수를 나타내는 그래프이다. 4 is a graph showing the number of breaks during the impact test with increasing heat treatment time according to the test example.

<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>

10 : 전해도금 구리, 12 : Sn-3.5wt%Ag-0.5wt%Mn         10: electroplated copper, 12: Sn-3.5wt% Ag-0.5wt% Mn

14 : Sn-3.5wt%Ag-0.1wt%Zn, 16 : Sn-3.5wt%Ag,         14: Sn-3.5wt% Ag-0.1wt% Zn, 16: Sn-3.5wt% Ag,

18 : Cu6Sn5 금속간 화합물, 20 : Cu3Sn 금속간 화합물 18: Cu 6 Sn 5 intermetallic compound, 20: Cu 3 Sn intermetallic compound

22 : 커켄달 간극(Kirkendall void)        22: Kirkendall void

Claims (9)

전해도금 구리로 표면처리된 전자부품과 솔더의 접합시에 발생하는 커켄달 간극(Kirkendall void)의 형성을 억제하는 방법에 있어서,In a method of suppressing the formation of Kirkendall voids generated at the joining of an electronic component and solder surface-treated with electroplating copper, 황화물 형성원소를 첨가한 솔더를 이용하여 전자부품과 솔더의 접합부를 형성하는 단계를 포함하는 것을 특징으로 하는 전해도금 구리로 표면처리된 전자부품과 솔더의 접합시에 발생하는 커켄달 간극의 억제방법.A method of suppressing the kekendal gap generated during the joining of an electronic component and a solder surface-treated with electroplated copper, comprising forming a junction between the electronic component and the solder by using a solder containing a sulfide forming element. . 제 1항에 있어서, 상기 황화물 형성원소가 Mn, Zn, Mg, V, Na, Cr, Fe, W, Mo, Co 및 Ni로 이루어진 군에서 선택된 1종 이상인 것을 특징으로 하는 커켄달 간극의 억제방법. The method of claim 1, wherein the sulfide forming element is at least one selected from the group consisting of Mn, Zn, Mg, V, Na, Cr, Fe, W, Mo, Co, and Ni. . 제 1항에 있어서, 상기 황화물 형성원소를 0.01-5 중량% 첨가하는 것을 특징으로 하는 커켄달 간극의 억제방법. The method of claim 1, wherein the sulfide forming element is added in an amount of 0.01-5% by weight. 제 1항에 있어서, 상기 솔더가 납(Pb)을 함유하거나 무연솔더인 것을 특징으로 하는 커켄달 간극의 억제방법. The method of claim 1, wherein the solder contains lead (Pb) or is a lead-free solder. 제 4항에 있어서, 상기 납을 함유하는 솔더의 재료가 Pb-Sn인 것을 특징으로 하는 커켄달 간극의 억제방법. 5. The method of suppressing a Kerkendal gap according to claim 4, wherein the lead-containing solder material is Pb-Sn. 제 4항에 있어서, 상기 무연솔더의 재료가 Sn, Sn-Ag, Sn-Ag-Cu, Sn-Cu, Sn-Bi 및 Sn-In으로 이루어진 군에서 선택된 1종 이상인 것을 특징으로 하는 커켄달 간극의 억제방법. The Kirkendal gap according to claim 4, wherein the lead-free solder is at least one selected from the group consisting of Sn, Sn-Ag, Sn-Ag-Cu, Sn-Cu, Sn-Bi, and Sn-In. Method of suppression. 제 1항에 있어서, 상기 황화물 형성원소를 첨가한 솔더를 이용하여 형성된 전자부품과 솔더의 접합부를 열처리하는 단계를 더 포함하는 것을 특징으로 하는 커켄달 간극의 억제방법. The method of claim 1, further comprising heat-treating the junction between the electronic component and the solder formed by using the solder to which the sulfide-forming element is added. 제 1항에 있어서, 상기 전자부품이 칩, BGA 패키지 또는 인쇄회로 기판인 것을 특징으로 하는 커켄달 간극의 억제방법.The method of claim 1, wherein the electronic component is a chip, a BGA package, or a printed circuit board. 전해도금 구리로 표면처리된 전자부품과 솔더를 제 1항 내지 제 8항 중 어느 한 항의 방법에 의해 접합시킨 접합부를 포함하는 전자 패키지. An electronic package comprising a junction portion in which an electronic component surface-treated with electroplating copper and a solder are joined by the method of any one of claims 1 to 8.
KR1020070120103A 2007-11-23 2007-11-23 Method for preventing Kirkendall void formation for packages fabricated by joining an electronic component finished with electroplated Cu containing sulfur to solder and electronic packages fabricated by using the same KR100922891B1 (en)

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