KR20090052815A - Semiconductor memory device - Google Patents

Abstract

The semiconductor memory device 10 includes a memory cell array 11 having a plurality of memory cells set in a low-resistance state / high-resistance state according to "0" data / "1" data. The assignment of “0” data / “1” data and low-resistance state / high-resistance state switches when the power is turned on.

Low-Resistance State, High-Resistance State, Memory Cells, Memory Cell Arrays, Switching

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a test method thereof, and for example, to a semiconductor memory device using a magnetoresistive element capable of recording information by allowing a current to flow in both directions.

Recently, various types of memories for recording information on the basis of new principles have been proposed, and as one of such memories, magnetic random access memory (MRAM) using a tunneling magnetoresistive (TMR) effect is known.

The MRAM stores "1" and "0" information through a magnetic tunnel junction (MTJ) device. The MTJ element has a structure formed by disposing a non-magnetic layer (tunnel barrier layer) between two magnetic layers (free layer and fin layer). The information stored in the MTJ element is determined by whether the spin directions of the two magnetic layers are parallel or anti-parallel.

In the spin transfer torque recording type MRAM, inversion of magnetization occurs because a current flowing in a direction perpendicular to the film surface of the MTJ element transfers a spin to the free layer along the flow direction of the current. When the MTJ element is of the vertical magnetization type, it is sufficient to provide uniaxial anisotropy in the direction perpendicular to the film surface, and it is unnecessary to provide magnetic shape anisotropy in the plane direction unlike the in-plane magnetization type. . Therefore, it is possible to set an aspect ratio of the MTJ element to approximately 1, and to reduce the size of the MTJ element to processing limitations. In addition, unlike the in-plane magnetization type, it is not necessary to provide a current induction magnetic field wiring that generates a current induction magnetic field in directions about two axes. The operation can be performed if there are two terminals connected to the upper and lower electrodes of the MTJ element, so that the cell area for each bit can be reduced.

Recently, a film of polysilicon magnesium oxide (MgO) oriented to the (001) plane, which is the tunnel barrier layer of the MTJ element, is disposed between the films of polysilicon CoFeB oriented to the (001) plane so that MgO serves as a spin filter. The magnetization of the free layer can be reversed in parallel from anti-parallel by injecting electrons from the pinned layer to the free layer, and the magnetization of the free layer can be reversed from parallel to anti-parallel by injecting electrons from the free layer into the pinned layer, It will be identified which magnesium oxide (MgO) is used as a preferred material for realizing a high TMR spin transfer torque recording type MRAM.

In order to reduce the write current, it is necessary to reduce the volume, the saturation magnetization (Ms), the damping constant, and the like of the free layer. However, there is a physical limit to the reduction of the film thickness to reduce the volume of the free layer, a treatment limit to the reduction of the area in the plane direction, and thermal stability becomes low when the damping constant is excessively reduced. Therefore, it is necessary to adjust the parameters in order to obtain the overall balance and reduce the write current, but it is not easy to reduce the factor. If the write current cannot be sufficiently reduced, the power supply voltage of the circuit is normally determined, so it is necessary to set the desired write current by reducing the film thickness of the MgO barrier and lowering its resistance. Therefore, the MgO barrier, which is a component of the MTJ device, must be thin enough and apply high voltage stress during operation.

In the case of the MTJ laminated film using MgO, even when formed into a thin film, the magnetoresistance ratio (MR ratio) exceeds 100%, so the resistance in the "1" state is set to a value almost equal to or twice the resistance in the "0" state. Therefore, the total stress applied to the film is the case where the MTJ element is set to the "0" state and the write current of "0" continues to flow, and the MTJ element is set to the "1" state and the write current of "1" continues. If it flows through, it is estimated to be quite different. Thus, if the stress applied is significantly different, the service life of the MTJ element is different.

For example, when MRAM is used for a drive recorder as image memory, when "0" information is intensively used and recorded in the MTJ element depending on the conditions of the application environment or the configuration of the decoder for image information, or "1" information is " It is estimated that the case where recording is more concentrated than the 0 "information occurs. Therefore, the service life of an MTJ device depends on the application environment, so the device must be designed to overcome the worst case environment as the device's specification. Therefore, a problem arises in that the device specifications must be strictly set accordingly.

As a technique related to the above technique, Japanese Patent Application Laid-open No. 2002-343078, which is the following patent document, is provided.

According to an aspect of the present invention, there is provided a memory cell array having a plurality of memory cells set to a low-resistance state / high-resistance state according to "0" data / "1" data, wherein said "0" data The assignment of the " 1 " data and the low-resistance state / high-resistance state provides a semiconductor memory device that switches when the power is turned on.

According to another aspect of the present invention, there is provided a memory cell array having a plurality of memory cells set to a low-resistance state / high-resistance state according to " 0 " data / " 1 " data, and a pulse at each predetermined time. And a timer circuit for generating, wherein the assignment of the " 0 " data / " 1 " data and the low-resistance state / high-resistance state provides a semiconductor memory device that switches each time the pulse is generated.

According to another aspect of the invention, a plurality of memory cell strings, each of the memory cell strings comprising a plurality of memory cells set to a low-resistance state / high-resistance state according to "0" data / "1" data And a plurality of memory cell arrays each provided for the memory cell string and configured to store allocation information of the "0" data / "1" data and the low-resistance state / high-resistance state. A semiconductor memory device including a flag cell and performing data write and data read operations based on the allocation information.

According to another aspect of the present invention, a memory cell having a plurality of memory cells selectively set to a low-resistance state and a high-resistance state according to stored data and a plurality of measurement cells each having the same configuration as the memory cell A semiconductor memory device including an array, each of the measurement cells accessed from the outside, and outputting characteristics of each of the measurement cells to the outside.

Embodiments of the present invention will now be described with reference to the accompanying drawings. In the following description, components having the same functions and configurations are denoted by the same symbols and described only when necessary.

[First Embodiment]

1 is a block diagram showing the configuration of a semiconductor memory device 10 according to a first embodiment of the present invention. The semiconductor memory device 10 includes a memory cell array 11, an address buffer 12, an input / output buffer 13, a row decoder 14, a column decoder 15, a write circuit 16 and 17, a read circuit. 18, column selection circuits 19 and 20, setting circuit 21, and control circuit 22.

The memory cell array 11 includes a plurality of memory cells MC arranged in a matrix form. In this embodiment, a case where the magnetoresistive element is used as the memory element 30 included in the memory cell MC is described, for example. 2 is a circuit diagram showing the configuration of the memory cell array 11.

The n bit lines BL1 to BLn extending in the column direction are arranged in the memory cell array 11. In the memory cell array 11, n bit lines / BL1 to / BLn extending in the column direction are arranged. In addition, m word lines WL1 to WLm extending in the row direction are arranged in the memory cell array 11. In this case, n and m are natural numbers equal to or greater than one.

The memory cell MC is disposed in the intersection region between the bit line pairs BL, / BL and the word line WL. Each memory cell MC includes a magnetoresistive element 30 and a selection transistor 31 used as a memory element. For example, the selection transistor 31 is configured of an N-channel MOSFET (metal oxide semiconductor field effect transistor).

3 is a sectional view showing the structure of the magnetoresistive element 30. Arrows shown in FIG. 3 indicate the direction of magnetization. The magnetoresistive element 30 sequentially stacks a lower electrode 32, a pinned layer (or fin layer) 33, a non-magnetic layer 34, a recording layer (or free layer) 35, and an upper electrode 36. It has a laminated structure obtained by. The stacking order of the pinned layer 33 and the recording layer 35 may be reversed.

The magnetization (or spin) direction of the pinned layer 33 is invariant (fixed). The magnetization direction of the recording layer 35 is variable (can be reversed). The gentle magnetization directions of the pinned layer 33 and the recording layer 35 may be set perpendicular to the film surface (vertical magnetization type) or parallel to the film surface (in-plane magnetization type). When the magnetoresistive element is formed in the vertical magnetization type, it may provide uniaxial anisotropy in a direction perpendicular to the film surface, and unlike the in-plane magnetization type, it is not necessary to provide magnetic shape anisotropy in the plane direction. . Therefore, since the aspect ratio of the magnetoresistive element can be set to 1 and the size of the magnetoresistive element can be reduced to the processing limit in principle, it is more preferable to use the vertical magnetization type in view of miniaturization and reduction of the write current.

Ferromagnetic materials are used as the recording layer 35 and the pinned layer 33. As the non-magnetic layer 34, a metal, an insulator or a semiconductor is used.

As a method for fixing the magnetization direction of the pinned layer 33, for example, a coercive force differential structure can be used. That is, by setting the coercive force of the pinned layer 33 sufficiently harder than the coercive force of the recording layer 35, the magnetization direction of the pinned layer 33 is fixed, and the magnetization direction of the recording layer 35 is variable. Can be configured. Alternatively, an antiferromagnetic layer can be added at a location adjacent to the pinned layer 33. In this case, the magnetization direction of the pinned layer 33 is fixed in one direction due to the exchange coupling between the pinned layer 33 and the antiferromagnetic layer. At the same time, high magnetic anisotropy energy is imparted to the pinned layer 33, and the function as the pinned layer 33 is imparted due to the exchange coupling between the pinned layer 33 and the antiferromagnetic layer.

One end (corresponding to the upper electrode 36) of each magnetoresistive element 30 is electrically connected to a corresponding one of the bit lines BL. The other end of the magnetoresistive element 30 (corresponding to the lower electrode 32) is electrically connected to the drain of the corresponding select transistor 31. The source of the select transistor 31 is electrically connected to the bit line / BL. The gate of the select transistor 31 is electrically connected to a corresponding one of the word lines WL.

The address buffer 12 receives an address signal ADD from the outside. Then, the address buffer 12 transmits the column address signal CA of the address signal ADD to the column decoder 15, and transmits the row address signal RA to the row decoder 14.

The row decoder 14 decodes the row address signal RA to obtain a row address decode signal. The row decoder 14 then selects one of the word lines WL1 to WLm based on the row address decode signal.

The column decoder 15 decodes the column address signal CA to obtain column selection signals CSL1 to CSLn. The column select signals CSL1 to CSLn are supplied to the column select circuits 19 and 20.

The bit lines BL1 to BLn are connected to the write circuit 16 and the read circuit 18 through the column select circuit 19. The column select circuit 19 connects the bit line BL selected based on the column select signal CSL to the write circuit 16 (or the read circuit 18). The column select circuit 19 includes switch elements 19-1 to 19-n corresponding to bit lines BL1 to BLn. The switch elements 19-1 to 19-n are formed of, for example, N-channel MOSFETs. The column select signals CSL1 to CSLn are supplied to the gates of the NMOSFETs 19-1 to 19-n, respectively.

The bit lines / BL1 to / BLn are connected to the write circuit 17 through the column select circuit 20. The column select circuit 20 connects the selected bit line / BL to the write circuit 17 based on the column select signal CSL. The column select circuit 20 includes switch elements 20-1 to 20-n corresponding to bit lines / BL1 to / BLn. The switch elements 20-1 to 20-n are formed of, for example, N-channel MOSFETs. The column select signals CSL1 to CSLn are supplied to the gates of the NMOSFETs 20-1 to 20-n, respectively.

The write circuits 16 and 17 write data to the selected memory cell MC. Specifically, the write circuits 16 and 17 supply the write current in the direction corresponding to the data between the selected bit line BL and / BL.

The read circuit 18 reads data from the selected memory cell MC. Specifically, the read circuit 18 reads data from the selected memory cell MC by detecting a current flowing in the selected bit lines BL and / BL or a voltage between the selected bit lines BL and / BL.

The input / output buffer 13 receives input data DI from the outside. The input data DI is supplied to the recording circuits 16 and 17 as write data. The input / output buffer 13 also receives the read data from the read circuit 18 and outputs the read data to the outside as output data DO.

The control circuit 22 receives various commands (including write commands, read commands and erase commands) from the outside. The control circuit 22 controls each circuit of the semiconductor memory device 10 in accordance with the command. For example, the control circuit 22 supplies the write signal to the write circuits 16 and 17 in response to the write command.

The setting circuit 21 receives an on / off signal from the outside. The on / off signal is a signal indicating whether the power supply of the system on which the semiconductor memory device 10 is mounted is on or off. The on / off signal is high when the power supply of the system is on, and low when the power supply is off. The setting circuit 21 generates the switching signal DPOL based on the on / off signal.

The semiconductor memory device 10 of this embodiment operates in response to an on / off signal indicating whether the system is on or off. That is, the semiconductor memory device 10 is used for a non-all-night operation type (discontinuous operation type) system that is repeatedly set to on and off.

4 is a timing diagram for illustrating the operation of the setting circuit 21. The setting circuit 21 switches the high and low levels of the switching signal DPOL by using the rising edge of the on / off signal as a trigger (that is, when the system is turned on). As shown in Fig. 4, the setting circuit 21 makes the switching signal DPOL high at the first rising edge of the on / off signal. The setting circuit 21 then turns the switching signal DPOL low on the next rising edge of the on / off signal. Subsequently, the setting circuit 21 repeatedly performs the same operation. The switching signal DPOL supplies the write circuits 16 and 17 and the read circuit 18.

Next, the operation of the semiconductor memory device 10 configured as described above will be described. The magnetoresistive element 30 of this embodiment is a spin transfer torque recording type magnetoresistive element. Therefore, when data is written to the magnetoresistive element 30, current flows in both directions in a direction perpendicular to the film surface (or laminated surface) of the magnetoresistive element 30. The operation of writing data to the magnetoresistive element 30 will be described below.

First, the memory cell MC in which data is written is selected by selecting the bit line pairs BL, / BL and word line WL. Then, the write circuits 16 and 17 apply a voltage between the selected bit lines BL and / BL so that the write current corresponding to the data flows to the magnetoresistive element 30 included in the selected memory cell MC.

That is, when electrons from the pinned layer 33 (that is, electrons moving from the pinned layer 33 to the recording layer 35) are supplied, electrons having spins polarized in the same direction as the magnetization direction of the pinned layer 33 It is injected into the recording layer 35. In this case, the magnetization direction of the recording layer 35 is set in the same direction as the magnetization direction of the fixed layer 33. As a result, the magnetization directions of the pinned layer 33 and the recording layer 35 are set in a parallel arrangement. The resistance of the magnetoresistive element 30 is minimum when the parallel arrangement is set (low-resistance state is set).

On the other hand, when electrons from the recording layer 35 (that is, electrons moving from the recording layer 35 to the fixed layer 33) are supplied, they are reflected from the fixed layer 33 and are opposite to the magnetization direction of the fixed layer 33. Electrons having spins polarized in the direction are injected into the recording layer 35. In this case, the magnetization direction of the recording layer 35 is set in the direction opposite to the magnetization direction of the fixed layer 33. As a result, the magnetization directions of the pinned layer 33 and the recording layer 35 are set in an anti-parallel arrangement. The resistance of the magnetoresistive element 30 is maximum when the anti-parallel arrangement is set (high-resistance state is set).

The operation of reading data from the magnetoresistive element 30 is performed as follows. The selection operation of the memory cell MC is the same as the operation described in the case of the write operation. The read current is supplied by the read circuit 18 to the magnetoresistive element 30. The read current is set to a value such that the magnetization direction of the recording layer 35 is not inverted (that is, a value lower than the write current). The data stored in the magnetoresistive element 30 can be read by detecting a change in resistance of the magnetoresistive element 30 at this point of time through a sense amplifier or the like included in the read circuit 18.

The write circuits 16 and 17 are " 0 " and " 1 " depending on the low-resistance state and the high-resistance state of the magnetoresistive element 30 and the state (high or low) of the switching signal DPOL. "0 " and " 1 " data items according to the state (high or low) of the switching signal DPOL switching the data items, or assigning the low-resistance state and the high-resistance state of the magnetoresistive element 30. Switch to That is, the write circuits 16 and 17 supply the write current to the magnetoresistive element 30 so that when the switching signal DPOL is low, the low-resistance state is set to "0" data and the high-resistance state is "." Set to 1 "data. In addition, the write circuits 16 and 17 supply the write current to the magnetoresistive element 30 to give an inverted allocation, i.e., when the switching signal DPOL is high, the low-resistance state is set to "1" data. Set the high-resistance state to "0" data.

Similarly, the readout circuit 18 has "0" and "1" data items according to the assignment of the low-resistance state and the high-resistance state of the magnetoresistive element 30 and the state (high or low) of the switching signal DPOL. Switch. That is, the readout circuit 18 outputs the read data so that when the switching signal DPOL is low, the low-resistance state is set to "0" data and the high-resistance state is set to "1" data. In addition, the read circuit 18 outputs the read data and gives an inverted allocation, that is, when the switching signal DPOL is high, the low-resistance state is set to "1" data and the high-resistance state is " Set to 0 "data.

The setting circuit 21 includes a memory circuit 21A that stores the assignment of " 0 " data / " 1 " data and low-resistance state / high-resistance state (i.e., state of the switching signal DPOL). In a system that can be backed up through a battery, but can use the same nonvolatile memory elements as the memory cells, for example in a completely powered off system, the memory circuit 21A is used for static random access memory (SRAM). It may be a latch circuit composed of a MOSFET. In other cases it can be formed without adding an extra manufacturing process.

More specific embodiments of the first embodiment are described below.

Example 1-1

Embodiment 1-1 shows an example in which the semiconductor memory device 10 is used as a volatile RAM circuit.

First, at the start of the system (at the rising edge of the on / off signal), the write circuits 16 and 17 write the " 1 " or " 0 " data for every bit of the memory cell array 11 so as to write the memory cell array. Initialize (11).

Specifically, the control circuit 22 detects the start of the system by receiving an on / off signal. Next, the control circuit 22 supplies a write signal to the write circuits 16 and 17. Subsequently, the control circuit 22 sequentially supplies the row address signal RAC to the row decoder 14 and the column select signal CSL to the column select circuit 19 to sequentially select the memory cells MC. The selection operation may be performed to simultaneously select the plurality of memory cells MC (for each column unit or each row unit). The write circuits 16 and 17 then write erase data to the selected memory cell MC. Thus, "1" data or "0" data can be written for every bit of the memory cell array 11 at initialization.

The write circuits 16 and 17 then perform a data write operation based on the switching signal DPOL. Similarly, the read circuit 18 performs a data read operation based on the switching signal DPOL.

Example 1-2

Embodiment 1-2 shows an example in which the semiconductor memory device 10 is used as a nonvolatile RAM circuit. 5 is a block diagram showing the configuration of the semiconductor memory device 10 according to the embodiment 1-2.

The semiconductor memory device 10 includes a latch circuit 23. The latch circuit 23 latches the read data read out from the memory cell array 11 by the read circuit 18 and transfers the latched data to the write circuits 16 and 17.

In this embodiment, a rewrite operation of reading a data item from all bits of the memory cell array 11 and rewriting (rewriting) the inverted data item obtained by inverting the read data item into the memory cell array 11. Initialization operation is performed at system startup.

First, the control circuit 22 detects the start of the system by receiving an on / off signal. Next, the control circuit 22 supplies the row address signal RAC to the row decoder 14 and the column select signal CSL to the column select circuits 19 and 20 to sequentially supply the memory cells MC. Choose. The selection operation may be performed to simultaneously select the plurality of memory cells MC (eg, for each column unit or each row unit). The read circuit 18 then reads data from the selected memory cell MC. Thus, the read data is supplied to the latch circuit 23 and latched.

The read data latched in the latch circuit 23 is then supplied to the write circuits 16 and 17. The control circuit 22 then selects one of the same memory cells MC as the memory cell in which the read operation is performed. Next, the write circuits 16 and 17 write the inverted data obtained by inverting the read data into the selected memory cell MC. The above operation is performed repeatedly until the data item of every bit is inverted.

After all data items of the memory cell array 11 are inverted, the write circuits 16 and 17 perform a data write operation based on the switching signal DPOL. Similarly, the read circuit 18 performs a data read operation based on the switching signal DPOL.

Example 1-3

Example 1-3 does not perform the initialization operation (rewrite operation) described in Example 1-2 at the start of the system. The inverted data item is rewritten in a plurality of memory cell columns connected to the bit line when the bit line to which the memory cell MC for which data writing or reading operation is performed is connected is first accessed. Therefore, the initialization operation described in Embodiments 1 and 2 can be omitted, and accordingly, the start cycle of the semiconductor memory device 10 can be reduced.

6 is a circuit diagram showing the configuration of the memory cell array 11 according to the embodiments 1-3. The block diagram of the semiconductor memory device 10 is the same as the block diagram of FIG. 5.

The memory cell array 11 includes a flag cell string 37, and the flag cell string 37 is configured by arranging n flag cells FC in a row direction. Each flag cell FC has the same configuration as that of the memory cell MC and includes the magnetoresistive element 30 and the selection transistor 31. The n flag cell FC is connected to the bit line pairs BL1 to BLn and / BL1 to / BLn, respectively. In addition, the n flag cell FC is connected to the common word line FWL. The word line FWL is connected to the row decoder 14.

The operation of the semiconductor memory device 10 configured as described above will be described. For example, assume that "0" data is written in all the flag cells FC. First, when the system starts up, the on / off signal is high. The setting circuit 21 receives the on / off signal and generates a high switching signal DPOL. Thus, the read circuit 18 outputs the read data to set the low-resistance state to "1" data and the high-resistance state to "0" data. In this step, the initialization operation (rewrite operation) is not performed.

Next, the column decoder 15 selects the bit line pairs BL and / BL connected to the memory cell MC in which the write or read operation is performed. The control circuit 22 then selects the word line FWL by using the row address signal RAC. Therefore, the read circuit 18 reads the data of the flag cell FC connected to the selected bit line. At this time, the data of the flag cell FC is read as " 1 " data because the switching signal DPOL is high.

The control circuit 22 confirms the data read from the flag cell FC. If the data is "1" data, the rewrite operation of the inverted data is performed. If the data is "0" data, the rewrite operation of the inverted data is not performed. In this embodiment, since the data items of all the flag cells FC are read out as "1" data, the rewrite operation is performed by the column (bit line) corresponding to the flag cell FC when the flag cell FC is first accessed. Perform on.

That is, the control circuit 22 sequentially selects the memory cells MC in the selected column by supplying the row address signal RAC to the row decoder 14. The read circuit 18 then reads data from the selected memory cell MC. The read data is transferred to the latch circuit 23 and latched.

The read data latched in the latch circuit 23 is then supplied to the write circuits 16 and 17. Next, the control circuit 22 sequentially selects the memory cells MC in the selected column. The write circuits 16 and 17 then sequentially write the inverted data items obtained by inverting the read data items into the selected memory cell MC.

In the rewrite operation, the data of the flag cell FC is also inverted (replaced by "0" data). Therefore, when the on / off signal goes high again and the switching signal DPOL goes low, the data of the flag cell FC is read as "1" data. Therefore, when each flag cell FC is first accessed, a rewrite operation is performed on the column (bit line) corresponding to the flag cell FC.

After the data items of one column of the memory cell array 11 are inverted, the write circuits 16 and 17 perform a data write operation on the column based on the switching signal DPOL. Similarly, the read circuit 18 performs a data read operation based on the switching signal DPOL.

Embodiments 1-3 describe a system in which flag bits are arranged for each bit line, but in some cases, flag bits may be arranged in word line units or block units. In this case, the operation principle is the same as the operation principle when the flag bit is arranged for each bit line.

As described above, according to the first embodiment, since the low-resistance state and the high-resistance state of the magnetoresistive element 30 are switched for a predetermined period, respectively, the magnetoresistive element for storing the same data for a long time ( The stress biased in 30 can be prevented from being applied. That is, even when the magnetoresistive element 30 normally stores the same data for a long time, the inverted data can be stored after the preset period expires by applying this embodiment. As a result, the service life of the memory cell MC can be extended by suppressing the influence of an uneven application environment.

Further, this embodiment can be applied to volatile RAM and nonvolatile RAM, and thus can be used for memory for various applications.

Second Embodiment

The semiconductor memory device 10 according to the second embodiment is used in a non-all-night operation type (discontinuous operation type) system that repeatedly sets on and off. Further, the second embodiment includes a timer circuit for generating a clock, and the level of the first switching signal DPOLX output from the setting circuit 21 is changed for each period of the clock. In addition, the state of the first switching signal DPOLX on the rising edge of the on / off signal is used as the second switching signal DPOL, and the data write operation and the read operation are based on the second switching signal DPOL. To perform.

7 is a block diagram showing a configuration of a semiconductor memory device 10 according to the second embodiment of the present invention. The semiconductor memory device 10 includes a timer circuit 24 and a register 25.

The timer circuit 24 generates a pulse for each preset period. The timer circuit 24 supplies the clock CLK having a plurality of pulse strings to the setting circuit 21. The setting circuit 21 switches the high and low levels of the first switching signal DPOLX by using the rising edge of the clock CLK as a trigger.

8 is a timing diagram for illustrating the operation of the timer circuit 24 and the setting circuit 21. The setting circuit 21 makes the first switching signal DPOLX high on the first rising edge of the clock CLK. The setting circuit 21 then turns the first switching signal DPOLX low on the next rising edge of the clock CLK. Subsequently, the setting circuit 21 repeatedly performs the above-described operation. The first switching signal DPOLX is supplied to the register 25.

It is common to assume that the service life of the insulating film used for the semiconductor memory device is 10 years in actual application environment. Therefore, it is important to set the period of the clock CLK shorter than the period. However, in this embodiment, since the semiconductor memory device is assumed to be used in a non-all-night operation type system, it is assumed that the semiconductor memory device is triggered daily on average, and that the clock period is set to be substantially equal to or slightly longer than the period. . For example, set the clock CLK period to approximately one day, one week, or one month.

The setting circuit 21 stores the assignment of " 0 " data / " 1 "data and the low-save state / high-save state (i.e., the state of the switching signal DPOLX) or the " 0 " data / " 1 " data. And a memory circuit 21A for storing the allocation of? In the low-store state / high-store state. For a system that can be backed up with a battery, but that can use the same nonvolatile memory elements as the memory cell elements, for example, in a fully powered off system, the memory circuit 21A may be a latch circuit such as an SRAM with a MOSFET. It may be. In other cases it can be formed without adding an extra manufacturing process.

The register 25 holds the first switching signal DPOLX. In addition, the register 25 receives an on / off signal from the outside indicating the on state or the off state of the system. The register 25 uses the rising edge of the on / off signal as a trigger to output the state of the first switching signal DPOLX as the second switching signal DPOL at this point in time. The second switching signal DPOL supplies the write circuits 16 and 17 and the read circuit 18.

The data write operation and read operation using the second switching signal DPOL and the on / off signal are the same as those in the first embodiment.

More specific embodiments of the second embodiment are described below.

Example 2-1

Embodiment 2-1 shows an example in which the semiconductor memory device 10 is used as a volatile RAM circuit. That is, Example 2-1 is obtained by applying the second embodiment to Example 1-1.

First, at the start of the system (at the rising edge of the on / off signal), the write circuits 16 and 17 write the " 1 " or " 0 " data for every bit of the memory cell array 11 so as to write the memory cell array. Initialize (11).

Specifically, the control circuit 22 detects the start of the system by receiving an on / off signal. Next, the control circuit 22 supplies a write signal to the write circuits 16 and 17. Subsequently, the control circuit 22 sequentially supplies the row address signal RAC to the row decoder 14 and the column select signal CSL to the column select signal 19 to sequentially select the memory cells MC. The selection operation may be performed to simultaneously select the plurality of memory cells MC (for each column unit or each row unit). The write circuits 16 and 17 then write erase data to the selected memory cell MC. Thus, "1" data or "0" data can be written for every bit of the memory cell array 11 at initialization.

In addition, the register 25 outputs the switching signal DPOL by using the first switching signal DPOLX and the on / off signal. The write circuits 16 and 17 then perform a data write operation based on the switching signal DPOL. Similarly, the read circuit 18 performs a data read operation based on the switching signal DPOL.

Example 2-2

Embodiment 2-2 shows an example in which the semiconductor memory device 10 is used as a nonvolatile RAM circuit. That is, Example 2-2 is obtained by applying the second embodiment to Example 1-2. 9 is a block diagram showing the structure of the semiconductor memory device 10 according to the embodiment 2-2.

The semiconductor memory device 10 includes a latch circuit 23. The latch circuit 23 latches the read data read out from the memory cell array 11 by the read circuit 18 and transfers the latched data to the write circuits 16 and 17.

In this embodiment, the operation of reading the data item from all the bits of the memory cell array 11 and rewriting the inverted data item obtained by inverting the read data item into the memory cell array 11 is performed at the start of the system. do. The rewrite operation (initialization operation) is the same as that in the embodiment 1-2.

The register 25 outputs the second switching signal DPOL by using the first switching signal DPOLX and the on / off signal. After all data items of the memory cell array 11 are inverted, the write circuits 16 and 17 perform a data write operation based on the switching signal DPOL. Similarly, the read circuit 18 performs a data read operation based on the switching signal DPOL.

Example 2-3

Example 2-3 is obtained by applying the second example to Example 1-3. That is, the embodiment 2-3 does not perform the initialization operation (rewrite operation) described in the embodiment 2-2 at the start of the system. The inverted data item is rewritten in a plurality of memory cell columns connected to the bit line when the bit line to which the memory cell MC in which the data write operation or the read operation is performed is connected is first accessed. The configuration of the memory cell array 11 is the same as that of FIG. 6, and the memory cell array 11 includes n flag cells FC corresponding to bit line pairs BL1 to BLn and / BL1 to / BLn.

The operation of rewriting the inverted data by using the latch circuit 23 is the same as that in the embodiment 1-3. The write circuits 16 and 17 also perform a data write operation based on the switching signal DPOL from the register 25. Similarly, the read circuit 18 performs a data read operation based on the switching signal DPOL from the register 25.

As described above, in the second embodiment, as in the first embodiment, the service life of the memory cell MC can be extended by suppressing the influence of an uneven application environment.

Third Embodiment

The semiconductor memory device 10 of the third embodiment is used in an all-night operation type (continuous operation type) system such as an engineering workstation (EWS) or a general purpose computer for long time large scale system control. Therefore, in the semiconductor memory device 10 of the third embodiment, the switching signal DPOL is generated by using the clock CLK generated from the timer circuit without using the on / off signal indicating the on state or the off state of the system.

10 is a block diagram showing a configuration of a semiconductor memory device 10 according to the third embodiment of the present invention. The semiconductor memory device 10 includes a timer circuit 24.

The timer circuit 24 generates a pulse for each preset period. The timer circuit 24 supplies the clock CLK including the plurality of pulse strings to the setting circuit 21. The setting circuit 21 switches the high and low levels of the switching signal DPOL by using the rising edge of the clock CLK as a trigger.

It is common to assume that the service life of the insulating film used for the semiconductor memory device 10 is 10 years in the actual application environment. Therefore, it is important to set the period of the clock CLK to be sufficiently shorter than the period. However, since the present embodiment assumes use in an all-night operation type system, a time loss of the system occurs when the period is set too short. Thus, for example, the period of the clock CLK is set to approximately one day, one week, or one month.

11 is a timing diagram for illustrating the operation of the timer circuit 24 and the setting circuit 21. The setting circuit 21 makes the switching signal DPOL high on the first rising edge of the clock CLK. The setting circuit 21 then turns the switching signal DPOL low on the next rising edge of the clock CLK. Subsequently, the setting circuit 21 repeatedly performs the above-described operation. The switching signal DPOL supplies the write circuits 16 and 17 and the read circuit 18.

The write circuits 16 and 17 are "0" and "1" data items according to the assignment of the low-resistance state and the high-resistance state of the magnetoresistive element 30 and the state (high or low) of the switching signal DPOL. Switch. That is, the write circuits 16 and 17 supply the write current to the magnetoresistive element 30 so that when the switching signal DPOL is low, the low-resistance state is set to "0" data and the high-resistance state is "." Set to 1 "data. In addition, the write circuits 16 and 17 supply the write current to the magnetoresistive element 30 to give an inverted allocation, i.e., when the switching signal DPOL is high, the low-resistance state is set to "1" data. Set the high-resistance state to "0" data.

Similarly, the readout circuit 18 has "0" and "1" data items according to the assignment of the low-resistance state and the high-resistance state of the magnetoresistive element 30 and the state (high or low) of the switching signal DPOL. Switch the assignment of. That is, the read circuit 18 outputs the read data so that when the switching signal DPOL is low, the low-save state is set to "0" data and the high-save state is set to "1" data. In addition, the read circuit 18 outputs the read data and gives an inverted allocation, that is, when the switching signal DPOL is high, the low-resistance state is set to "1" data and the high-resistance state is " Set to 0 "data.

More specific embodiments of the third embodiment are described below.

Example 3-1

Example 3-1 shows an example in which the semiconductor memory device 10 is used as a nonvolatile RAM circuit. That is, Example 3-1 is obtained by applying the third example to Example 1-2. The configuration of the semiconductor memory device 10 according to the embodiment 3-1 is the same as that of FIG. 10.

As shown in FIG. 10, the semiconductor memory device 10 includes a latch circuit 23. The latch circuit 23 latches the read data read out from the memory cell array 11 by the read circuit 18 and transfers the latched data to the write circuits 16 and 17.

In this embodiment, the rewrite operation (initialization operation) of reading the data item from all the bits of the memory cell array 11 and rewriting the inverted data item obtained by inverting the read data item into the memory cell array 11 is performed. Performing during the first period when the switching signal DPOL is inverted.

When the switching signal DPOL is inverted, the control circuit 22 supplies the row address signal RAC to the row decoder 14 and the column select signal CSL to the column select circuits 19 and 20 to store the memory. Select cells MC sequentially. The selection operation may be performed to simultaneously select the plurality of memory cells MC (for each column unit or each row unit). The read circuit 18 then reads data from the selected memory cell MC. Thus, the read data is supplied to the latch circuit 23 and latched.

The read data latched in the latch circuit 23 is then supplied to the write circuits 16 and 17. Then, the control circuit 22 selects the same memory cell MC as the memory cell in which the read operation is performed. The write circuits 16 and 17 then write the inverted data obtained by inverting the read data into the selected memory cell MC. The above operation is performed repeatedly until the data item of every bit is inverted.

After all data items of the memory cell array 11 are inverted, the write circuits 16 and 17 perform a data write operation based on the switching signal DPOL. Similarly, the read circuit 18 performs a data read operation based on the switching signal DPOL.

Example 3-2

Example 3-2 is obtained by applying the third embodiment to Examples 1-3. That is, in Example 3-2, the inverted data item includes a plurality of memory cell columns connected to the bit line when the bit line to which the memory cell MC in which the data write operation or the data read operation is performed is connected is first accessed. Is written to, the rewrite operation (initialization operation) described in the embodiment 3-1 when the switching signal DPOL is inverted is not performed. The configuration of the memory cell array 11 is the same as that of FIG. 6, and the memory cell array 11 includes n flag cells FC corresponding to bit line pairs BL1 to BLn and / BL1 to / BLn.

The operation of the semiconductor memory device 10 configured as described above will be described. For example, assume that "0" data is recorded in all the flag cells MC. First, when the clock CLK is generated from the timer circuit 24, the setting circuit 21 inverts the switching signal DPOL in response to the clock CLK. In this embodiment, for example, it is assumed that the switching signal DPOL is high. Thus, the read circuit 18 outputs the read data to set the low-resistance state to "1" data and the high-resistance state to "0" data. In this step, the initialization operation is not performed.

Next, the column decoder 15 selects the bit line pair BL and / BL connected to the memory cell MC in which the write operation or the read operation is performed. The control circuit 22 then selects the word line FWL by using the row address signal RAC. Therefore, the read circuit 18 reads the data of the flag cell FC connected to the selected bit line. At this time, the data of the flag cell FC is read as " 1 " data because the switching signal DPOL is high.

The control circuit 22 confirms the data read from the flag cell FC. The rewrite operation of the inverted data is performed when the data is "1" data, and the rewrite operation of the inverted data is not performed when the data is "0" data. In this embodiment, the data items of all the flag cells FC are read as "1" data, so that the rewrite operation is performed by the column (bit line) corresponding to the flag cells FC when each flag cell FC is first accessed. ).

That is, the control circuit 22 sequentially selects the memory cells MC in the selected column by supplying the row address signal RAC to the row decoder 14. The read circuit 18 then reads data from the selected memory cell MC. The read data is transferred to the latch circuit 23 and latched.

The read data latched in the latch circuit 23 is then supplied to the write circuits 16 and 17. Next, the control circuit 22 sequentially selects the memory cells MC in the selected column. The write circuits 16 and 17 then write the inverted data items obtained by inverting the read data items to the selected memory cell MC.

In the rewrite operation, the data of the flag cell FC is inverted (replaced by "0" data). Therefore, when the switching signal DPOL is low, the data of the flag cell FC is read as "1" data. Therefore, when each flag cell FC is first accessed, a rewrite operation is performed on the column (bit line) corresponding to the flag cell FC.

After the data items of one column of the memory cell array 11 are inverted, the write circuits 16 and 17 perform a data write operation on the column based on the switching signal DPOL. Similarly, the read circuit 18 performs a data read operation based on the switching signal DPOL.

As described above, according to the third embodiment, as in the first embodiment, the service life of the memory cell MC is uneven when applying this embodiment to an all-night operation type (continuous operation type) system. It can extend by suppressing the influence of.

[Example 4]

The magnetization direction of the recording layer 35 in the magnetoresistive element 30 is reversed by supplying the bidirectional write current Iw. The data is identified according to the resistance change of the magnetoresistive element 30 which changes based on the magnetization arrangement of the pinned layer 33 and the recording layer 35. 12 is a diagram showing an ideal I-R curve of the magnetoresistive element 30. The abscissa represents the write current Iw, and the ordinate represents the resistance of the magnetoresistive element 30. Rap represents the resistance of the magnetoresistive element 30 in which the magnetization of the pinned layer 33 and the recording layer 35 is set in the anti-parallel state (high-resistance state), and Rp represents the pinned layer 33 and the recording layer 35. ) Represents the resistance of the magnetoresistive element 30 in which the magnetization is set to a parallel state (low-resistance state). Inega represents the maximum value of the negative write current Iw, and Iposi represents the maximum value of the positive write current Iw. The absolute value of the maximum value Iposi is greater than the absolute value of the maximum value Inega.

The I-R curve of the magnetoresistive element 30 is ideally an I-R hysteresis loop with an inverted current threshold symmetric about the Y axis shown in FIG. In reality, however, as shown in FIG. 13, the magnetic properties shift due to the film thickness distribution and the defects of the magnetoresistive element 30, and the inverted current becomes substantially asymmetrical with respect to the positive and negative sides in the same case. In addition, in consideration of the memory cell MC formed of the magnetoresistive element 30 and the selection transistor 31 connected in series, the identifiable conductance of the nonlinear element is a select transistor 31 formed of a MOSFET. ) Is a nonlinear element, and varies depending on whether or not the potential on the source side is set to the electrically floating state. As a result, the maximum value of the write current Iw changes in accordance with the polarity of the voltage applied to the memory cell MC.

When the hysteresis loop is shifted with respect to the Y axis as shown in Fig. 13, the direction of the current passing through the memory cell MC may be a bit line, a word line, a predetermined number of memory cells MC or a memory cell array ( 11) is reversed. FIG. 14 is a diagram showing an I-R curve obtained when the write current flowing through the magnetoresistive element 30 having the I-R curve shown in FIG. 13 is inverted (that is, after a trimming operation).

As shown in Fig. 14, the magnetoresistive element 30 can have a large operating margin by changing the direction of the write current Iw. As a determination criterion for determining the direction in which the write current Iw flows, for example, data indicating the direction in which the current flows in writing is stored in the flag cell FC, and the direction of the current is based on the data of the flag cell FC. Decide by

FIG. 15 is a block diagram showing a configuration of a semiconductor memory device 10 according to the fourth embodiment of the present invention. The semiconductor memory device 10 includes a memory cell array 11, an address buffer 12, an input / output buffer 13, a row decoder 14, a column decoder 15, a write circuit 16 and 17, a read circuit. 18, column selection circuits 19 and 20 and control circuit 22.

The configuration of the memory cell array 11 is the same as that of FIG. The memory cell array 11 includes a flag cell column 37 in addition to the m × n memory cells MC arranged in a matrix form. The flag cell column 37 is composed of n flag cells FC arranged in a row direction. That is, in the present embodiment, the case where the allocation of "0" and "1" data items is switched in bit line units (column units) will be described. However, the present invention is not limited to this case, but a block unit or memory cell array in which the allocation of the "0" and "1" data items is formed in word line units (row units), and in a predetermined number of memory cells MC ( The whole part of 11) may be switched in units.

Each flag cell FC stores "0" data or "1" data depending on the polarity of the write current Iw. For example, when the data of the flag cell FC is "0", the write circuits 16 and 17 supply the write current Iw to the magnetoresistive element 30 to change the low-resistance state to "0" data. And set the high-save state to "1" data. On the other hand, when the data of the flag cell FC is "1", the write circuits 16 and 17 supply the write current Iw to the magnetoresistive element 30 to give an inverted allocation, i.e., low-resistance. Set the state to "1" data and the high-resistance state to "0" data.

The read circuit 18 switches the "0" and "1" data items according to the assignment of the low-resistance state and the high-resistance state of the magnetoresistive element 30 and the data of the flag cell FC. That is, the readout circuit 18 outputs the read data, and when the data of the flag cell FC is "0", sets the low-resistance state to "0" data and the high-resistance state to "1" data. Set it. Further, the read circuit 18 outputs the read data and gives an inverted allocation, that is, when the data of the flag cell FC is "1", the low-resistance state is set to "1" data and the high- Set the resistance state to "0" data.

The operation of the semiconductor memory device 10 configured as described above will be described. The characteristics of the memory cell are measured before shipment time, and in order to increase the operating margin of the magnetoresistive element 30 based on the measurement result, " 1 " data or " 0 " data is recorded and assigned to the flag cell FC. To give.

First, the data recording operation will be described. When the control circuit 22 receives the write command and the address buffer 12 receives the address signal ADD, the semiconductor memory device 10 starts the data write operation. At the start, the column decoder 15 selects the bit line pair BL, / BL connected to the memory cell MC in which the write operation is performed. The control circuit 22 then selects the word line FWL by using the row address signal RAC. As a result, the read circuit 18 reads out data of the flag cell FC connected to the selected bit line. Data of the flag cell FC is supplied to the write circuits 16 and 17.

Next, the row decoder 14 selects the word line WL connected to the memory cell MC in which the write operation is performed. Then, the write circuits 16 and 17 determine the allocation based on the data of the flag cell FC, and assign the write current Iw corresponding to the write data to the bit line pair BL, / BL selected based on the allocation. Supply. Therefore, desired data is written to the memory cell MC in which the write operation is performed.

Next, the data read operation will be described. When the control circuit 22 receives the read command and the address buffer 12 receives the address signal ADD, the semiconductor memory device 10 starts a data read operation. First, the column decoder 15 selects the bit line pairs BL and / BL connected to the memory cell MC in which the read operation is performed. The control circuit 22 then selects the word line FWL by using the row address signal RAC. As a result, the read circuit 18 reads out data of the flag cell FC connected to the selected bit line.

Next, the row decoder 14 selects the word line WL connected to the memory cell MC in which the read operation is performed. Then, the read circuit 18 determines the allocation based on the data of the flag cell FC, and outputs the read data based on the allocation. Therefore, desired data is read from the memory cell MC in which the read operation is performed.

As described above, according to the fourth embodiment, the assignment of the low-resistance state and the high-resistance state of the magnetoresistive element 30 and the "0" and "1" data items take into account the characteristics of the memory cell MC. This can be switched. Therefore, the memory cell MC may have a large operating margin. As a result, the number of chips that can be reduced can be increased by performing the trimming operation, and the manufacturing yield of the chips can be improved, and thus the manufacturing cost can be reduced.

[Example 5]

In the fifth embodiment, the semiconductor memory device 10 includes a plurality of memory cell arrays 11 and includes a measurement circuit having measurement memory cells (memory cells to be measured) having the same configuration as the memory cells MC ( 40 is disposed near each memory cell array 11. Then, the characteristics of the measurement memory cell are measured, and the measurement results are reflected in the trimming operation to perform an optimal trimming operation.

16 is a schematic diagram showing the configuration of a semiconductor memory device 10 according to the fifth embodiment of the present invention. The semiconductor memory device 10 includes a plurality of memory cell arrays 11 (in this embodiment, twelve memory cell arrays 11-1 to 11-12 are shown as one example). The configuration of each memory cell array 11 is the same as that of FIG. In addition, the peripheral circuit of the memory cell array 11 is the same as the peripheral circuit of FIG.

The semiconductor memory device 10 includes a plurality of measurement circuits 40 used to obtain trimming data. In this embodiment, the eleven measuring circuits 40 are shown as an example. The plurality of measurement circuits 40 are uniformly disposed between and around the plurality of memory cell arrays 11.

Each measuring circuit 40 measures an object and includes a plurality of measuring memory cells MC having the same configuration as that of the memory cells MC of the memory cell array 11. For example, in the case of a 1-Gbit chip (semiconductor memory device 10), one memory cell array 11 includes approximately tens of Mbits to several hundred Mbits, and one measurement circuit 40 has tens of bits to several kbits. It is formed as a small circuit. The measurement circuit 40 is a simple circuit that includes a column decoder, a row decoder and electrode pads in addition to a small array of memory cells.

The characteristics of the bit that cannot be evaluated by the normal use of the memory cell array 11 can be obtained by the measuring circuit 40, and the entire trim portion of the chip can be subjected to the optimum trimming operation described in the fourth embodiment. At least one measurement circuit 40 may be mounted on each chip, and in order to obtain more specific characteristics of the memory cell MC, a plurality of measurement circuits may be arranged on the chip as shown in FIG. 16.

17 is an equivalent circuit diagram showing the configuration of the measurement circuit 40 shown in FIG. The measurement circuit 40 includes a memory cell array 41. The memory cell array 41 includes, for example, 16 (4 × 4) measurement memory cells MC. Each memory cell MC shown in FIG. 17 has the same structure as that of the memory cell MC of the memory cell array 11.

Four bit lines BL1 to BL4 extending in the column direction are arranged in the memory cell array 41. In addition, four bit lines / BL1 to / BL4 extending in the column direction are arranged in the memory cell array 41. In addition, four word lines WL1 to WL4 extending in the row direction are disposed in the memory cell array 41. The connection relationship between the bit line pair BL, / BL, the word line WL, and the memory cell MC is the same as that of FIG.

The characteristics of the 16-bit memory cell MC are obtained by the memory cell array 41. For this purpose, for example, a terminal (not shown) is connected to the bit line pair BL, / BL and word line WL. The characteristics of the memory cell array 41 are measured by contacting the measurement probes with the terminals and supplying a write current to each memory cell MC. Then, the semiconductor memory device 10 performs the same trimming operation as in the fourth embodiment by setting data of the flag cell FC based on the measurement result.

18 is a block diagram illustrating another configuration example of the measurement circuit 40. The measurement circuit 40 includes a row decoder 42, a column decoder 43, a write circuit 44 and 45, a read circuit 46, and a column select circuit 47 and 48 in addition to the memory cell array 41. . That is, as in the case of FIG. 1 and the like, the measurement circuit 40 includes peripheral circuits for performing data writing and reading operations.

The measurement probe selectively contacts one of the terminals respectively connected to the row decoder 42 and the column decoder 43 to directly supply the address signal ADD to the decoders. The low decoder 42 selects one of the word lines WL1 to WL4 according to the address signal ADD. The column decoder 43 decodes the address signal ADD to obtain column select signals CSL1 to CSL4. The column select signals CSL1 to CSL4 are supplied to the column select circuits 47 and 48.

The bit lines BL1 to BL4 are connected to the write circuit 44 and the read circuit 46 through the column select circuit 47. The column select circuit 47 connects the selected bit line BL to the write circuit 44 (or the write circuit 46) in accordance with the column select signal CSL.

The bit lines / BL1 to / BL4 are connected to the write circuit 45 through the column select circuit 48. The column select circuit 48 connects the selected bit line / BL to the write circuit 45 in accordance with the column select signal CSL.

The write circuits 44 and 45 write data to the selected memory cell MC. Specifically, the write circuits 44 and 45 supply the write current in the direction corresponding to the data to the selected bit line pairs BL and / BL.

The read circuit 46 reads data from the selected memory cell MC. Specifically, the read circuit 46 reads data from the selected memory cell MC by detecting the current (or voltage) of the selected bit line pair BL. The read data is output from the terminal (not shown) connected to the read circuit 46 to the outside.

Using the configuration of FIG. 18, the characteristics of the memory cell array 11 can be measured by inputting the address signal ADD.

As described above, according to the fifth embodiment, the characteristics of the memory cell array 11 differ in the case where the specifications of the memory cell MC differ depending on the position where the memory cell array 11 is disposed. It can measure by using the measuring circuit 40 arrange | positioned near). As a result, the optimum trimming operation can be set by using the measurement result.

In addition, by performing the trimming operation, the number of chips that can be reduced can be increased, and the manufacturing yield of the chips can be improved, and thus the manufacturing cost can be reduced.

[Example 6]

In the first to fifth embodiments, a case where the magnetoresistive element is used as an example of the memory element 30 included in the memory cell MC will be described. However, the present invention is not limited to the above cases and can be used for various types of nonvolatile memories. Other examples of the memory element 30 will be described.

[One. Resistance-change type nonvolatile memory (ReRAM: resistance RAM)]

ReRAM can be used as the semiconductor memory device 10. In this case, a resistance-changing element is used as the memory element 30. 19 is a cross-sectional view showing the structure of the resistance-changing element 30.

The resistance-changing element 30 includes a lower electrode 32, an upper electrode 36, and a recording layer (resistance-changing layer) 50 disposed therebetween. As the recording layer 50, a perovskite oxide film or a binary-series transition metal oxide film is used. A perovskite oxide, it is also possible to provide a _{Pr 0.7 Ca 0.3 MnO 3, SrZrO} 3 / SrTiO 3 or _{Pb (Zr, Ti) O 3} / Zn 0 .4 Cd 0 .6 S. As a binary transition metal oxide film, NiO, TiN, TiO ₂ , HfO ₂ or ZrO ₂ may be provided.

The resistance of the recording layer 50 changes due to the application of voltage pulses. The recording layer 50 has a high-resistance state (reset state) and a low-resistance state (set state), and selectively moves to one of the above states due to the application of a voltage pulse.

That is, the voltage for moving the recording layer 50 from the high-resistance state (reset state) to the low-resistance state (set state) is set as the set voltage Vset, and the recording layer 50 is set to the low-resistance state. Assume that the voltage which causes the transition from the (setting state) to the high-resistance state (reset state) is set as the reset voltage Vreset. Then, the set voltage Vset is set to a positive bias that causes a positive voltage to be applied to the upper electrode 36 relative to the lower electrode 32, and the reset voltage Vreset sets a negative voltage to the lower electrode 32. The negative bias is applied to the upper electrode 36. As a result, the resistance-changing element 30 can store 1-bit data by setting the low-resistance state and the high-resistance state, respectively, corresponding to the "0" and "1" data items.

In the data read operation, a sufficiently low voltage set to approximately 1/1000 to 1/4 times the reset voltage Vreset is supplied to the resistance-changing element 30. The data can then be read by detecting a change in current at this point in time.

[2. Phase-change type nonvolatile memory (PRAM)]

The PRAM can be used as the semiconductor memory device 10. In this case, a phase-change element is used as the memory element 30. The cross section of the phase-change element 30 is the same as the cross section of FIG. 19.

The phase-change element 30 includes a lower electrode 32, an upper electrode 36, and a recording layer (phase-change layer) 50 disposed therebetween. The recording layer 50 phase-changes from the crystalline state to the amorphous state or from the amorphous state to the crystalline state due to the heat generated by passing a current from the upper electrode 36 to the lower electrode 32. The resistance of the recording layer 50 goes low in the crystalline state (low-resistance state) and goes high in the amorphous state (high-resistance state).

As a material of the recording layer 50, a chalcogen compound such as Ge-Sb-Te, In-Sb-Te, Ag-In-Sb-Te or Ge-Sn-Te can be given. The material can be preferably used to obtain a high speed switching operation, repeated recording stability and high reliability.

20 is a circuit diagram showing the configuration of the memory cell MC using the phase-change element. One end of the phase-change element 30 is connected to the bit line BL. The other end of the phase-change element 30 is connected to the drain of the select transistor 31. The source of the select transistor 31 is connected to the bit line / BL. The gate of the select transistor 31 is connected to the word line WL.

Next, an operation of writing data to the memory cell MC constituted by the phase-change element 30 and the selection transistor 31 will be described. First, a pulse-shaped current is applied to the recording layer 50. The recording layer 50 is heated due to the application of a current pulse. The current value of the current pulse is set to set the temperature of the recording layer 50 to be equal to or higher than the crystallization temperature threshold value TH. The crystallization temperature threshold TH is the temperature at which the recording layer changes from the crystalline state to the amorphous state. The temperature of the heated recording layer 50 decreases rapidly after the application of the current pulse due to the application of the current pulse. At this point, the recording layer 50 is set to an amorphous state (high-resistance state).

A small current is applied to the recording layer 50 in which the current value decreases after the pulse-shaped current. In this case, the temperature of the heated recording layer 50 decreases due to the application of the current pulse, but the temperature slowly decreases due to the application of a small current. At this point, the recording layer 50 is set to a crystalline state (low-resistance state).

That is, the recording layer 50 heated due to the application of current is heated to a temperature equal to or higher than the crystallization temperature threshold value TH. Therefore, the recording layer 50 is set to the crystalline state (low-resistance state) when the temperature drop near the crystallization temperature threshold TH is small, and the current to which the temperature drop near the crystallization temperature threshold TH is applied is applied. If large depending on the falling condition of the pulse, it is set to an amorphous state (high-resistance state).

Then, the case where the recording layer 50 is set to the amorphous state (high-resistance state) is defined as "1" data, and the case where the recording layer 50 is set to the crystalline state (low-resistance state) is " By defining as 0 "data, one-bit information can be written in the memory cell MC. The data read operation is the same as that of the magnetoresistive element.

[3. Ferroelectric RAM (FeRAM)]

FeRAM can be used as the semiconductor memory device 10. In this case, the memory cell MC is composed of a ferroelectric capacitor 30 and a selection transistor 31. In other words, the ferroelectric capacitor 30 corresponds to the memory element. The cross section of the ferroelectric capacitor 30 is the same as the cross section of FIG.

The ferroelectric capacitor 30 includes a lower electrode 32, an upper electrode 36, and a ferroelectric film 50 disposed therebetween. As the ferroelectric film 50, PZT [Pb (Zr _X T _{1 -X} ) O ₃ ], SBT (SrBi ₂ Ta ₂ O ₉ ), or the like is used.

A ferroelectric material is a dielectric material that can change the direction of spontaneous polarization by applying a voltage and maintain the direction of polarization even after voltage application is stopped. The ferroelectric capacitor 30 can be used as a memory element by setting two polarized states of the ferroelectric capacitor 30 corresponding to "0" and "1" data items.

FIG. 21 is a circuit diagram showing the configuration of a memory cell MC using ferroelectric capacitors. The drain of the select transistor 31 is connected to the bit line BL. The gate of the select transistor 31 is connected to the word line WL. The source of the select transistor 31 is connected to one electrode of the ferroelectric capacitor 30. The other electrode of the ferroelectric capacitor 30 is connected to the bit line / BL.

When the above-described memory element 30 is used, the same effects as those in the first to fifth embodiments can be obtained.

Other advantages and modifications readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

1 is a block diagram showing the configuration of a semiconductor memory device 10 according to a first embodiment of the present invention.

2 is a circuit diagram showing the configuration of the memory cell array 11;

3 is a cross-sectional view showing the structure of the magnetoresistive element 30.

4 is a timing diagram for illustrating the operation of the setting circuit 21.

5 is a block diagram showing a configuration of a semiconductor memory device 10 according to the embodiment 1-2.

6 is a circuit diagram showing a configuration of the memory cell array 11 according to the embodiments 1-3.

7 is a block diagram showing a configuration of a semiconductor memory device 10 according to the second embodiment of the present invention.

8 is a timing diagram for illustrating the operation of the timer circuit 24 and the setting circuit 21.

9 is a block diagram showing the structure of the semiconductor memory device 10 according to the embodiment 2-2.

10 is a block diagram showing a configuration of a semiconductor memory device 10 according to the third embodiment of the present invention.

11 is a timing diagram for illustrating the operation of the timer circuit 24 and the setting circuit 21.

12 is a diagram showing an ideal I-R curve of the magnetoresistive element 30.

13 is a diagram showing an I-R curve of a magnetoresistive element 30 in which positive and negative inversion currents are asymmetric.

FIG. 14 is a diagram showing an I-R curve obtained after trimming in the magnetoresistive element 30 having the I-R curve shown in FIG.

Fig. 15 is a block diagram showing the construction of a semiconductor memory device 10 according to the fourth embodiment of the present invention.

16 is a schematic diagram showing a configuration of a semiconductor memory device 10 according to the fifth embodiment of the present invention.

17 is an equivalent circuit diagram showing the configuration of the measurement circuit 40 shown in FIG. 16.

18 is a block diagram illustrating another configuration example of the measurement circuit 40.

19 is a sectional view showing the structure of the resistance-changing element 30. FIG.

20 is a circuit diagram showing a configuration of a memory cell MC using a phase-change element.

21 is a circuit diagram showing a configuration of a memory cell MC using ferroelectric capacitors.

<Explanation of symbols for the main parts of the drawings>

10: semiconductor memory device

11: memory cell array

12: address buffer

13: I / O buffer

14: low decoder

15: column decoder

16, 17: recording circuit

18: readout circuit

19, 20: column selection circuit

21: setting circuit

22: control circuit

Claims (20)

As a semiconductor memory device, Memory cell array having a plurality of memory cells set to a low-resistance state / high-resistance state according to "0" data / "1" data Including, And the assignment of the " 0 " data / " 1 " data and the low-resistance state / high-resistance state switches when the power is turned on. The method of claim 1, A write circuit for writing data to the memory cell array in accordance with the assignment; Read circuit for reading data from the memory cell array in accordance with the assignment The semiconductor memory device further comprising. The method of claim 1, And a setting circuit for receiving a first signal indicative of an on / off state of the power supply and generating a second signal for use in switching the allocation based on the first signal. The method of claim 1, And a write circuit for rewriting the data of the memory cell array into inverted data obtained by inverting the data of the memory cell array each time the allocation is switched. The method of claim 4, wherein And a latch circuit for temporarily holding data of the memory cell array upon the rewriting. The method of claim 1, Provide a plurality of memory cell strings, each of the memory cell strings comprising a predetermined number of memory cells of the plurality of memory cells, wherein the " 0 " data / " 1 " data and the low-resistance state / high A plurality of flag cells configured to store allocation information of the resistance state; A write circuit for rewriting the data of the memory cell string into inverted data obtained by inverting the data of the memory cell string based on the allocation information when the memory cell string is first accessed after the allocation is switched The semiconductor memory device further comprising. The method of claim 1, And a memory circuit for storing the allocation. The method of claim 7, wherein And the memory circuit comprises the same memory element as the memory cell. The method of claim 1, The memory cell comprises one of MRAM, ReRAM, PRAM and FeRAM cells. As a semiconductor memory device, A memory cell array having a plurality of memory cells set to a low-resistance state / high-resistance state in accordance with " 0 " data / " 1 "data; Timer circuit for generating pulses at each preset time Including, And the allocation of the " 0 " data / " 1 " data and the low-resistance state / high-resistance state switches each time the pulse is generated. The method of claim 10, A write circuit for writing data to the memory cell array in accordance with the assignment; Read circuit for reading data from the memory cell array in accordance with the assignment The semiconductor memory device further comprising. The method of claim 10, And a setting circuit for generating a signal for use in switching the assignment based on the pulse. The method of claim 10, And a write circuit for rewriting the data of the memory cell array into inverted data obtained by inverting the data of the memory cell array each time the allocation is switched. The method of claim 10, Provide a plurality of memory cell strings, each of the memory cell strings comprising a predetermined number of memory cells of the plurality of memory cells, wherein the " 0 " data / " 1 " data and the low-resistance state / high A plurality of flag cells configured to store allocation information of the resistance state; A write circuit for rewriting the data of the memory cell string into inverted data obtained by inverting the data of the memory cell string based on the allocation information when the memory cell string is first accessed after the allocation is switched The semiconductor memory device further comprising. As a semiconductor memory device, A memory cell array having a plurality of memory cell strings, each memory cell string including a plurality of memory cells set to a low-resistance state / high-resistance state according to " 0 " data / " 1 " , A plurality of flag cells each provided for the memory cell string and configured to store allocation information of the "0" data / "1" data and the low-resistance state / high-resistance state; Including, And a data write and data read operation based on the allocation information. The method of claim 15, A writing circuit for checking allocation information of the flag cells and writing data to a memory cell string corresponding to the flag cells in accordance with the allocation information; A read circuit for checking allocation information of the flag cell and reading data from a memory cell string corresponding to the flag cell in accordance with the allocation information The semiconductor memory device further comprising. The method of claim 15, And the allocation information is set according to a characteristic of the memory cell. As a semiconductor memory device, A memory cell array having a plurality of memory cells selectively set to a low-resistance state and a high-resistance state according to stored data and a plurality of measurement cells each having the same configuration as the memory cell Including, And each of the measurement cells is accessed from the outside, and outputs characteristics of each of the measurement cells to the outside. The method of claim 18, Each of the measurement cells provides for each of a predetermined number of memory cells of the plurality of memory cells. The method of claim 18, And the memory cell and the measurement cell each comprise one of an MRAM, a ReRAM, a PRAM, and a FeRAM cell.

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