KR20090052228A - Fabrication method of poly-crystalline si thin film and transistor adopting the same - Google Patents

Abstract

Disclosed are a polycrystalline silicon thin film and a method of manufacturing a thin film transistor using the same. The disclosed polycrystalline silicon thin film manufacturing method includes forming an active layer of amorphous silicon on a substrate; Applying gold nanorods to the active layer; And irradiating the gold nanorods with light in an infrared region to crystallize the active layer.

Description

Fabrication method of poly-crystalline Si thin film and transistor adopting the same}

The present invention relates to a polycrystalline silicon thin film and a method of manufacturing a thin film transistor using the same, and more particularly, to a polycrystalline silicon thin film capable of large-area crystallization at low temperature and a method of manufacturing a thin film transistor using the same.

Recently, research on LTPS TFT (Low temperature poly-Si) used in organic light emitting display or liquid crystal display has been actively conducted, and research on SOG (System on Glass) which completely eliminated the external driver IC is increasing. By forming an external driver IC together on the display panel itself, a connection line between the panel and the external driver IC is unnecessary, so that the display defect can be reduced and the reliability can be greatly improved. Ultimately, the end goal will be SOG, in which all display systems including controllers as well as data and gate driver ICs are integrated into the panel. To achieve this goal, the mobility of LTPS is greater than 400 cm ² / Vsec and the uniformity must be excellent. However, currently known methods such as Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), and Metal-Induced Lateral Crystallization (MILC) have not yet produced LTPS of desired quality.

Methods of preparing polycrystalline silicon include a method of directly depositing polycrystalline silicon and a method of depositing amorphous silicon and then crystallizing it. In the crystallization method, amorphous silicon is formed on a substrate and then heat-treated by Excimer Laser Annealing (ELA), that is, an excimer laser, to crystallize amorphous silicon and convert it to polycrystalline silicon.

The excimer laser used in the ELA method is a square beam having a length of approximately 1 cm. Heat treatment of a large area of amorphous silicon using such a square beam proceeds sequentially from the divided regions of the checkerboard, which are finely divided into beam size. According to the sequential heat treatment for each region, a portion having a crystal state different from that of other portions occurs even when crystallized or not crystallized at the boundary portion between the unit heat treatment regions. The boundary between the unit heat treatment regions influences the local quality of the polycrystalline silicon. Therefore, in the case of an active matrix liquid crystal display (AMLCD) or an active matrix organic light emission diode display (AMOLED), the operating characteristics of the pixel-by-pixel transistors are not uniform. The difference appears as non-uniform on the screen.

It is an object of the present invention to provide a polycrystalline silicon thin film capable of large-area crystallization at low temperature using light in an infrared region absorbed by gold nanorods and a method of manufacturing a thin film transistor using the same.

According to an exemplary embodiment of the present invention,

Forming an active layer of amorphous silicon on the substrate;

Applying gold nanorods to the active layer;

And crystallizing the active layer by irradiating the gold nanorods with light in an infrared region. A method of manufacturing a polycrystalline silicon thin film is provided.

The gold nanorods may have a ratio of length to diameter of 0.5 to 2.

The method may further include forming a heat transfer layer between the active layer and the gold nanorods.

The heat transfer layer may be Mo, Cr, Au, Ag, AlN.

The wavelength of the light in the infrared region may be 750 ~ 910 nm.

According to another exemplary embodiment of the present invention,

Forming an active layer of amorphous silicon on the substrate;

Applying gold nanorods to the active layer;

Irradiating the gold nanorods with light in an infrared region to crystallize the active layer;

Doping the active layer with impurity ions and then patterning to form a channel region;

A method of manufacturing a thin film transistor is provided, the method comprising: forming a source and a drain positioned at both sides of the channel region.

Hereinafter, a polycrystalline silicon thin film and a method of manufacturing a thin film transistor using the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings refer to like elements, and the size of each element may be exaggerated for clarity.

1 is a process chart of a method of manufacturing a polycrystalline silicon thin film according to an embodiment of the present invention. Referring to FIG. 1A, the active layer 150 is formed of amorphous silicon (a-Si: H) on the substrate 110. The active layer 150 may be formed by the PECVD method using a mixed gas of SiH ₄ and H ₂ as a source gas. The thickness of the amorphous silicon layer may be 500 to 2000 mm 3. The substrate 110 may be formed of a material used as a substrate of a general semiconductor device, and may be formed of silicon, glass, or an organic material. A blocking layer 110a made of an insulating material such as silicon oxide (SiOx) may be formed between the substrate 110 and the active layer 150. The blocking layer 110a may be formed by using plasma enhanced chemical vapor deposition (PECVD) using SiH ₄ , H ₂ , N ₂ O, or the like as a source gas. The blocking layer 110a serves to prevent foreign substances of the substrate 110 from penetrating into the active layer 110a in a subsequent process.

Subsequently, as illustrated in FIG. 1B, a plurality of gold nanorods 160 are coated on the active layer 150. The gold nanorods 160 may be manufactured by a method for manufacturing gold nanorods known in the art, and examples thereof include electrolysis, chemical reduction, and light reduction. In the electrolytic method, an aqueous solution containing a cationic command active agent is electrolyzed under a constant current to elute gold clusters from a gold plate or the like of a positive electrode to generate gold nanorods. As the surfactant, a quaternary ammonium having a structure in which four hydrophobic substituents are bonded to a nitrogen atom is used, and a compound which does not form an autonomous molecular aggregate, for example, tetradodecyl ammonium bromide (TDAB), etc. Is added. The source of gold is a gold cluster which is eluted from the gold plate of the anode, and gold salts such as gold chloride are not used. Ultrasonic irradiation is performed in the electrolysis process, so as to immerse the silver plate in the solution to promote the growth of gold nanorods (Yu, Y. -Y. Yu, S. -S. Chang, C. -L. Lee, C.-L. Lee, CRC Wang, J. Phys. Chem. B, 101, 6661 (1997). In the chemical reduction method, gold nanorods are produced by reducing gold chloride (HAuCl ₄ ) with NaBH ₄ , and the nanorods are obtained by growing these gold nanorods as seed particles in solution. The length of the gold nanorods produced is determined by the ratio of the seed particles and the gelatin chloride added to the growth solution and the growth time (NRJana, L. Gearheart, CJ Murphy, J. Phys. Chem. B, 105, 4065 (2001). ) Reference). The photoreduction method adds chlorochloric acid to the solution which is almost the same as the electrolytic method, and reduces chlorochloric acid by ultraviolet irradiation. Low pressure mercury lamps are used for light irradiation. In the photoreduction method, gold nanorods can be produced without generating seed particles. Control of length is possible by irradiation time (see F.Kim, JHSong, R. Yang, J. Am. Chem. Soc., 124, 14316 (2002)).

The gold nanorods 160 may be coated by applying a solution containing gold nanorods to the surface of the active layer 150 and then drying them. At this time, when the gold nanorods are patterned and crystallized, lateral crystallization is possible. The gold nanorods may have a ratio of length to diameter of 0.5 to 2.

The method may further include forming a heat transfer layer 160a between the active layer 150 and the gold nanorods 160. The heat transfer layer 160a may be a metal such as Mo, Cr, Au, Ag, or an insulator such as AlN, and may have a thickness of 100 kPa to 5000 kPa. The heat transfer layer 160a may facilitate the transfer of heat generated from the gold nanorods 160 to the active layer 150, so that crystallization may be efficiently performed even with low light output. In addition, since uniform heat transfer is possible, uniform crystallization is possible even if the substrate has a large area. And impurities contained in the gold nanorods can be prevented from penetrating into the active layer.

Subsequently, as shown in FIG. 1C, the gold nanorods 160 are irradiated with light in an infrared region to crystallize the active layer 150. A laser or a lamp may be used as the light source in the infrared region. By using a lamp, it is possible to crystallize a large area substrate at once. The wavelength of the light in the infrared region may be 750nm to 910nm, the output may be 5 ~ 20W. The gold nanorods 160 generate heat by absorbing light in the infrared region, and amorphous silicon of the active layer 150 is crystallized into polycrystalline silicon by the generated heat. According to an embodiment of the present invention, since the light in the infrared region is used for crystallization, it is possible to crystallize at a low temperature of 100 ° C. or lower, unlike methods such as solid phase crystallization (SPC) and metal induced crystallization (MIC).

2 illustrates a thin film transistor manufactured by an embodiment of the present invention.

Referring to FIG. 2, a gate 220 is formed on one region of the substrate 210, and a gate insulating layer 230 is formed on the substrate 210 and the gate 220. Here, the blocking layer 210a formed of an oxide or a nitride material may be further included on the substrate 210. The channel 250 corresponding to the active region is formed on the gate insulating layer 230 corresponding to the gate 220. The source electrode 270a and the drain electrode 270b are formed at both sides of the channel 250.

Hereinafter, a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 3E.

Referring to FIG. 3A, a substrate 210 is prepared. After forming the blocking layer 210a on the substrate 210, the gate 220 is formed by applying and patterning a conductive material 220a such as a metal or a conductive metal oxide thereon. Referring to FIG. 3B, an insulating material is coated and patterned on the gate 220 by a process such as CVD to form the gate insulating layer 230.

Referring to FIG. 3C, the channel material is amorphous silicon 250a, heat transfer layer 260a, and gold nanorods 160 on the gate insulating layer 230 corresponding to the gate 220 in the same manner as the above-described embodiment. After coating in order to crystallize the amorphous silicon (250a).

Referring to FIG. 3D, the channel 250 may be removed by removing the gold nanorods 260 and the heat transfer layer 260a, implanting impurity ions into the crystallized silicon 250a, and patterning them by dry or wet etching. Get)

Referring to FIG. 3E, a conductive material is coated on the channel 250 and the gate insulating layer 230, and then patterned in a predetermined pattern to connect the source 270a and the drain 270b to both sides of the channel 250. To form. The source 270a and the drain 270b may be formed of a conductive metal oxide or a metal material. Examples of the conductive metal oxide include indium tin oxide (ITO), indium zinc oxide (IZO), and zinc aluminum oxide (ZAO). Examples of the conductive metal oxide include Ti, Pt, Cr, W, Al, Ni, and Cu. , Mo, Ta or alloys thereof can be used.

4 is a Raman Spectrum for checking the degree of crystallization of silicon according to an embodiment of the present invention. Polycrystalline silicon will show an inherent peak of 510 cm ⁻¹ on the Raman spectrum. Referring to FIG. 4, index numbers 1 and 2 show Raman spectra for Si monolayers and Si / Mo stacks that are not light treated (or light absorbed), and 3, 4, and 5 are used for silicon crystallization. The nanorods show a spectrum of silicon on which the nanorods are irradiated with light formed on the silicon. Here, 3 shows the light absorption after coating the gold nanorods without the heat transfer layer on the silicon, its spectrum does not show the peak of the polycrystalline silicon. And 4 and 5 are Raman spectra having polycrystalline silicon peaks, 4 is a Raman spectrum after about 8 watts of light irradiation under a heat transfer layer formed under the nanorods, and 5 is about 12 without a heat transfer layer under the nanorods. It appears that light absorption of watts has taken place. This results in a crystallization of the gold nanorods coated on amorphous silicon and absorption of light in the nanorods, and crystallization at low light absorption, i.e. at low light output, compared to the absence of a heat transfer layer under the nanorods. It can be seen that appears.

Through the above embodiments, those skilled in the art will be able to manufacture various electronic devices such as displays or memory devices using thin film transistors according to the spirit of the present invention. The thin film transistor according to the embodiment of the present invention may be used as a bottom gate type or a top gate type. As a result, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

1 is a process chart of the polycrystalline silicon thin film manufacturing method according to an embodiment of the present invention.

2 is a schematic cross-sectional view of a thin film transistor according to an exemplary embodiment of the present invention.

3 is a flowchart of a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110, 210: substrate 220: gate

230: gate insulating layer 150, 250: channel layer

160, 260: gold nanorod 260a: heat transfer layer

270a: source 270b: drain

Claims (6)

Forming an active layer of amorphous silicon on the substrate; Applying gold nanorods to the active layer; And crystallizing the active layer by irradiating the gold nanorods with light in an infrared region. The method of claim 1, The gold nano-rod is a polycrystalline silicon thin film manufacturing method, characterized in that the ratio of the length to the diameter of 0.5 to 2. The method of claim 1, And forming a heat transfer layer between the active layer and the gold nanorods. The method of claim 4, wherein the Mo, Cr, Au, Ag, AlN one of the manufacturing method. The method of claim 1, The wavelength of the light in the infrared region is 750 ~ 910 nm polysilicon thin film manufacturing method characterized in that. Forming an active layer of amorphous silicon on the substrate; Applying gold nanorods to the active layer; Irradiating the gold nanorods with light in an infrared region to crystallize the active layer; Doping the active layer with impurity ions and then patterning to form a channel region; And forming a source and a drain positioned at both sides of the channel region, respectively.

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