KR20090049190A - Semicondutor device having modified recess channel gate and method for fabricating the same - Google Patents

Semicondutor device having modified recess channel gate and method for fabricating the same Download PDF

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Publication number
KR20090049190A
KR20090049190A KR1020070115318A KR20070115318A KR20090049190A KR 20090049190 A KR20090049190 A KR 20090049190A KR 1020070115318 A KR1020070115318 A KR 1020070115318A KR 20070115318 A KR20070115318 A KR 20070115318A KR 20090049190 A KR20090049190 A KR 20090049190A
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South Korea
Prior art keywords
gate
trench
substrate
recess
forming
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KR1020070115318A
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Korean (ko)
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김동석
노경봉
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주식회사 하이닉스반도체
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Priority to KR1020070115318A priority Critical patent/KR20090049190A/en
Publication of KR20090049190A publication Critical patent/KR20090049190A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

After the first substrate is etched with a predetermined thickness with a line width smaller than the line width of the gate line according to the present invention, the second substrate is etched with a predetermined thickness with a line width of the gate line. That is, the first etched semiconductor substrate may be additionally etched by the second etching so that the first etched portion and the second etched portion may have a step to form a T-shaped trench. Accordingly, the effective channel length of the active region may be increased to improve electrical characteristics of the semiconductor device. For example, an increase in ion implantation amount due to a decrease in threshold voltage and leakage current due to electric field concentration can be prevented, thereby improving the reflash characteristics of the semiconductor device.

Recess channel, trench, gate, short channel effect

Description

Semicondutor device having modified recess channel gate and method for fabricating the same

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device having a modified recess channel gate and a method of manufacturing the same.

As the design rules of devices become smaller due to the recent higher integration of DRAM cells, the size of cell transistors is reduced, and the channel length of transistors is also shortened. As the channel length of the trencher becomes shorter, short channel effects occur that cause punch through, decrease threshold voltage, increase leakage current, and decrease the relash characteristics. Can be.

Therefore, a semiconductor device having a recess trench that suppresses short channel effects by increasing the length of a channel within a limited area has been proposed. For example, forming a trench in a substrate, forming a recess gate for forming a gate in the trench, or forming a trench bottom surface in a spherical shape, and forming a bulb type recess gate for forming a gate in the trench. have.

However, the recess gate having such a structure must inject ions to the lower end recessed in the semiconductor substrate during ion implantation for channel formation, thereby injecting ions with high energy. In addition, the channel is increased by the recessed depth, and the cell resistance of the transistor is rapidly increased. When the ion implantation dose is increased to reduce this resistance, the electric field increases to cause a leakage current, thereby deteriorating the electrical characteristics of the semiconductor device, for example, the re-flash characteristics of the device, causing malfunction of the device.

A semiconductor device having a modified recess channel gate according to the present invention includes an active region defined by an isolation layer in a substrate; A trench disposed in the active region in a T-shape; And a recess gate in the trench.

The T-shaped trench may include: a first trench recessed in a predetermined thickness in an active region of the substrate; And a second trench recessed in the middle portion of the first trench bottom surface relatively deeper than the first trench.

The second trench is preferably arranged to have a line width relatively smaller than that of the first trench.

The first trench is preferably arranged to have a depth of 100 to 1000 mm 3 from the surface of the substrate.

The second trench is preferably arranged to have a depth of 200 to 2000 microns from the surface of the substrate.

Preferably, the recess gate includes a gate insulating film, a gate conductive film, and a hard mask film.

A method of manufacturing a semiconductor device having a modified recess channel gate according to the present invention may include forming an isolation layer for setting an active region on a substrate; Forming a first trench by etching the substrate to a predetermined thickness using a first mask pattern that selectively exposes the active region of the substrate; Further etching the substrate to a predetermined thickness using a second mask pattern having an open area relatively larger than the first mask pattern to form a T-shaped second trench; And forming a recess gate in the second trench.

Preferably, the first mask pattern exposes an active region of the substrate with a line width relatively smaller than that of the recess gate.

Etching for the first trench is preferably etched to a depth of 100 ~ 1000Å from the surface of the substrate.

The first trench may adjust the line width of the first trench by the open margin of the first mask pattern.

The second mask pattern may expose the active region of the substrate at the recess gate line width.

Etching for the second trench is preferably etched to a depth of 100 ~ 1000Å from the surface of the substrate.

The second T-shaped trench may be formed by etching the first trenched substrate together while further etching the substrate exposed by the second mask pattern.

After the forming of the second trench, forming a screen oxide film on the semiconductor substrate on which the second trench is formed; And implanting impurity ions for channel formation into the substrate.

The impurity ions are preferably implanted with BF 2 ions at an energy of 10 to 30 KeV and a dose concentration of 1.0E12 to 1.0E 14 ions / cm 2.

The implanting of the impurity ions may be performed by applying a tilt of a predetermined range to inject ions into the T-shaped second trench side.

The forming of the recess gate may include forming a gate insulating layer, a gate conductive layer, and a hard mask layer on the substrate on which the second trench is formed; And sequentially patterning the hard mask layer, the gate conductive layer, and the gate insulating layer to form a recess gate including a gate insulating layer pattern, a gate conductive layer pattern, and a hard mask layer pattern.

(Example 1)

Referring to FIG. 1, a structure of a semiconductor device having a modified recess channel gate according to the present invention is formed by filling an insulating film in a device isolation trench introduced to form a device isolation region in a semiconductor substrate 100. The device isolation layer 130, the trench 151 disposed in a T-shape disposed in the active region defined by the device isolation layer 130, and the gate line disposed in the recess channel trench are included. The T-shaped trench consists of a first trench recessed in a predetermined thickness in the active region of the substrate and a second trench recessed deeper than the first trench in the middle portion of the first trench bottom surface. In this case, the second trench may be arranged to have the same line width as that of the gate line, and the first trench may be arranged to have a line width relatively smaller than that of the second trench. The first trench may be arranged to have a depth of 100 to 1000 microns from the substrate surface, and the second trench may be disposed to have a depth of 200 to 2000 microns from the substrate surface to be etched deeper in the bottom middle portion of the first trench. have.

The gate line includes a gate insulating film pattern 161, a gate conductive film pattern 171, a gate metal film pattern 181, and a hard mask film pattern 191. For example, the gate insulating layer pattern 161 may be formed of an insulating material such as silicon oxide. The gate conductive layer pattern 171 may be disposed as a polysilicon layer doped with impurities such as phosphorous. The gate conductive layer pattern 171 may be disposed as a polysilicon layer having a thickness of approximately 500 to 1500 Å. The gate metal layer pattern 181 may include a tungsten nitride layer and a tungsten layer. Before forming the gate metal layer pattern 180, a tungsten silicide layer pattern may be disposed. The hard mask layer pattern 191 may include an insulating material such as a silicon nitride layer.

(Example 2)

Referring to FIG. 2, a mask pattern including a pad oxide film pattern 110 and a pad nitride film pattern 111 is formed on the semiconductor substrate 100. Specifically, after forming a pad oxide film, a pad nitride film, and a resist film on the semiconductor substrate 100, a photolithography process is performed to form a resist film pattern 120 exposing a predetermined region of the semiconductor substrate 100. Here, the pad oxide film serves to relieve stress of the semiconductor substrate due to the attraction of the pad nitride film. The resist film pattern 120 may be disposed to expose a region where the device isolation layer defining the active region is to be formed.

Next, an etching process using the resist film pattern 120 as an etching mask is performed to form the pad oxide film pattern 110 and the pad nitride film pattern 111. In this case, the pad nitride layer pattern 111 may be used as a hard mask during an etching process for forming a trench for subsequent device isolation.

Next, a portion of the semiconductor substrate 100 exposed by the pad nitride layer pattern 111 and the pad oxide layer pattern 110 is selectively etched to form a device isolation trench 130. The device isolation trench may be formed by a plasma etching process or a dry etching process.

Referring to FIG. 3, a trench device isolation layer 131 filling an insulating layer, for example, a high density plasma (HDP) oxide layer 140 in the device isolation trench 130 to set an active region of the semiconductor device 100. To form. Specifically, an HDP oxide film is formed on the entire surface of the semiconductor substrate on which the device isolation trench 130 is formed, and a planarization process for separating the HDP oxide film is performed, for example, chemical mechanical polishing (CMP). Subsequently, the pad nitride film pattern, the pad oxide film pattern, and the resist pattern are removed. Then, the trench isolation layer 131 is formed on the semiconductor substrate 100 to define the active region and the isolation region.

Referring to FIG. 4, a first mask pattern 140 is formed on the semiconductor substrate 100 on which the device isolation layer 131 is formed to selectively expose the active region. The first mask pattern 140 may be formed to expose the active region of the semiconductor substrate with a line width relatively smaller than that of the subsequent gate line.

Next, the first trench 150 is formed by etching the semiconductor substrate 100 having the first mask pattern 140 as an etch mask to a predetermined thickness d 1 . In this case, the first trench 150 may be etched to have a depth of 100 to 1000 Å from the surface of the semiconductor substrate. Since the line width w 1 of the first trench 150 is determined by an open margin of the first mask pattern 140, for example, a portion of the semiconductor substrate exposed by the first mask pattern 140, the first width 150 may be defined. The line width w 1 of the first trench 150 may be adjusted by adjusting the open margin of the mask pattern 140. On the other hand, the open margin of the first mask pattern 140 is preferably formed to have a line width relatively smaller than the line width of the subsequent gate line.

Referring to FIG. 5, after removing the first mask pattern, a second mask pattern 141 having an open margin relatively larger than the first mask pattern is formed. The second mask pattern 141 may be formed to expose the active region of the semiconductor substrate by the line width of the subsequent gate line.

Referring to FIG. 6, the T-shaped second trench 151 is formed by etching the semiconductor substrate 100 exposing the second mask pattern 141 as an etch mask to a predetermined thickness d 2 . For example, as the semiconductor substrate 100 exposed by the second mask pattern 141 is etched to a predetermined thickness d 2 , a portion of the semiconductor substrate exposed to the bottom surface of the first trench is a predetermined thickness d 1 + d 2 . The second trench 151 having a stepped T shape is formed by etching.

In this case, the second trench 151 may be etched to have a depth of 100 to 1000 Å from the surface of the semiconductor substrate 100. That is, the portion of the semiconductor substrate 100 which is blocked by the first mask pattern and exposed by the second mask pattern 141 is etched to a thickness of 100 to 1000 Å, so that the portion of the first trenched semiconductor substrate 100 is 100 To 1000 μs thick may be further etched to etch to 200 to 2000 μs deep. The line width w 2 of the second trench may be formed with a line width relatively larger than the line width w 1 of the first trench, and may be formed with the line width of a subsequent gate line.

Referring to FIG. 6, N-type impurity ions are implanted into the semiconductor substrate 100 on which the T-shaped second trench 151 is formed. Specifically, BF 2 using ion implantation equipment in the semiconductor substrate 100 Implant ions. The ion implantation equipment may use single type or semi batch type equipment. At this time, BF 2 Ions are implanted with ion implantation energies of 10 to 30 KeV and doses of B 11 ions of 1.0E12 to 1.0E14 ions / cm 2. During ion implantation, a range of tilts may be applied to cause ions to be implanted in the T-shaped second trench side. Accordingly, ions can be uniformly implanted into the bottom and side surfaces of the T-shaped second trench without increasing the ion implantation amount.

Before implanting the impurity ions, a screen oxide film may be formed on the semiconductor substrate on which the second trench 151 is formed. The screen oxide film acts as a protective film to prevent damage to the semiconductor substrate during impurity ion implantation.

 Meanwhile, the semiconductor substrate may be defined as a semiconductor substrate for forming an NMOS transistor. In some cases, the semiconductor substrate may be defined as a semiconductor substrate for forming a PMOS transistor, but in this case, it is preferable to implant P-type impurity ions.

Referring to FIG. 7, the gate insulating layer 160 is formed on the semiconductor substrate 100 on which the T-shaped second trench 151 is formed. The gate insulating layer 160 may be formed by selectively oxidizing the semiconductor substrate 100 so that the silicon oxide layer is grown only in the active region of the semiconductor substrate 100.

A gate conductive layer 170 is formed to cover the second T-shaped trench 151 having the gate insulating layer 160 formed thereon. The gate conductive layer 170 may be formed of a polysilicon layer doped with impurities such as phosphorous (P). The polysilicon film can be formed to a thickness of approximately 500 to 2500 kPa. In this case, the phosphorus doped in the polysilicon film may be formed to have a dose concentration of 2.0 E 20 to 8.0E 20 ions / cm 3. The polysilicon film may be formed using a furnace or sheet type deposition equipment. At this time, the deposition equipment is preferably maintained at a temperature of about 450 to 700 ℃.

Referring to FIG. 8, a planarization process, for example, an etch back process, is performed such that the gate conductive film remains only inside the T-shaped second trench. Then, the gate conductive film pattern 171 is formed in the T-shaped second trench.

A gate metal layer 180 and a hard mask layer 190 are formed on the semiconductor substrate 100 on which the gate conductive layer pattern 100 is formed. The gate metal film 180 may include a tungsten nitride film and a tungsten film. Before forming the gate metal film 180, a tungsten silicide film may be formed. In this case, the tungsten silicide layer may suppress the occurrence of silicon nitride at the interface between the gate conductive layer 170, for example, the polysilicon layer and the tungsten nitride layer by a subsequent thermal process. The hard mask layer 190 may include an insulating material such as a silicon nitride layer. The hard mask layer 190 may be used as an etching mask in a subsequent gate etching process, or may protect the lower gate electrode during subsequent contact hole formation.

Referring to FIG. 9, a hard mask film, a gate metal film, a gate conductive film, and a gate insulating film are patterned using a photolithography process to form a gate insulating film pattern 161, a gate conductive film pattern 171, and a gate metal film pattern 181. ) And a gate line formed of the hard mask pattern 191.

According to an embodiment of the present invention, first, the semiconductor substrate is first etched to a predetermined thickness with a line width smaller than the line width of the gate line, and then a second thickness is etched to the line width of the gate line. That is, the first etched semiconductor substrate may be additionally etched by the second etching so that the first etched portion and the second etched portion may have a step to form a T-shaped trench. Accordingly, the effective channel length of the active region may be increased to improve electrical characteristics of the semiconductor device. For example, an increase in ion implantation amount due to a decrease in threshold voltage and leakage current due to electric field concentration can be prevented, thereby improving the reflash characteristics of the semiconductor device.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 is a cross-sectional view illustrating a semiconductor device having a modified recess channel gate according to the present invention.

2 to 10 are cross-sectional views illustrating a method of forming a semiconductor device having a modified recess channel gate according to the present invention.

Claims (16)

An active region defined by an isolation layer in the substrate; A trench disposed in the active region in a T-shape; And And a modified recess channel gate having a recess gate in the trench. The method of claim 1, The trench arranged in the T-shape, A first trench recessed to a predetermined thickness in an active region of the substrate; And a modified recess channel gate in a middle portion of the bottom surface of the first trench, the second trench being recessed relatively deeper than the first trench. The method of claim 2, And the second trench has a modified recess channel gate disposed to have a line width relatively smaller than that of the first trench. The method of claim 2, And the first trench has a modified recess channel gate disposed to have a depth of 100 to 1000 microns from the surface of the substrate. The method of claim 2, And the second trench has a modified recess channel gate disposed to have a depth of 200 to 2000 microns from the surface of the substrate. The method of claim 1, And the recess gate has a modified recess channel gate including a gate insulating film, a gate conductive film, a gate metal film, and a hard mask film. Forming an isolation layer for setting an active region on the substrate; Forming a first trench by etching the substrate to a predetermined thickness using a first mask pattern that selectively exposes the active region of the substrate; Etching the substrate to a predetermined thickness using a second mask pattern having an open area relatively larger than the first mask pattern, and further etching the first trenched substrate to form a T-shaped second trench; And Forming a recess gate in the second trench; and forming a recess gate in the second trench. The method of claim 7, wherein The first mask pattern has a modified recess channel gate to expose the active region of the substrate with a line width relatively smaller than the line width of the recess gate. The method of claim 7, wherein And etching the first trenches to a depth of 100 to 1000 microns from the surface of the substrate. The method of claim 7, wherein And the second mask pattern has a modified recess channel gate exposing an active region of the substrate with the recess gate line width. The method of claim 7, wherein And etching the second trenches to a depth of 100 to 1000 microns from the surface of the substrate. The method of claim 7, wherein The second trench having the T-shape has a modified recess channel gate formed by etching the first trenched substrate together while further etching the substrate exposed by the second mask pattern. The method of claim 7, wherein After forming the second trench, Forming a screen oxide film on the semiconductor substrate on which the second trench is formed; And implanting impurity ions for channel formation into the substrate. The method of claim 13, The impurity ion is a method of manufacturing a semiconductor device having a modified recess channel gate is implanted by setting the BF2 ions to energy of 10 to 30 KeV and the dose concentration of 1.0E12 to 1.0E 14 ions / ㎠. The method of claim 13, The implanting the impurity ions is a method of manufacturing a semiconductor device having a modified recess channel gate for implanting by applying a range of tilt (tilt) to implant ions into the T-shaped second trench side. The method of claim 7, wherein Forming the recess gate, Forming a gate insulating film, a gate conductive film, a gate metal film, and a hard mask film on the substrate on which the second trench is formed; And Sequentially patterning the hard mask, gate metal, gate conductive and gate insulating layers to form a recess gate including a gate insulating pattern, a gate metal layer pattern, a gate conductive layer pattern, and a hard mask layer pattern. A method of manufacturing a semiconductor device having a modified recess channel gate.
KR1020070115318A 2007-11-13 2007-11-13 Semicondutor device having modified recess channel gate and method for fabricating the same KR20090049190A (en)

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