KR20090046406A - Chip on glass type liquid crystal display device - Google Patents

Abstract

The present invention provides a display device comprising: a first substrate having a display area and a first non-display area having a gate pad terminal formed therein and a second non-display area having a data pad terminal defined therein; A plurality of gate driving integrated circuits in a chip form spaced apart from each other and mounted in the first non-display area on the first substrate; A plurality of data driving integrated circuits in a chip form spaced apart from each other and mounted in the second non-display area on the first substrate; A first connection part spaced apart from the first non-display area by a first distance in the second non-display area and electrically connected to and mounted in the plurality of data driving integrated circuits and the plurality of driving gate driving integrated circuits; A second connection part electrically connected to the plurality of data driving integrated circuits, the second connection part being spaced apart from the first non-display area by a second distance greater than a first distance from the first non-display area; A flexible printed circuit (FPC) electrically connected to the first connector and the second connector; A plurality of signal wires electrically connected to the first connection part in an area between the first non-display area and the second non-display area and between the first non-display area and the first connection part; A first area between the first connection part and the second connection part closest to the second non-display area, and a second area from the second connection part to an end located in an opposite direction in which the first connection part is located; A plurality of dummy patterns serving to prevent light transmission; A second substrate facing the first substrate; Provided is a COG type liquid crystal display device including a liquid crystal layer interposed between the first and second substrates.

LCD, COG, Light leakage, Dummy pattern, FPC

Description

CIO on type liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display (COG) structure having a dummy pattern for preventing light leakage.

Recently, as the information society has developed rapidly, the necessity of a display device having excellent characteristics such as thinning, light weight, and low power consumption has emerged. Accordingly, development of flat panel displays has been actively conducted. In particular, liquid crystal displays are excellent in resolution, color display, image quality, and the like, and are being actively applied to monitors of notebook computers and desktop computers.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

In more detail, the structure thereof will be described with reference to FIG. 1, which is an exploded perspective view of a general liquid crystal display. As shown, the liquid crystal display includes an array substrate 10 and a color filter with a liquid crystal layer 30 therebetween. The substrate 20 has a configuration in which the substrates are face-to-face bonded to each other. The array substrate 10 of the lower part of the plurality of gate wirings 14 is vertically and horizontally arranged on the upper surface of the transparent substrate 12 to define a plurality of pixel regions P. And a data line 16, and a thin film transistor T is provided at an intersection point of the two lines 14 and 16 so as to be connected one-to-one with the pixel electrode 18 provided in each pixel region P. FIG.

In addition, the upper color filter substrate 20 facing the array substrate 10 is a rear surface of the transparent substrate 22, and the non-display of the gate wiring 14, the data wiring 16, the thin film transistor T, and the like. A grid-like black matrix 25 is formed around the pixel region P so as to cover the region, and red (R) and green are sequentially arranged in order to correspond to the pixel region (P) in the grid. A color filter layer 26 including (G) and blue (B) color filter patterns 26a, 26b, and 26c is formed, and is transparent over the entire surface of the black matrix 25 and the color filter layer 26. The common electrode 28 is provided.

Although not shown in the drawings, each of the two substrates 10 and 20 is sealed with a sealant or the like along the edge to prevent leakage of the liquid crystal layer 30 interposed therebetween. 10 and 20 are interposed between upper and lower alignment layers that provide reliability in the molecular alignment direction of the liquid crystal at a boundary portion of the liquid crystal layer 30, and at least one outer surface of each substrate 10 and 20 is provided with a polarizing plate. have.

In addition, a back-light is provided on the outer surface of the array substrate 10 to supply light, so that the on / off signal of the thin film transistor T is transmitted to the gate wiring 14. When the image signal of the data wiring 16 is transferred to the pixel electrode 18 of the selected pixel region P by being sequentially scanned and applied, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the transmittance of light We can display various images by change

In the liquid crystal display device having such a structure, the array substrate, the color filter substrate, and the liquid crystal layer interposed between the two substrates are defined as a liquid crystal panel, and a driving unit for driving the liquid crystal panel is formed on the outer side of the liquid crystal panel. The driving unit is a printed circuit board (PCB) on which components generating various control signals, data signals, etc. are mounted, and a driving integrated circuit connected to the liquid crystal panel and the printed circuit board and applying a signal to the wiring of the liquid crystal panel. And a drive IC, comprising a chip on glass (COG) method, a tape carrier package (TCP) method, and the like, according to a method of packaging a driving integrated circuit on the liquid crystal panel. It is divided into a chip on film (COF) method.

The dual COG method has been widely applied to liquid crystal display devices in recent years because the structure is simpler than the TCP method and the COF method, and the liquid crystal panel can increase the ratio of the liquid crystal panel.

Referring to FIG. 2, which is a schematic plan view of a conventional COG type liquid crystal display, a conventional COG type liquid crystal display 51 includes a display area AA for displaying an image and a peripheral portion of the display area AA. The first substrate 60 in which the first and second non-display areas NA1 and NA2 are positioned is disposed, and at a position corresponding to the display area AA of the first substrate 60, The second substrate 80 is disposed to expose the first and second non-display areas NA1 and NA2 of the first substrate 60. In the first non-display area NA1 of the first substrate 60, the plurality of gate driving integrated circuits 67 apply gate signal voltages to the plurality of gate lines 63 formed in the display area AA. In the second non-display area NA2, a plurality of data driving integrated circuits 69 for applying data signal voltages to the plurality of data lines 65 formed in the display area AA are mounted. In addition, the second non-display area NA2 including the data driving integrated circuit 69 among the non-display areas NA1 and NA2 including the gate driving integrated circuit 67 or the data driving integrated circuit 69 is configured to perform the gate. Alternatively, an FPC 75 having a wiring and a circuit configured to apply an input signal to each of the data driver integrated circuits 67 and 69 is connected through two FPC connectors 73a and 73b. In this case, the plurality of data driver integrated circuits 69 are all located on the same line, and the two FPC connection parts 73a and 73b are located outside the plurality of data driver integrated circuits 69.

Meanwhile, a left side of the two FPC connectors 73a and 73b adjacent to the first non-display area NA1 in which the gate driving integrated circuit 67 is located (hereinafter, referred to as a first FPC connector 73a). In order to transfer various signals to the gate driving integrated circuit 67, a plurality of signal connection wirings 70 are connected to the first FPC connection portion 73a and the outermost side along the edge of the first substrate 60. Consists of. In this case, the first FPC connection unit 73a connects the plurality of signal connection wirings to signals transmitted to the gate driving integrated circuit 67 in addition to the signals to the data driving integrated circuits 69 that receive signals. It will serve to deliver through 70.

In the COG type liquid crystal display device, the reason why the signal connection wiring is formed on the first substrate 60 as described above is that a gate PCB or a gate FPC in which a circuit and wiring for applying a signal to the gate driving integrated circuit 67 are formed. (Flexible Printed Circuit) is omitted, and one FPC 75 is formed by forming both a circuit and a wiring for applying a signal to the gate driver integrated circuit 67 in the FPC 75 connected to the data driver integrated circuit 69. This is to reduce the manufacturing cost of the liquid crystal display by driving using.

However, the conventional COG type liquid crystal display 51 having the signal connection wiring 70 and the FPC 75 and the first and second FPC connectors 73a and 73b has the second non-display area NA2. In the region between the first and second FPC connectors 73a and 73b and the right region of the second FPC connector 73b, the signal connection wiring 70 is not formed, thereby remaining transparent. When the image is implemented through the area AA, although the edge black matrix 83 is formed to cover the display area AA and block light, the first and second FPC connection parts 73a and 73b are internally formed. Light leaks into the areas B and C where no components are formed between and between the right side of the second FPC connection 73b and the non-display areas NA1 and NA2 are not shown in the drawing. Reflected by the module, such as the top cover to reach the display area This causes light leakage, which causes unevenness due to the difference in luminance, thereby degrading display quality.

An object of the present invention is to provide a COG type liquid crystal display device having a structure in which light leakage does not occur in a region between FPC connection portions.

According to the present invention, there is provided a COG type liquid crystal display device comprising: a first substrate having a display area, a first non-display area having a gate pad terminal formed therein, and a second non-display area having a data pad terminal defined therein; A plurality of gate driving integrated circuits in a chip form spaced apart from each other and mounted in the first non-display area on the first substrate; A plurality of data driving integrated circuits in a chip form spaced apart from each other and mounted in the second non-display area on the first substrate; A first connection part spaced apart from the first non-display area by a first distance in the second non-display area and electrically connected to and mounted in the plurality of data driving integrated circuits and the plurality of driving gate driving integrated circuits; A second connection part electrically connected to the plurality of data driving integrated circuits, the second connection part being spaced apart from the first non-display area by a second distance greater than a first distance from the first non-display area; A flexible printed circuit (FPC) electrically connected to the first connector and the second connector; A plurality of signal wires electrically connected to the first connection part in an area between the first non-display area and the second non-display area and between the first non-display area and the first connection part; A first area between the first connection part and the second connection part closest to the second non-display area, and a second area from the second connection part to an end located in an opposite direction in which the first connection part is located; A plurality of dummy patterns serving to prevent light transmission; A second substrate facing the first substrate; And a liquid crystal layer interposed between the first and second substrates.

The plurality of dummy patterns may be in the same wiring form as the signal connection wiring, bar or plate, and may be formed of the same material on the same layer as the signal connection wiring.

In the display area of the first substrate, a gate wire connected to the gate pad terminal, a data wire connected to the data pad terminal, a thin film transistor connected to the gate and the data wire, and a pixel electrode connected to the thin film transistor are further included. The second substrate may further include a color filter layer and a common electrode corresponding to the display area.

An array wave for a COG type liquid crystal display device according to the present invention comprises: a substrate having a display area and a first non-display area having a gate pad terminal formed therein and a second non-display area having a data pad terminal defined therein; A plurality of gate driver integrated circuits in a chip form spaced apart from each other and mounted in the first non-display area on the substrate; A plurality of data driver integrated circuits in chip form spaced apart from each other and mounted in the second non-display area on the substrate; A first connection part spaced apart from the first non-display area by a first distance in the second non-display area and electrically connected to and mounted in the plurality of data driving integrated circuits and the plurality of driving gate driving integrated circuits; A second connection part electrically connected to the plurality of data driving integrated circuits and spaced apart from the first non-display area by a second distance greater than a first distance from the first non-display area; A flexible printed circuit (FPC) electrically connected to the first connector and the second connector; A plurality of signal wires electrically connected to the first connection part in an area between the first non-display area and the second non-display area and between the first non-display area and the first connection part; A first area between the first connection part and the second connection part closest to the second non-display area, and a second area from the second connection part to an end located in an opposite direction in which the first connection part is located; And include a plurality of dummy patterns which serve to prevent light transmission.

In the COG type liquid crystal display according to the present invention, a plurality of FPC connection units for transmitting various signals to gate and data driving integrated circuits connected to these terminals in the first and second non-display areas where gate and data pad terminals are formed. By forming a dummy pattern such as a signal connection wiring formed to connect the FPC connection unit and the gate driving integrated circuit in an area therebetween, there is an effect of preventing light leakage caused by light emitted through this area. Furthermore, the display quality is improved by preventing light leakage.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

3 is a schematic plan view of a COG type liquid crystal display according to an exemplary embodiment of the present invention.

As illustrated, the COG type liquid crystal display device 151 according to the present invention includes a display area AA and first and second non-display areas NA1 and NA2 defined around the display area AA. The first and second non-display areas NA1 and NA2 of the first substrate 160 are exposed at positions corresponding to the first substrate 160 and the display area AA of the first substrate 160. The two substrates 180 face each other, and a liquid crystal layer (not shown) is interposed between the two substrates 160 and 180.

On the other hand, in the display area AA of the first substrate 160, a plurality of gate lines 163 and data lines 165 defining a plurality of pixel areas P intersecting with each other, and the pixel areas P, respectively. ) A gate electrode (not shown), a gate insulating film (not shown), and a semiconductor layer (not shown) that are sequentially connected to the gate line 163 and the data line 165 defining the pixel areas P, respectively. A thin film transistor Tr including a spaced source and drain electrode (not shown) and a pixel electrode 161 connected to the drain electrode (not shown) of the thin film transistor Tr are formed.

In this case, each of the plurality of gate lines 163 and the plurality of data lines 165 is divided into several groups, and ends thereof extend into the first non-display area NA1 and the second non-display area NA2, respectively. Each end extending to the first and second non-display areas NA1 and NA2 has a gate pad terminal (not shown) and a data pad terminal (not shown), respectively. The gate and data pad terminals (not shown) are formed to have a very tight first spacing within the group for each divided group, and have a second spacing which is several times to several hundred times larger than the first spacing between different groups. It is spaced apart and composed. In the drawing, the plurality of gate wires 163 and the gate pad terminals (not shown) connected thereto constitute a total of three groups, and the data wires 165 and the data pad terminals (not shown) connected thereto constitute a total of eight groups. The number of such groups may be variously configured according to the size and model of the COG type liquid crystal display.

Meanwhile, as described above, the gate and data pad terminals (not shown), which are divided into a plurality of groups, overlap with each other, and are electrically connected to each other through terminals and bumps. The gate and data driving integrated circuits 167 and 169 are mounted for each group so as to be located on the same line in the non-display areas NA1 and NA2. One gate 171a is connected, and a plurality of gate driving integrated circuits 167 are also electrically connected through a plurality of second wires 171b.

The plurality of gate pad terminals (not shown) and the data pad terminals (not shown) may be divided into a plurality of groups so that the plurality of gate pad terminals and the data pad terminals are mounted in contact with the gate pad terminals and the data pad terminals. And the data driving integrated circuits 167 and 169 are configured in a chip form having a predetermined width and width, and the chip integrated driving integrated circuits have a limit of ability to process simultaneously. This is because all the circuit elements for signal processing applied to all the gates and the data lines 163 and 165 may not be configured in one chip. In addition, although the chip-type gate and data driving integrated circuits 167 and 169 may be formed to have sufficient ability to transmit signals to all the gate and data lines 163 and 165 in this case, Since the length and width must be increased, it is difficult to mount one chip type gate and data driver integrated circuit having such a large length and width in the first and second non-display areas NA1 and NA2 of the first substrate, respectively. This is because it is high and is likely to be easily affected by an external impact, and an internal defect is likely to occur. In addition, when a chip defect occurs, a repair process is performed. In this case, a plurality of chips are removed even when the gate and data driving integrated circuits 167 and 169 which are already mounted on the first substrate 160 are removed. In the case of mounting, the removal time is increased because more parts are connected to the gate and data wiring pad terminals (not shown) than to remove one chip having a defect, and the cost also increases.

Therefore, in view of all of these, the gate and data driving integrated circuits 167 and 169 have a further advantage of being appropriately divided into several groups. In this case, in mounting the gate and data driving integrated circuits 167 and 169 having a plurality of chip shapes, the chip and gate and data driving integrated circuits 167 may be easily mounted to increase the mounting efficiency and to be easily removed during the repair process. 169, it is advantageous to have a predetermined spacing interval so that these chip-shaped gates and data driving integrated circuits 167, 169 are arranged to have a suitable spacing interval as shown, and these chip-shaped gates and The gate pad terminals (not shown) and the data pad terminals (not shown) connected to the gate and the data lines 163 and 165, respectively, for electrical connection with the data driving integrated circuits 167 and 169 form a grouped form. .

In the first substrate 160 having such a configuration, in the second non-display area NA2 in which the data driving integrated circuit 169 is formed, the first and second FPCs are disposed below the line on which the data driving integrated circuit 169 is formed. The connecting portions 173a and 173b are electrically connected to and mounted in the plurality of gate and data driving integrated circuits 167 and 169 through an anisotropic conductive film (ACF) (not shown). In this case, although the FPC connection parts 173a and 173b are shown as two, a larger number of FPC connection parts 173 may be mounted as a modification. In this case, the FPC connection portion mounted closest to the first non-display area NA1 is defined as a plurality of second FPC connection portions 173b other than the first FPC connection portion 173a.

Meanwhile, flexible printed circuits (FPCs) including circuits and wirings for applying predetermined signals to the gate and data driving integrated circuits 167 and 169 are provided at ends of the first and second FPC connectors 173a and 173b. 175 is configured. In this case, the first and second FPC connection parts 173a and 173b may be integrally formed with the FPC 175 or may be dualized with the FPC 175 to form a film including a plurality of wirings. Like the shape mounted on the first substrate 160, the FPC 175 may be attached via an anisotropic conductive film (ACF) (not shown).

On the other hand, the first non-display from the first FPC connection 173a which is adjacent to the first non-display area NA1 provided with the gate driving integrated circuit 167 and is mounted in the second non-display area NA2. The plurality of areas in the area outside the plurality of data driving integrated circuits 169 and the first non-display area NA1 among the areas to the left end of the second non-display area NA2 that meet the area NA1. For the region outside the chip-shaped gate driver integrated circuit 167, a plurality of signals are transferred from the FPC 175 to the gate driver integrated circuit 167 through the second FPC connection 173a. The signal connection wiring 170 is configured.

In addition, as a characteristic feature of the present invention, in the second non-display area NA2, an area between the first FPC connection part 173a and the second FPC connection part 173b positioned closest thereto, The plurality of data driving integrated circuits 169 of the plurality of data driving integrated circuits 169 of the areas from the outermost second FPC connection unit 173b to the end of the second non-display area NA2 that do not meet the first non-display area NA1. The second FPC connection portion 173b is substantially not exposed to the transparent first substrate 160 with respect to the outer side, that is, the edge located on the edge of the first substrate (hereinafter, referred to as dummy regions B and C, respectively). The plurality of dummy patterns 191, to which no signal is transmitted, are not electrically connected to each other, and are formed in a wiring form as the plurality of signal connection wirings 170 are formed. In the modification, dummy patterns are also formed in regions (not shown) between the plurality of second FPC connection portions.

In this case, the plurality of dummy patterns 191 may be formed of the same material on the same layer on which the signal connection line 170 is formed, or is opaque to another layer different from the layer on which the signal connection line 170 is formed. It may be formed of a material. At this time, the dummy pattern 191 is a plan view of the COG type liquid crystal display device according to a modification of the embodiment of the present invention (as shown in FIG. 4 with the same reference numerals to the same components as the embodiment) as shown in FIG. It is not necessarily wired, but may be in the form of a plate or bar. The reason for this configuration is that the dummy pattern 191 reflects light from a backlight (not shown) to the module such as a top cover (not shown) made of a metal material through the dummy areas B and C. To prevent light leakage from the data pad side by leaking into the display area AA, and thus the dummy areas B and C are opaque materials that do not transmit light without maintaining a transparent state as in the prior art. This is because the dummy pattern 191 may be configured to only transmit light emitted from the backlight (not shown).

Therefore, the dummy patterns 191 formed in the dummy regions B and C do not necessarily have to be in the form of wires. However, since it is most preferable to create the same environment as the areas in the first and second non-display areas NA1 and NA2 in which the plurality of signal connection wirings 170 are formed, the dummy area ( B and C) shows that the dummy pattern 191 is configured in a wiring form as if the signal connection wiring 170 is formed.

Meanwhile, the second substrate 180 positioned to expose the first and second non-display areas NA1 and NA2 in correspondence with the first substrate 160 having the above-described configuration may be disposed at the edge portion thereof. The edge black matrix 183 is formed to have a predetermined width and surround the display area AA. Although not shown, the gate and data formed on the first substrate 160 inside the edge black matrix 183 are not shown. A black matrix (not shown) is formed of the same material forming the edge black matrix 183 corresponding to the wirings 163 and 165 and the region where the thin film transistor Tr is formed, and the black matrix (not shown) A color filter layer (not shown) including red, green, and blue color filter patterns is formed and overlaps with each other to sequentially overlap each pixel region P. The color filter layer (not shown) overlaps with and is transparent. The whole electrode (not shown) is formed.

Although not shown in the figure, the two substrates 160 and 180 correspond to a region in which the edge black matrix 183 is formed to prevent leakage of a liquid crystal layer (not shown) interposed therebetween. The seal pattern is formed along an edge of the display area AA, and at least one outer surface of the first and second substrates 160 and 180 is formed with a polarizer (not shown). A back-light (not shown) is formed on the outer surface of the 160 to form the COG type liquid crystal display 151 according to the present invention.

The COG type liquid crystal display device 151 having such a configuration includes a non-display area B between the first and second FPC connection parts 173a and 173b and a gate and a second FPC connection part 173b positioned at the outermost part. Light leakage occurs in the display area AA by forming a dummy pattern 191 in the form of a wire, a bar, or a plate corresponding to the non-display area C to the edge of the side portion where the pad terminal (not shown) is not formed. It is characterized by improving the display quality by preventing.

In addition, this invention is not limited to the above-mentioned embodiment and its modified example, It can implement in various changes within the range which does not deviate from the meaning of this invention.

1 is a perspective view of a general liquid crystal display device.

2 is a schematic plan view of a conventional COG type liquid crystal display device.

3 is a schematic plan view of a COG type liquid crystal display device according to an embodiment of the present invention.

4 is a schematic plan view of a COG type liquid crystal display according to a modification of the present invention.

<Description of Symbols for Main Parts of Drawings>

151 COG type liquid crystal display device 160 first substrate

161: pixel electrode 163: gate wiring

165: data wiring 167: gate driving integrated circuit

169: data driving integrated circuit 170: signal connection wiring

171a, 171b: 1st, 2nd wiring 173a, 173b: 1st, 2nd FPC connection part

175: FPC 180: second substrate

183: border black matrix 191: dummy pattern

AA: Display Area B, C: Dummy Area

NA1, NA2: first and second non-display areas P: pixel areas

Tr: Thin Film Transistor

Claims (5)

A first substrate including a first non-display area having a display area and a gate pad terminal formed around the display area and a second non-display area having a data pad terminal; A plurality of gate driving integrated circuits in a chip form spaced apart from each other and mounted in the first non-display area on the first substrate; A plurality of data driving integrated circuits in a chip form spaced apart from each other and mounted in the second non-display area on the first substrate; A first connection part spaced apart from the first non-display area by a first distance in the second non-display area and electrically connected to and mounted in the plurality of data driving integrated circuits and the plurality of driving gate driving integrated circuits; A second connection part electrically connected to the plurality of data driving integrated circuits, the second connection part being spaced apart from the first non-display area by a second distance greater than a first distance from the first non-display area; A flexible printed circuit (FPC) electrically connected to the first connector and the second connector; A plurality of signal wires electrically connected to the first connection part in an area between the first non-display area and the second non-display area and between the first non-display area and the first connection part; A first area between the first connection part and the second connection part closest to the second non-display area, and a second area from the second connection part to an end located in an opposite direction in which the first connection part is located; A plurality of dummy patterns serving to prevent light transmission; A second substrate facing the first substrate; Liquid crystal layer interposed between the first and second substrate COG type liquid crystal display device comprising a. The method of claim 1, And the plurality of dummy patterns have the same wiring form as that of the signal connection wiring, or a bar or plate form. The method of claim 2, And the plurality of dummy patterns are formed of the same material on the same layer as the signal connection line. The method of claim 1, In the display area of the first substrate, a gate wire connected to the gate pad terminal, a data wire connected to the data pad terminal, a thin film transistor connected to the gate and the data wire, and a pixel electrode connected to the thin film transistor are further included. And a color filter layer and a common electrode corresponding to the display area on the second substrate. A substrate in which a display area and a first non-display area having a gate pad terminal formed therein and a second non-display area having a data pad terminal defined therein are defined; A plurality of gate driver integrated circuits in a chip form spaced apart from each other and mounted in the first non-display area on the substrate; A plurality of data driver integrated circuits in chip form spaced apart from each other and mounted in the second non-display area on the substrate; A first connection part spaced apart from the first non-display area by a first distance in the second non-display area and electrically connected to and mounted in the plurality of data driving integrated circuits and the plurality of driving gate driving integrated circuits; A second connection part electrically connected to the plurality of data driving integrated circuits, the second connection part being spaced apart from the first non-display area by a second distance greater than a first distance from the first non-display area; A flexible printed circuit (FPC) electrically connected to the first connector and the second connector; A plurality of signal wirings electrically connected to the first connection portion in an area between the first non-display area and the second non-display area and between the first non-display area and the first connection portion; A first area between the first connection part and the second connection part closest to the second non-display area, and a second area from the second connection part to an end located in an opposite direction in which the first connection part is located; Multiple dummy patterns serving to prevent light transmission Array substrate for a COG type liquid crystal display device comprising a.

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