KR20090045695A - High integrated semiconductor memory apparatus - Google Patents

Abstract

The present invention provides a semiconductor memory device that can reduce the area and power consumption of the internal circuit. A semiconductor memory device according to the present invention includes a decoding unit for decoding contents of a mode register set corresponding to an external command, an internal clock having the same period as that of a system clock, and an increased period, and an increased period corresponding to an output of the decoder. A clock generator for generating an internal pulse, a timing controller for shifting a phase of an internal command signal by a predetermined period in response to the output of the decoder, and a timing controller in response to an output of the decoder Selecting one includes a selection unit for determining the activation time of the internal operation corresponding to the external command. Accordingly, the present invention provides a circuit for determining the activation time of the precharge operation in response to the time required for the operation and the operating environment to automatically execute the precharge operation after the operation corresponding to the externally input command is performed. Can reduce the area.

Semiconductor, Precharge, tWR (Write Recovery Time), Memory Device, Divider

Description

Highly Integrated Semiconductor Memory Device {HIGH INTEGRATED SEMICONDUCTOR MEMORY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, wherein a configuration and control method capable of reducing the size of a timing control circuit for controlling a time point for performing an internal operation before and after an active operation for reducing power consumption and applying the same to a highly integrated semiconductor memory device. It is about.

In a system composed of a plurality of semiconductor devices, the semiconductor memory device is for storing data. When data is requested from a data processing device such as a central processing unit (CPU), the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or at a position corresponding to the address. Stores data provided from the data requesting device.

As the operating speed of a system composed of semiconductor devices has increased and the technology related to semiconductor integrated circuits has been developed, semiconductor memory devices have been required to output or store data at a higher speed. To store more data and operate at higher speeds, semiconductor memory devices have become smaller, more integrated, and power supply voltages have gradually decreased.

A commonly used semiconductor memory device first outputs data from a plurality of unit cells connected to a word line activated through an active command to read data stored in one unit cell, detects and amplifies the data, and then selects them through a column read command. Output to the outside. At this time, the unit cell size of the highly integrated semiconductor memory device is designed to be very small, so that the amount of charge corresponding to the data stored in the capacitor in the unit cell is not large. Therefore, a very small potential corresponding to the data stored in the unit cell corresponding to the activated word line is output to the bit line, and the sense amplifier senses and amplifies it. Here, the sense amplifier is connected to a pair of bit lines, and when data is applied to one of the pair of bit lines, the sense amplifier senses a voltage difference from the other.

Typically, the bit line is precharged to a level of 1/2 supply voltage (or core voltage) before data is applied. The level of precharge is a level when one of a pair of bit lines receives data from a unit cell and a potential difference occurs with the other. The ground voltage or the supply voltage is used as a precharge voltage according to a semiconductor memory device. Sometimes. After the semiconductor memory device executes an active operation in response to an externally input command and an address, the potential of each pair of bit lines becomes uneven according to the value of the output data, which corresponds to the next command. Makes it difficult to perform. Therefore, after the active operation, the equalization unit and the precharge unit connected to the pair of bit lines are controlled to make the potential of each bit line uniform and again to have a constant precharge level. This series of operations is called a precharge operation.

In order to execute the precharge operation immediately after the active operation is performed, the semiconductor memory device uses an auto precharge signal indicating a time point for performing the precharge operation. Here, the auto precharge signal should be deactivated when the active operation starts and activated when the active operation ends, and the activation is determined by the precharge timing control circuit included in the semiconductor memory device.

1 is a block diagram illustrating a general semiconductor memory device.

As illustrated, the semiconductor memory device includes a decoder 120, a clock generator 140, a timing controller 160, a selector 180, and a command decoder 190. When the semiconductor memory device receives the write command, it performs an active operation through the command decoder and the address decoder, and activates the auto precharge command APCGCMD to proceed with the precharge operation after the active operation. The timing controller 160 receiving the auto precharge command APCGCMD checks the timing until the semiconductor memory device finishes the active operation, and then the auto precharge signal according to the preset specifications in the semiconductor memory device. APCG_WT) is output to the bank in which the active operation was performed.

In detail, when the write command is input, the write clock state signal WCLKON which becomes active when the write command is input and the contents (MRS_a <0: 3>) related to the write operation of the mode register set MRS are input to the decoding unit 120. do. When the write clock state signal WCLKON is activated, the decoding unit 120 selects the signal LSB <0: 3> for selecting the timing of the auto precharge signal APCG_WT and the auto precharge signal APCG_WT. The phase change select signal MSB <0: 2> for controlling the degree to which the phase is changed, and the write clock select signal WCLK_MSB <0: 2> corresponding to the write operation are output. The clock generator 140 receiving the write clock selection signal WCLK_MSB <0: 2> receives a clock rising pulse CLKRP corresponding to the rising edge of the system clock input from the outside and a clock corresponding to the falling edge of the system clock. Outputs a number of internal clocks CLKRPD, CLKFPD, CLKRPD_MSB <0: 2>, CLKFPD_MSB <0: 2>, CLKRPD_RD, CLKFPD_RD to receive the polling pulse CLKFP to shift the phase of the auto precharge signal APCG_WT. do.

The timing controller 160 shifts the phase of the auto precharge command APCGCMD activated in response to the write command based on the output of the clock generator 140, and changes the phase change select signal MSB <0: 2>. To determine the degree of phase shift. When the degree of phase shift of the auto precharge command APCGCMD is determined, the timing controller 160 finally outputs a plurality of phase alignment signals IWR <0: 3> having a phase difference of one clock from the determined degree. . The selector 180 that receives the plurality of phase alignment signals IWR <0: 3> selects an auto precharge signal by selecting one according to the selection signal LSB <0: 3> output from the decoder 120. The output will be (APCG_WT).

FIG. 2 is a block diagram illustrating the decoding unit 120 illustrated in FIG. 1.

As shown, the decoding unit 120 includes a first decoder 122, a first multiplexer 124, and a second multiplexer 126. The contents (MRS_a <0: 3>) related to the write operation of the mode register set (MRS) input to the decoding unit 120 are divided into three bits (MRS_a <0: 2>) in which a burst length is defined and a burst. It consists of 1 bit that defines the type (Burst Type). As is well known to those skilled in the art, the burst length refers to the number of data output at one time and the burst type is used to determine whether to continuously output or use an interleaving scheme. The first decoder 122 outputs the selection signal LSB <0: 3> corresponding to the burst length to the selector 180, and the first multiplexer 124 changes the phase in response to the burst length and the burst type. The select signal MSB <0: 2> is output to the timing controller 160, and the second multiplexer 126 corresponds to the write clock state signal WCLKON to write signal select signal WCLK_MSB <0: 2>. ) Is output to the clock generator 140.

FIG. 3 is a block diagram illustrating the selector 180 illustrated in FIG. 1.

As illustrated, the selector 180 receives a plurality of phase alignment signals IWR <0: 3> output from the timing controller 160 and selects signals LSB <0 output from the decoder 120. In response to: 3>), one of them is output as the auto precharge signal APCG_WT. Here, since the selector 180 receives four input signals and outputs one of them, the selector 180 may be implemented by using a multiplexer or a transmission gate, and thus a detailed description thereof will be omitted.

4 is a block diagram illustrating the timing adjusting unit 160 shown in FIG. 1.

As illustrated, the timing controller 160 includes a first shift register 162, first to third phase shifters 164A to 164C, and a phase shifter 168.

The first shift register 162 receives the auto precharge command APCGCMD and shifts the phase by two periods of the system clock in response to the internal clocks CLKRPD_RD and CLKFPD_RD output from the clock generator 140. Output the signal B2.

The first movement signal B2 is input to the first to third phase shifters 164A to 164C to move by the clock shift value of each phase shifter. Specifically, the third phase shifter 164C, which receives the first shift signal B2 shifted in phase by two cycles, shifts the phase by four cycles and moves the second shift signal B6 shifted by six cycles in total. One of the first moving signals B2 is selected and output in response to the third phase change selecting signal MSB <2>, and the second phase shifting unit 164B outputs the first phase shifting unit 164C. The ADD8 is shifted again by four periods so that one of the third shift signal B10 and the first shift signal B2 shifted for a total of 6 or 10 cycles is converted to the second phase change select signal MSB <1>. After selecting in correspondence to the < RTI ID = 0.0 >, it outputs to the first phase shifter 164A. Like the first and second phase shifters 164A and 164B, the first phase shifter 164A receives the output ADD4 of the second phase shifter 164B and shifts the phase by four periods for a total of six cycles or One of the fourth movement signal B14 and the first movement signal B2 moved by 14 cycles is selected corresponding to the first phase change selection signal MSB <0> and then output to the phase shifter 168.

Specifically, the first to third phase shifters 164A to 164C each include two shift registers and one multiplexer, and each shift register is clocked in response to a write command from the clock generator 140. The internal clocks (CLKRPD_MSB <0: 2>, CLKFPD_MSB <0: 2>), which are converted from the rising pulse (CLKRP) and the clock polling pulse (CLKFP), can be shifted and outputted by two cycles. Each multiplexer corresponds to a phase shift selection signal MSB <0: 2> output from the decoding unit 120 and one of a signal whose phase is shifted through each of the two shift registers. Outputs

The phase shifter 168 receives the output LAT_B of the first phase shifter 164A, sets the reference time, and outputs four phase alignment signals IWR <0: 3> shifted in phase by one period therefrom. Output The phase shifter 168 includes two shift registers, and each shift register has a phase of the input signal by one cycle using the internal clocks CLKRPD and CLKFPD output from the clock generator 140. It can output two shifted signals.

FIG. 5 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1. The illustrated operation of the semiconductor memory device is described based on the clock rising pulse CLKRP, and the same operation is performed based on the clock falling pulse CLKFP.

When the internal commands (CASP6_WT and WTCMDOUT) are activated in response to the externally written write command, the corresponding auto precharge command (APCGCMD) is activated. Thereafter, the first shift register 162 generates the first shift signal B2 shifted in phase by two periods. The output ADD4 of the second phase shifter 164B input to the first phase shifter 164A is a signal in which the first shift signal B2 is shifted in phase by four periods. As a result, the third phase shifter 164C outputs the first shift signal B2 instead of the second shift signal B6 to the second phase shifter 164B, and as a result, is input to the phase shifter 168. The output LAT_B of the first phase shifter 164A is shifted in phase by 10 cycles. Thereafter, the selection unit outputs the first phase alignment signal IWR <0> as the auto precharge signal APCG_WT by the first selection signal IBS <0> activated at the logic low level.

As described above, in response to an operation and a specification corresponding to an externally input command, the semiconductor memory device may store some information of the external command and the mode register set MRS in order to determine when to execute a precharge operation corresponding to the command. It has a circuit that determines the time point corresponding to the result after receiving and decoding it. However, if the write recovery time (tWR) of the externally input write operation is 16 ns and the system clock has a period of 2 ns, eight shift registers in the timing controller 160 are required and the system clock is 1 ns. 4, the timing adjusting unit 160 shown in FIG. 4 requires 16 shift registers. That is, the timing adjusting unit for calculating the activation time included in the conventional semiconductor memory device according to the operating speed and the internal specification requires more components, thereby greatly increasing the area and power consumption.

The present invention can reduce the area and power consumption of the internal circuit by dividing the system clock for determining the operation speed at a constant division rate less than 1 to determine the activation time of the internal operation in order to solve the above-mentioned conventional problems. It is a feature to provide a semiconductor memory device.

According to the present invention, a decoding unit for decoding contents of a mode register set corresponding to an external command, divides an internal clock having the same period as the system clock, increases the period, and generates an internal pulse having an increased period corresponding to the output of the decoding unit. Selects one of a clock generator, a timing controller for shifting the phase of the internal command signal by a predetermined period in response to the output of the decoder, and an output of the timing controller in response to the output of the decoder. A semiconductor memory device including a selection unit for determining an activation time point of an internal operation corresponding to a command is provided.

The present invention also divides an instruction decoder for generating an auto precharge command in response to a write command, a decoder for decoding the contents of a mode register set corresponding to the write command, and an internal clock having the same period as the system clock. A clock generator for increasing an interval and generating an internal pulse having an extended period corresponding to an output of the decoding unit, and for shifting a phase of the auto precharge command by a predetermined period using the internal pulse in response to an output of the decoding unit A semiconductor device includes a timing controller and a selector configured to select one of an output of the timing controller corresponding to an output of the decoder to determine an activation time of an auto precharge operation corresponding to a write command.

In a conventional semiconductor memory device, in performing an auto precharge operation using a pulse activated after a predetermined time at a time when a command is input from an external device, a plurality of shift registers are used to determine a predetermined time according to a specification and an operation speed. Has been used. As the operation speed of a semiconductor memory device increases, a large number of shift registers are required to shift a phase of a pulse for a predetermined time. In order to reduce the area of the circuit and reduce power consumption, the present invention uses a clock divider. The system clock is divided at a division rate of 1 or less to increase the period, and then used to determine when to activate the auto precharge operation.

The present invention divides a system clock supplied to a semiconductor memory device into 1/2 to determine an activation time of an internal operation, thereby shifting a phase to shift a phase compared to a case of determining an activation time using an existing system clock. Reducing the number of resistors has the advantage of reducing the area and power consumption.

Specifically, when the precharge operation is performed on the bit line using the clock divider in the semiconductor memory device, the present invention operates to automatically execute the precharge operation after the operation corresponding to the externally input command is performed. The area of the circuit for determining the activation time of the precharge operation can be reduced according to the time required and the operating environment.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

As illustrated, the semiconductor memory device may include a decoding unit 620 for decoding the contents (MRS_a <0: 3>) of the mode register set corresponding to an external command, and an internal clock CLKRP having the same period as the system clock. Clock generator 640 and decoder 620 for generating the internal pulses CLKRPD_MSB_2X <0: 2> and CLKFPD_MSB_2X <0: 2> having a longer period by dividing to increase the period and corresponding to the output of the decoding unit. Timing control unit for moving the phase of the internal command signal APCGCMD in response to (MSB <0: 2>) by a predetermined period using internal pulses CLKRPD_MSB_2X <0: 2> and CLKFPD_MSB_2X <0: 2> 660, and an internal operation corresponding to an external command by selecting one of the outputs IWR <0: 3> of the timing controller 660 in response to the outputs LSB <0: 3> of the decoding unit 620. It includes a selection unit 680 for determining the activation time of the.

More specifically, in the embodiment of the present invention, a write command WT is applied to the semiconductor memory device as an external command and a precharge operation is performed after an internal operation corresponding to the write command is performed. The semiconductor memory device further includes a command decoder 690 for generating an internal command signal APCGCMD for indicating a precharge operation after the data access operation in response to the write command. Here, the command decoder 690 uses an internal command signal CAT8 using an address so that the data access can be made with the data access write pulse CASP6_WT generated internally in response to the write command WT. Create (APCGCMD). The internal command signal (APCGCMD) is a signal that is derived from an active operation, not a separate external command for instructing the precharge operation. The internal command signal (APCGCMD) is activated after a time required for data access and performs an auto precharge operation. It is the basis for generating the charge signal APCG_WT.

Herein, the contents of the mode register set MRS_a <0: 3> input to the decoding unit 620 may be set to a burst length and a burst type that are set in relation to the write command WT. to be. As is well known to those skilled in the art, a burst length means a length in which data is continuously input, and a burst type means whether data is input / output in one cell region or interleaved in multiple cell regions. do.

According to the present invention, operations of the decoder 620, the command decoder 690, and the selector 680 for generating the auto precharge signal APCG_WT by shifting the phase of the internal command signal APCGCMD by a predetermined time may be described. Similar to the prior art, but differs in the method and configuration of shifting the phase of the internal command signal APCGCMD to generate the auto precharge signal APCG_WT, and the area of the control circuit required to generate the auto precharge signal APCG_WT. And reducing power consumption. In particular, in order to shift the phase of the internal command signal APCGCMD, the clock generator 640 receives the internal pulses CLKRPD_MSB_2X <0: 2> and CLKFPD_MSB_2X <0: 2>, which have twice the period of the system clock. This allows the timing controller 660 to be implemented in a smaller area than the prior art.

Although the period of the internal pulses CLKRPD_MSB_2X <0: 2> and CLKFPD_MSB_2X <0: 2> is twice as long as the period of the system clock, the present invention has been described with reference to the operating environment of the semiconductor memory device. Implementation may change. However, the period of the internal pulses CLKRPD_MSB_2X <0: 2> and CLKFPD_MSB_2X <0: 2> should be at least shorter than the write recovery time tWR specified by the specification of the semiconductor memory device.

FIG. 7 is a block diagram illustrating the clock generator 640 shown in FIG. 6.

As shown, the clock generator 640 divides the internal clock CLKRP at a predetermined frequency division ratio to generate a plurality of source pulses CLKRP_2X and CLKRP_2XB, each of which phases are complementary to each other, and decoding. In response to the output (WCLK_MSB <0: 2>) of the unit 620, a plurality of source pulses CLKRP_2X and CLKRP_2XB are converted into the internal pulses CLKRPD_MSB_2X <0: 2> and CLKFPD_MSB_2X <0: 2> for output. And a clock generator 644.

Here, the frequency division rate of the clock generator 640 is 1/2, so that the period of the plurality of source pulses CLKRP_2X and CLKRP_2XB is twice the period of the internal clock CLKRP having the same period as the system clock. The clock generator 644 receiving the plurality of source pulses CLKRP_2X and CLKRP_2XB receives a plurality of internal clocks CLKRPD and CLKRPD_MSB_2X <0: 2 corresponding to one source pulse CLKRP_2X. And generate a plurality of other internal clocks (CLKFPD, CLKFPD_MSB_2X <0: 2>) corresponding to the falling edge of the system clock in response to another source pulse (CLKRP_2XB). many

FIG. 8 is a block diagram illustrating the timing controller 660 of FIG. 6.

As shown in the drawing, the timing adjusting unit 660 shifts the first command signal A2 whose phase is shifted by two periods in response to the internal command signals APCGCMD in response to the internal pulses CLKRPD and CLKFPD. First to third phase shifts for outputting a phase shifted signal by receiving the first shift signal A2 in response to the register 662 and the output MSB <0: 2> of the decoding unit 620. Frequency change for outputting a plurality of phase alignment signals IWR <0: 3> whose phases are shifted by one cycle of the sections 664A to 664C and the output LAT_A of the first phase shifter 664A in sequence. Section 668.

Specifically, the first to third phase shifters 664A to 664C of the signal input using the internal pulses CLKRPD_MSB_2X <0: 2> and CLKFPD_MSB_2X <0: 2> output from the clock generator 640. Selecting and outputting one of the shifted phase shifting signal and the shifted phase shifted signal and the shifted phase shifted signal corresponding to the output MSB <0: 2> of the decoding unit 620 It contains one multiplexer. Each of the first to third phase shifters 664A to 664C may generate a signal shifted in phase by four periods of the input signal, and four periods corresponding to the output of the decoding unit from the first shift signal A2. Outputs a signal selectively shifted in phase by one of 8 cycles, and 12 cycles.

That is, the third phase shifter 664C receives the first shift signal A2 to generate a signal shifted in phase by 4 cycles, and corresponds to the output MSB <2> of the decoder 620. One of the first shifted signal A2 and the shifted phase is output as the second shifted signal A6 to the second phase shifter 664B. Accordingly, the second movement signal A6 means a signal in which the internal command signal APCGCMD is shifted in phase by two or six cycles. Similarly, the second phase shifter 664B receives the second shift signal A6 to generate a signal further shifted in phase by 4 cycles, and corresponds to the output MSB <1> of the decoder 620. One of the first shifted signal A2 and the shifted phase is output as the third shifted signal A10 to the first phase shifter 664A. Accordingly, the third movement signal A10 refers to a signal in which the internal command signal APCGCMD is shifted in phase by 2 cycles, 6 cycles, or 10 cycles. The operation of the first phase shifter 664A is similar, so that the output LAT_A of the first phase shifter 664A is phased by two, six, ten, or fourteen cycles of the internal command signal APCGCMD. This is a moved signal.

In this process, shift registers have been conventionally used as many phase shifts of the system clock have increased, which increases the area in the highly integrated semiconductor memory device and increases the power consumed. On the other hand, the present invention can reduce the number of shift registers by increasing the period of the clock used in the shift register by a certain ratio longer than the period of the system clock, thereby reducing the area occupied by the circuit for internal operation control and reducing power consumption.

9 is a block diagram illustrating the frequency changer 668 illustrated in FIG. 8.

As shown, the frequency changer 668 is an internal pulse output from the output LAT_A and the clock generator 640 of the first phase shifter 664A, specifically, output from the clock divider 642. Input phase outputting the signal A15 whose phase is shifted by one cycle by performing a logic operation on the source pulse CLKRP_2X, and two phase alignment signals IWR <0: 1 whose phase is shifted by one cycle relative to the output of the input stage. A second shift register for outputting >) and a third shift for outputting the other two phase alignment signals IWR <2: 3> shifted in phase by one period compared to the output of the second shift register Contains registers

The frequency changer 668 doubles the pulse width of the access write pulse CASP6_WT in response to the write command WT while shifting a phase using an internal pulse having a doubled period, and the minimum interval between commands ( In order to prevent the collision caused by tCCD), it is returned to the original pulse width and outputs a phase alignment signal IWR <0: 3> having a pulse width of 1 tCK.

FIG. 10 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 6.

In the circuit operation of the present invention, if the write recovery time tWR is 12, the write enable signal indicating whether the write operation is activated and the contents (MRS_a <0: 3>) of the mode register set corresponding to the external command are activated. The WCLKON is input to generate internal pulses CLKRP_2X, CLKRP_2XB, CLKRPD_MSB_2X <0: 2> and CLKFPD_MSB_2X <0: 2> through the clock generator 640. The internal operation signal APCGCMD corresponding to the output write pulse CASP6_WT and the internal information CAT8 utilizing the address in response to the outputs MSB <0: 2> and LSB <0: 2> of the decoding unit 620. Phase shift using internal pulses CLKRP_2X, CLKRP_2XB, CLKRPD_MSB_2X <0: 2>, CLKFPD_MSB_2X <0: 2>. During the phase shift, the first to third shift signals A2, A6, and A10 having a pulse width of 2 tCK are generated, but the phase alignment signal IWR <0 having a pulse width of 1 tCK through the last frequency changer 668. : 3) is output. Through this operation, the auto precharge signal APCG_WT may be activated after the write recovery time tWR has passed.

The present invention significantly reduces the number of shift registers for shifting phase compared to the prior art. For example, the number of shift registers may be reduced from 40 to 25 when applied to a semiconductor memory device (for example, GDDR5) that operates at a high speed having a bank address of 4 bits and a write recovery time tWR of 19. . At this time, the circuit area of 15 shift registers is reduced. Furthermore, since the signals are doubled and used for phase shifting, even in a semiconductor memory device operating at a high speed, the operating margin for phase shifting can be sufficiently ensured, and the number of signals toggling is reduced, resulting in current consumption, In other words, the power consumption is reduced. Furthermore, the number of shift registers can be reduced by using a signal whose cycle is tripled with the division ratio of 1/3 according to the operating environment of the semiconductor memory device.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a block diagram illustrating a general semiconductor memory device.

FIG. 2 is a block diagram illustrating the decoding unit shown in FIG. 1.

FIG. 3 is a block diagram illustrating the selector illustrated in FIG. 1.

FIG. 4 is a block diagram illustrating the timing controller shown in FIG. 1.

FIG. 5 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1.

6 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

FIG. 7 is a block diagram illustrating the clock generator illustrated in FIG. 6.

FIG. 8 is a block diagram for explaining a timing controller shown in FIG. 6.

FIG. 9 is a block diagram illustrating the frequency changer illustrated in FIG. 8.

FIG. 10 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 6.

Claims (18)

A decoding unit for decoding the contents of the mode register set corresponding to the external command; A clock generator for dividing an internal clock having the same period as a system clock to increase the period and to generate an internal pulse having an extended period corresponding to the output of the decoding unit; A timing adjusting unit for shifting a phase of an internal command signal by a predetermined period in response to an output of the decoding unit by using the internal pulse; And And a selector configured to select one of the outputs of the timing adjuster corresponding to an output of the decoder to determine an activation time of an internal operation corresponding to the external command. In claim 1, And a command decoder for generating the internal command signal in response to the external command. The method of claim 1, The clock generator A clock divider for dividing the internal clock at a constant division rate to generate a plurality of source pulses having phases complementary to each other; And And a clock generation unit configured to convert the plurality of source pulses into the internal pulses and output the internal pulses in response to the output of the decoding unit. The method of claim 1, Wherein the period of the internal pulse is twice the period of the system clock. The method of claim 4, wherein The timing adjusting unit A first shift register configured to output a first shift signal whose phase is shifted by two periods in correspondence to the inner pulse; First to third phase shifters configured to receive the first shift signal and output a phase shifted signal corresponding to an output of the decoder; And A frequency changer for outputting a plurality of phase alignment signals whose phases are shifted by one cycle of the output of the first phase shifter sequentially; And the first to third phase shifters are each composed of one shift register and one multiplexer for shifting a phase using the internal pulses. The method of claim 5, Each of the first to third phase shifters may generate a signal shifted in phase by four periods of the input signal, and one of four periods, eight periods, and twelve periods corresponding to the output of the decoding unit from the first shift signal. A semiconductor memory device, characterized in that for outputting a signal selectively shifted in phase. The method of claim 5, The frequency changer An input terminal for performing a logic operation on the output of the first phase shifter and the internal pulse to output a signal shifted in phase by one period; A second shift register for outputting two phase alignment signals shifted in phase by one period relative to the output of the input terminal; And And a third shift register for outputting two other phase alignment signals whose phases are shifted by one cycle again with respect to the output of the second shift register. The method of claim 1, And the contents of the mode register set are burst length and burst type. The method of claim 1, Wherein the external command is a write command and the internal operation is a precharge operation. The method of claim 9, Wherein the period of the internal pulse is more than twice the period of the system clock and shorter than the write recovery time (tWR). A command decoder for generating an auto precharge command in response to a write command; A decoding unit for decoding contents of a mode register set corresponding to the write command; A clock generator for dividing an internal clock having the same period as a system clock to increase the period and to generate an internal pulse having an extended period corresponding to the output of the decoding unit; A timing adjusting unit for shifting a phase of the auto precharge command by a predetermined period in response to an output of the decoding unit by using the internal pulse; And And a selector configured to select one of the outputs of the timing adjuster corresponding to an output of the decoder to determine an activation time of an auto precharge operation corresponding to the write command. The method of claim 11, The clock generator A clock divider for dividing the internal clock at a constant division rate to generate a plurality of source pulses having phases complementary to each other; And And a clock generation unit configured to convert the plurality of source pulses into the internal pulses and output the internal pulses in response to the output of the decoding unit. The method of claim 11, Wherein the period of the internal pulse is twice the period of the system clock. The method of claim 13, The timing adjusting unit A first shift register configured to output a first shift signal whose phase is shifted by two periods in correspondence to the inner pulse; First to third phase shifters configured to receive the first shift signal and output a phase shifted signal corresponding to an output of the decoder; And A frequency changer for outputting a plurality of phase alignment signals whose phases are shifted by one cycle of the output of the first phase shifter sequentially; And the first to third phase shifters are each comprised of one shift register and one multiplexer for shifting a phase with respect to the internal clock. The method of claim 14, Each of the first to third phase shifters may generate a signal shifted in phase by four periods of the input signal, and one of four periods, eight periods, and twelve periods corresponding to the output of the decoding unit from the first shift signal. A semiconductor memory device, characterized in that for outputting a signal selectively shifted in phase. The method of claim 14, The frequency changer An input terminal for performing a logic operation on the output of the first phase shifter and the internal pulse to output a signal shifted in phase by one period; A second shift register for outputting two phase alignment signals shifted in phase by one period relative to the output of the input terminal; And And a third shift register for outputting two other phase alignment signals whose phases are shifted by one cycle again with respect to the output of the second shift register. The method of claim 11, And the contents of the mode register set are burst length and burst type. The method of claim 11, Wherein the period of the internal pulse is more than twice the period of the system clock and shorter than the write recovery time (tWR).

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