KR20090045568A - Multi-port memory device having serial i/o interface - Google Patents

Abstract

In the present invention, a port reset operation is performed by applying a voltage level corresponding to the digital logic (0 or 1) through an external pin in a specific mode. At this time, the specific mode is entered as an external port reset mode through MRS (Mode Register Set) setting. While in this external port reset mode, the original internal port reset signal is disabled and the external pins are used for port reset only. Here, the external pins are connected one-to-one with each port, and multiple parallel data inputs and supports so-called Direct Test Mode (DTM), which directly test the memory core without going through the port logic of the multi-port memory device. The output (DQ) pin can be used as an external pin. During external port reset mode, applying a voltage level corresponding to a port reset to an external pin causes a port reset operation on that port. In this way, by applying the voltage level corresponding to the digital logic, it is possible to check all the operations that can be checked when the port reset operation is performed regardless of the port threshold voltage level.

Multi-Port Memory, Serial Input / Output Interface, Port Reset, External Pins, Multiplexers

Description

MULTI-PORT MEMORY DEVICE HAVING SERIAL I / O INTERFACE

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and more particularly, to a multi-port memory device having a serial input / output interface, and more particularly to a port reset operation.

In general, most memory devices, including random access memory (RAM), have one port, with multiple input / output pins on one port. That is, only one port is provided for data exchange with an external chipset. Such a single port memory device uses a parallel input / output interface that simultaneously transmits multiple bits of data through signal lines connected to multiple input / output pins. That is, data is exchanged in parallel with an external device through a plurality of input / output pins.

The input / output interface described above refers to an electrical and mechanical handling method for connecting transmission / reception data to the other party by connecting unit elements having different functions with signal lines. The input / output interface described below is also the same. It should be interpreted as meaning. In addition, the signal line generally refers to a bus for transmitting signals such as an address signal, a data signal, a control signal, and the like.

The parallel input / output interface can transfer multiple bits of data through multiple buses simultaneously, so it is used for short distances requiring high speed because of its high data processing efficiency (speed). However, the parallel input / output interface has an increased bus for transmitting input / output data, and thus, a long distance increases a product cost. In addition, in terms of hardware of a multi-media system, due to the limitation of a single port, in order to support various multimedia functions, a plurality of memory devices may be independently configured or one function may be used. There is a disadvantage in that the operation of other functions cannot be performed at the same time when the operation is performed.

Considering the shortcomings of the parallel input / output interface described above, efforts have been made to convert the input / output interface to the serial input / output interface, and also consider the expansion of compatibility with devices having other serial input / output interfaces. Therefore, the input / output environment of the semiconductor memory device is required to switch to the serial input / output interface. In addition, display devices, such as HDTV (High Definition TeleVision) and LCD (Liquid Crystal Display) LCDs, have built-in applications such as audio and video, and these applications are independent. Since in-data processing is required, the development of a multi-port memory device having a serial input / output interface through a plurality of ports is urgently required.

Currently, in the multi-port memory device having the proposed serial input / output interface, a processor for processing serial input / output signals and a DRAM core for performing parallel low-speed operation like a general-purpose DRAM device have the same wafer. It is implemented in one chip.

1 is a block diagram showing the configuration of a multi-port memory device having a serial input / output interface. For convenience of explanation, a multi-port memory device including two ports PORT0 and PORT1 and four banks BANK0 to BANK3 will be described as an example.

Referring to FIG. 1, a multi-port memory device having a serial input / output interface may include serial input / output pads TX +, TX-, RX +, and RX-, ports PORT0 and PORT1, and banks BANK0 to BANK3. It consists of a global data bus.

In the multi-port memory device having such a configuration, input signals (hereinafter referred to as input valid data signals) input from the ports PORT0 and PORT1 are input to all banks BANK0 to BANK3, and the banks BANK0 to Output signals output from BANK3) (hereinafter referred to as 'output valid data signals') must also be configured to be selectively transmitted to all ports PORT0 and PORT1.

For this purpose, the ports PORT0 and PORT1 and the banks BANK0 to BANK3 are connected to each other through the global data bus GIO. The global data bus is an input bus (PRX0 <0: 3>, PRX1 <0: 3>) for transferring input valid data signals transmitted from the ports PORT0 and PORT1 to the banks BANK0 to BANK3, and the bank ( An output bus (PTX0 <0: 3>, PTX1 <0: 3>) for transferring the output valid data signal transmitted from BANK0 to BANK3 to the ports PORT0 and PORT1.

In this way, the global data bus is separated into input buses PRX0 <0: 3> and PRX1 <0: 3> and output buses PTX0 <0: 3> and PTX1 <0: 3>. The input buses PRX0 <0: 3> and PRX1 <0: 3> transfer the parallel input valid data signals transmitted from the respective ports PORT0 and PORT1 to the respective banks BANK0 to BANK3. The output buses PTX0 <0: 3> and PTX1 <0: 3> transfer the parallel input valid data signals transmitted from the banks BANK0 to BANK3 to each port PORT0 and PORT1.

On the other hand, the input valid data signals outputted from the ports PORT0 and PORT1 also contain information on the bank selection signal for selecting the banks BANK0 to BANK3. Signals informing the data of which bank is being accessed are input. Accordingly, the data of the port is selectively transferred into the bank, and the data of the bank is transferred to the global data bus assigned to each port.

The ports PORT0 and PORT1 convert the signals input to the serial high speed receiving pads RX + and RX- into parallel input valid data signals, which are low-speed data communication methods, so that the input buses PRX0 <0: 3> and PRX1 <0 (3>) is transferred to the DRAM core areas of the banks BANK0 to BANK3, and the serialized output valid data signal outputted from the DRAM cores of the banks BANK0 to BANK3 is a high-speed data communication serialized signal. And a SERDES circuit for switching to and outputting. Here, the sustain circuit includes a serializer and a deserializer.

FIG. 2 is a block diagram illustrating a circuit implementation of the ports PORT0 and PORT1 shown in FIG. 1.

First, as illustrated in FIG. 2, the ports PORT0 and PORT1 perform data communication with an external device through a serial input / output interface method through serial input / output pads TX +, TX-, RX +, and RX-. In this case, the signals input through the reception pads RX + and RX- are serial high-speed input signals, and the signals output through the transmission pads TX + and TX- are also high-speed serial output signals. In general, high-speed I / O signals are composed of differential signals for smooth signal recognition, and serial input / output pads TX +, TX-, RX +, and RX- that respectively input and output these differential input / output signals are '+', Separated with '-'.

On the other hand, the ports PORT0 and PORT1 are a driver 21, a serializer 22, an input latch 23, a clock generator 24, a sampler 25, A parallelizer 26 and a data output unit 27 are provided.

The driver 21 outputs an output valid data signal serialized and output from the serializer 22 to an external device via the transmission pads TX + and TX-.

The serializer 22 serializes the parallel output valid data signal inputted through the input latch unit 23 in synchronization with an internal clock generated from the clock generator 24, and outputs the serialized output valid data signal to the driver 21.

The input latch unit 23 is output through the output bus PTXi <0: 3> (where i is 0 or 1, corresponding to the port) in synchronization with the internal clock generated from the clock generator 24. The output valid data signal is latched and transferred to the serializer 22.

The sampler 25 samples an external signal input from the external device through the reception pads RX + and RX- from the external device in synchronization with the internal clock generated by the clock generator 24, and transfers the external signal to the parallelizer 26. .

The parallelizer 26 synchronizes an external signal input through the sampler 25 in synchronization with an internal clock generated from the clock generator 24, and transfers the input valid data signal to the data output unit 27.

The data output unit 27 receives an input valid data signal input from the parallelizer 26 and loads it on an input bus PRXi <0; 3> (where i is 0 or 1, corresponding to the port). send.

The clock generator 24 receives a reference clock RCLK input from an external device and generates an internal clock. In this case, the internal clock may have the same period and phase as the reference clock RCLK, or may be a clock in which the period and / or phase are changed. In addition, the clock generator 24 may generate one internal clock or at least two internal clocks having different periods and phases using the reference clock RCLK.

The operation characteristics of the ports PORT0 and PORT1 having such a configuration will be described in detail as follows.

First, a process in which an external signal inputted at high speed in the form of a serial frame from an external device through the receiving pads RX + and RX- is carried on the input bus PRXi <0: 3>.

First, the external signal is sampled through the sampler 25 synchronized with the internal clock output from the clock generator 24. The sampler 25 transfers the sampled external signal to the parallelizer 26. The parallelizer 26, like the sampler 25, synchronizes an external signal input through the sampler 25 in synchronization with an internal clock output from the clock generator 24, and converts the parallel input effective data signal into a data output unit ( 27). The data output unit 27 carries the parallel input valid data signal outputted from the parallelizer 26 to the input bus PRXi <0: 3>.

Meanwhile, a process of converting the parallelized output valid data signal output through the output buses PTXi <0: 3> into serialized signals and outputting them to an external device through the transmission pads TX + and TX- will be described.

First, the parallelized output valid data signal is transmitted to the input latch unit 23 via the output buses PTXi <0: 3>. The input latch unit 23 latches and outputs the output valid data signal transmitted from the output buses PTXi <0: 3> to the serializer 22 in synchronization with the internal clock output from the clock generator 24. Similar to the input latch unit 23, the serializer 22 serializes the output valid data signal transmitted from the input latch unit 23 in synchronization with the internal clock output from the clock generator 24 to the driver 21. To pass. The driver 21 receives the serialized signal through the serializer 22 and outputs the serialized signal to the external device through the transmission pads TX + and TX-.

As described above, the multi-port memory device has a port having a function as a switching device for performing serial input / output operation at high speed with an external device and converting input / output signals input / output to / from the external device in parallel / parallel. Doing. Such a port is an essential element for performing a plurality of parallel processing with an external device and has a great influence on the operating characteristics of a multi-port memory device.

Meanwhile, the voltage level difference between the input signals rx + and rx- applied to the receiving pads RX + and RX- is defined as a port offset voltage, and the port offset voltage corresponding to the boundary point causing the port reset operation is defined as a port threshold. This is defined as the threshold voltage.

Inherently, the port reset operation occurs only when the port offset voltage is lower than the port threshold voltage. However, if the port threshold voltage is set too high due to process / design problems, the port reset operation may always occur even with a normal port offset voltage. In this case, the test environment that can give only a limited voltage level can not test any more, so the operation that can be confirmed only after the port reset operation cannot be confirmed, which is disadvantageous when the chip revision operation is performed.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a multi-port memory device having a serial input / output interface capable of eliminating an unstable port reset operation during a test.

According to an aspect of the present invention for achieving the above technical problem, a plurality of serial input / output port for receiving a differential port input signal and outputs a differential port output signal; Mode register set decoding means for decoding a mode register set code to output an external port reset mode signal; A plurality of external pins for transmitting internally applied level signals; In response to the external port reset mode signal, an external port reset signal applied through each external pin or an internal port reset signal generated from each serial input / output port is selectively output to each serial input / output port as a final port reset signal. A multi-port memory element having a serial input / output interface having a plurality of multiplexing means for providing is provided.

In addition, according to another aspect of the present invention, a plurality of serial input / output ports for receiving a differential port input signal and outputs a differential port output signal, and a plurality of external pins for transferring an internally applied level signal A method for driving a multi-port memory device having a serial input / output interface, comprising: decoding a mode register set code to output an external port reset mode signal; Outputting an external port reset signal applied through each external pin to each serial input / output port as a final port reset signal in response to the external port reset mode signal; And selectively outputting an internal port reset signal generated from each serial input / output port to each serial input / output port as a final port reset signal in response to the external port reset mode signal. A method of driving a multi-port memory device having is provided.

In the present invention, a port reset operation is performed by applying a voltage level corresponding to the digital logic (0 or 1) through an external pin in a specific mode. At this time, the specific mode is entered as an external port reset mode through MRS (Mode Register Set) setting. While in this external port reset mode, the original internal port reset signal is disabled and the external pins are used for port reset only. Here, the external pins are connected one-to-one with each port, and multiple parallel data inputs and supports so-called Direct Test Mode (DTM), which directly test the memory core without going through the port logic of the multi-port memory device. The output (DQ) pin can be used as an external pin. During external port reset mode, applying a voltage level corresponding to a port reset to an external pin causes a port reset operation on that port. In this way, by applying the voltage level corresponding to the digital logic, it is possible to check all the operations that can be checked when the port reset operation is performed regardless of the port threshold voltage level.

According to the present invention, an unstable port reset operation can be basically excluded in a test, and thus, even when a normal port reset operation is not performed, it is possible to test operations that can be confirmed only when the port reset is performed.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

3 is a block diagram illustrating a port reset structure of a multi-port memory device according to an embodiment of the present invention.

Referring to FIG. 3, the multi-port memory device according to the present embodiment receives a plurality of serial input / outputs for receiving differential port input signals rx + and rx− and outputting differential port output signals tx + and tx−. The output port (p0, p1, p2, p3), MRS decoder 30 for outputting the external port reset mode signal (ext_prst_mode) by decoding the MRS code (mrs_opcode), and transmits the level signal applied from the outside to the inside A plurality of external pins (d0, d1, d2, d3) and an external port reset signal (dq0i) applied through each external pin (d0, d1, d2, d3) in response to the external port reset mode signal (ext_prst_mode). , dq1i, dq2i, dq3i) or internal port reset signals (prst0_org, prst1_org, prst2_org, prst3_org) generated from each serial input / output port (p0, p1, p2, p3). , multiplexers (32, 3) for output to each serial input / output port (p0, p1, p2, p3) as prst2_new, prst3_new) 4, 36, 38).

Here, a plurality of parallel data input / output (DQ) pins supporting a so-called direct test mode (DTM) may be used as the plurality of external pins d0, d1, d2, and d3. dq0, dq1, dq2, and dq3 represent the input signals of the parallel data input / output (DQ) pins.

4 is a circuit diagram illustrating an embodiment of the multiplexer 32.

Referring to FIG. 4, a general multiplexer circuit including two transmission gates TG1 and TG2 which are selectively turned on, and is a final port reset signal prst0_new when the external port reset mode signal ext_prst_mode is activated to a logic level high. If the external port reset signals dq0i, dq1i, dq2i, and dq3i are output and the external port reset mode signal ext_prst_mode is deactivated to a logic level low, the internal port reset signals prst0_org, prst0_org, prst1_org, and prst2_org are used as the final port reset signals prst0_new. , prst3_org).

Meanwhile, not only the multiplexer 32 corresponding to the port p0 but also other multiplexers 34, 36, and 38 may be implemented in the same circuit configuration.

Hereinafter, the port reset operation will be described using port p0 as an example.

When the external port reset mode signal is not in the external port reset mode, since the external port reset mode signal ext_prst_mode is deactivated to a logic level low, the internal port reset signal prst0_org is selected by the multiplexer 32. Therefore, the port reset operation is determined by the internal port reset signal prst0_org regardless of the external port reset signal dq0i. The internal port reset signal prst0_org is activated to logic level high when the port offset voltage between the differential port input signals rx0 + and rx0- is lower than the port threshold voltage.

On the other hand, in the external port reset mode, since the external port reset mode signal ext_prst_mode is activated at a logic level high, the external port reset signal dq0i is selected by the multiplexer 32. Accordingly, the port reset operation is determined by the external port reset signal dq0i regardless of the internal port reset signal prst0_org. The external port reset signal dq0i is a signal applied through the external pin d0 and performs a port reset operation when activated at a logic level high.

The above operation can be summarized as shown in Table 1 below.

ext_prst_mode prst0_org dq0i port0 reset behavior disable (L) disable (L) don't care X enable (H) O enable (H) don't care disable (L) X enable (H) O

By applying the present embodiment as described above, by providing an alternative port reset operation solution through an external pin, even if a normal port reset is not performed internally, it is possible to test operations that can only be confirmed by the port reset.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the logic used in the above embodiment is inevitably changed to other logic as the polarity of the signal used is changed.

In addition, in the above-described embodiment, the DQ pin for supporting the DTM is used as an external pin, but the present invention also applies to the use of another pin as the external pin.

1 is a block diagram illustrating a configuration of a multi-port memory device having a serial input / output interface.

FIG. 2 is a block diagram illustrating a circuit implementation of the port shown in FIG. 1.

3 is a block diagram illustrating a port reset structure of a multi-port memory device according to an embodiment of the present invention.

4 is a circuit diagram illustrating an embodiment of the multiplexer 32.

* Explanation of symbols for the main parts of the drawings

30: MRS decoder

32, 34, 36, 38: multiplexer

Claims (7)

A plurality of serial input / output ports for receiving differential port input signals and outputting differential port output signals; Mode register set decoding means for decoding a mode register set code to output an external port reset mode signal; A plurality of external pins for transmitting internally applied level signals; In response to the external port reset mode signal, an external port reset signal applied through each external pin or an internal port reset signal generated from each serial input / output port is selectively output to each serial input / output port as a final port reset signal. Multiplexing means for A multi-port memory device having a serial input / output interface having a. The method of claim 1, And the plurality of external pins are a plurality of parallel data input / output (DQ) pins that support a direct test mode. The method according to claim 1 or 2, The plurality of multiplexing means, respectively, A first transmission gate for selectively outputting an external port reset signal applied through an external pin corresponding to a corresponding serial input / output port in response to the external port reset mode signal and its inversion signal; And a second transmission gate for selectively outputting an internal port reset signal generated from the corresponding serial input / output port in response to the external port reset mode signal and its inversion signal. Multi-Port Memory Device. The method of claim 3, And the internal port reset signal is activated when the port offset voltage of the differential port input signal is lower than the port threshold voltage. Has a serial input / output interface having a plurality of serial input / output ports for receiving a differential port input signal and outputting a differential port output signal, and a plurality of external pins for internally transferring a level signal applied from the outside; In the method of driving a multi-port memory device, Decoding the mode register set code and outputting an external port reset mode signal; Outputting an external port reset signal applied through each external pin to each serial input / output port as a final port reset signal in response to the external port reset mode signal; And Selectively outputting an internal port reset signal generated from each serial input / output port in response to the external port reset mode signal to each serial input / output port as a final port reset signal; Method of driving a multi-port memory device having a serial input / output interface comprising a. The method of claim 5, And the plurality of external pins are a plurality of parallel data input / output (DQ) pins that support a direct test mode. The method according to claim 5 or 6, And the internal port reset signal is activated when the port offset voltage of the differential port input signal is lower than the port threshold voltage.

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