KR20090045496A - Method for manufcturing semiconductor device - Google Patents

Method for manufcturing semiconductor device Download PDF

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Publication number
KR20090045496A
KR20090045496A KR1020070111343A KR20070111343A KR20090045496A KR 20090045496 A KR20090045496 A KR 20090045496A KR 1020070111343 A KR1020070111343 A KR 1020070111343A KR 20070111343 A KR20070111343 A KR 20070111343A KR 20090045496 A KR20090045496 A KR 20090045496A
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South Korea
Prior art keywords
forming
film
pattern
semiconductor device
spacer
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KR1020070111343A
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Korean (ko)
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오상록
유재선
조용태
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주식회사 하이닉스반도체
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Priority to KR1020070111343A priority Critical patent/KR20090045496A/en
Publication of KR20090045496A publication Critical patent/KR20090045496A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates to a method of manufacturing a semiconductor device capable of suppressing a threshold voltage variation of a semiconductor device. The method of manufacturing a semiconductor device of the present invention includes the steps of forming a gate pattern on a substrate. ; Forming a spacer insulating film on the entire surface of the resultant including the gate pattern; Forming a sacrificial film on the spacer insulating film; Etching the sacrificial layer and the spacer insulating layer to form a stacked pattern in which spacers and sacrificial layer patterns are stacked on both sidewalls of the gate pattern, and removing the sacrificial layer pattern, and forming a sacrificial layer on the spacer. By preventing the loss of the spacer during the etching process for forming the spacer, it is possible to form a spacer having a uniform thickness in the entire wafer area, thereby suppressing the threshold voltage variation.

Threshold Voltage, Sacrifice, Spacer

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFCTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a manufacturing method of a semiconductor device capable of suppressing a threshold voltage variation of a semiconductor device.

In forming a gate line (ie, a word line) of a semiconductor device, the thickness of the spacer formed on both sidewalls of the gate pattern is an important factor in determining the threshold voltage of the transistor.

Meanwhile, in order to prevent the electrical characteristics of the semiconductor device from deteriorating due to the field concentration of the source and drain regions as the semiconductor device is highly integrated, a semiconductor device having a lightly doped drain (LDD) has been proposed. .

1 is a cross-sectional view showing a semiconductor device having an LDD structure according to the prior art.

Referring to FIG. 1, a semiconductor device according to the related art forms a gate pattern 15 having a gate insulating film 12, a gate conductive film 13, and a gate hard mask film 14 stacked on a substrate 11. Thereafter, the first impurity region 16 is formed on the substrate 11 using the gate pattern 15 as an ion implantation barrier.

Next, after the spacer insulating film is formed on the entire surface of the resultant including the gate pattern 15, the spacer insulating film is selectively etched to form spacers 17 on both sidewalls of the gate pattern 15.

Next, the second impurity region 18 is formed on the substrate 11 on both sides of the spacer 17 using the gate pattern 15 and the spacer 17 as the ion implantation barrier. At this time, the second impurity region 18 has a doping concentration greater than that of the first impurity region 16, and the first impurity region 16 and the second impurity region 18 serve as source and drain regions. .

However, in the above-described prior art, there is a problem in that the thickness of the spacer 17 is not uniformly formed in the entire wafer area depending on the process conditions and the characteristics of the etching apparatus in the etching process for forming the spacer 17. The non-uniform distribution of the thickness of the spacer 17 has a problem of lowering the operation characteristics of the device by varying the threshold voltage of the semiconductor device.

In the case of forming the PMOS transistor and the NMOS transistor in the peripheral circuit region, an ion implantation mask is formed on one side to form the second impurity region 18, and then alternately the PMOS transistor region or the NMOS transistor region. Go through it. Subsequently, in the process of removing the ion implantation mask, the surface of the spacer 17 is exposed to an etching environment, and as a result, the thickness of the spacer 17 is more non-uniformly formed in the entire wafer area, and thus the threshold voltage is changed. This deepening problem occurs.

The present invention has been proposed to solve the above problems of the prior art, to provide a method for manufacturing a semiconductor device that can suppress the threshold voltage fluctuation by uniformly forming the spacer thickness of both sidewalls of the gate pattern in the entire wafer area. The purpose is.

According to one aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a gate pattern on a substrate; Forming a spacer insulating film on the entire surface of the resultant including the gate pattern; Forming a sacrificial film on the spacer insulating film; Etching the sacrificial layer and the spacer insulating layer to form a stacked pattern in which spacers and sacrificial layer patterns are stacked on both sidewalls of the gate pattern, and removing the sacrificial layer pattern.

The sacrificial film may be formed of a metal oxide film, for example, an aluminum oxide film, and the spacer insulating film may be formed of a single film composed of an oxide film or a nitride film, or may be formed of a laminated film in which they are stacked. In this case, the sacrificial layer may be formed to have a thickness smaller than that of the spacer insulating layer.

The forming of the stacking pattern may be performed using a fluorocarbon gas or a mixed gas in which methane fluoride gas and Cl 2 gas are mixed, and may be performed using a high density plasma etching apparatus. In this case, any one device selected from the group consisting of transform coupled plasma (TCP), inductive coupled plasma (ICP), decoupled plasma source (DPS), and electro cyclone resonance (ECR) may be used.

Removing the sacrificial layer pattern may be performed using a buffered oxide etchant (BOE).

Forming a first impurity region on the substrate on both sides of the gate pattern after forming the gate pattern, and forming a second impurity region on the substrate on both sides of the laminated pattern after forming the stacked pattern. It may further include. At this time, the doping concentration of the second impurity region is preferably formed to be larger than the doping concentration of the first impurity region.

In the present invention, by forming a sacrificial film on the spacer, during the etching process for forming the spacer, it is possible to form a spacer having a uniform thickness in the entire wafer area by preventing the loss of the spacer, thereby suppressing the threshold voltage variation It can be effective.

In addition, the present invention forms a sacrificial film on the spacer, thereby preventing the loss of the spacer when removing the ion implantation mask for forming the impurity regions of the PMOS transistor and the NMOS transistor in the peripheral circuit region, thereby preventing the electrical characteristics of the semiconductor device. There is an effect that can prevent this deterioration.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device having an LDD structure according to an embodiment of the present invention.

As shown in FIG. 2A, a gate pattern 25 including a gate insulating film 22, a gate conductive film 23, and a gate hard mask film 24 is formed on the substrate 21. In this case, the gate insulating film 22 may be formed of an oxide film, for example, a silicon oxide film (SiO 2 ) by thermal oxidation.

The gate conductive film 23 is any one selected from the group consisting of a polysilicon film, a metal film such as tungsten (W), a conductive metal nitride film such as titanium nitride (TiN), and a metal silicide film such as tungsten silicide (WSi). It can be formed as a laminated film laminated. For example, the gate conductive film 23 may be formed as a laminated film in which the gate oxide film 22, that is, a silicon oxide film and a polysilicon film having excellent interfacial properties and a tungsten silicide film having excellent electrical conductivity are laminated.

The gate hard mask film 24 may be formed of any one selected from the group consisting of an oxide film, a nitride film, an oxynitride, and a carbon-containing film or a laminated film in which these are stacked. For example, the oxide film may be a silicon oxide film (SiO 2 ), BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), SOG (Spin On Glass) , High Density Plasma Oxide (HDP) or Spin On Dielectric (SOD) can be used, Silicon Nitride (Si3N4) can be used as Nitride, and Amorphous Carbon Layer (ACL) as Carbon-containing. Alternatively, a carbon rich polymer film may be used.

Before the gate pattern 25 is formed, a recess pattern may be formed on the substrate 21 to increase the channel length of the semiconductor device. In this case, the recess pattern may be formed in any one shape selected from the group consisting of a polygon, a bulb type, and a saddle type. Here, the bulb type means a recess pattern having a structure wider than the upper part, and generally the lower part has a round shape. In addition, the saddle type means a recess pattern in which protrusions such as fins are formed on the bottom surface.

Next, the first impurity region 26 is formed on the substrate 21 on both sides of the gate pattern 25 using the gate pattern 25 as an ion implantation barrier. In this case, when forming the PMOS transistor, the first impurity region 26 may include boron (B), and when forming the NMOS transistor, the first impurity region 26 may be phosphorus (P) or arsenic (As). ) May be included.

Next, a spacer insulating layer 27 is formed on the entire surface of the resultant including the gate pattern 25. At this time, the spacer insulating film 27 may be formed of a single film composed of an oxide film or a nitride film, or may be formed of a laminated film in which an oxide film or a nitride film is laminated. The oxide film may be a silicon oxide film (SiO 2 ), BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), SOG (Spin On Glass) , High Density Plasma Oxide (HDP) or Spin On Dielectric (SOD) may be used, and a silicon nitride film (Si 3 N 4 ) may be used as the nitride film.

Next, a sacrificial film 28 is formed on the spacer insulating film 27. In this case, the sacrificial layer 28 is to uniformly form the thickness of the spacer in the entire wafer area during the etching process for forming the subsequent spacers, and may be formed of a metal oxide layer, for example, an aluminum oxide layer (Al 2 O 3 ).

In addition, the sacrificial layer 28 may be formed using an atomic layer deposition (ALD) method, and the sacrificial layer 28 may be formed to have a thickness thinner than that of the spacer insulating layer 27.

As shown in FIG. 2B, the sacrificial layer 28 and the spacer insulating layer 27 are selectively etched to form a stacked pattern in which spacers 27A and a sacrificial layer pattern 28A are stacked on both sidewalls of the gate pattern 25. do. In this case, the etching process may be performed using a front side etching process such as an etch barrier.

Here, the sacrificial film pattern 28A formed on the spacer 27A serves to prevent the spacer 27A from being lost due to process conditions or characteristics of the etching equipment during the etching process. That is, even if the thickness of the sacrificial film pattern 28A is not uniformly formed in the entire wafer area, the spacer 27A may be formed to have a uniform thickness.

Specifically, the etching process may include a spacer insulating layer 27, for example, methane fluoride gas (C x H y F z , x, y, z are natural waters) or carbon fluoride gas (C x F y ,) capable of removing an oxide film or a nitride film. x, y may be performed using a mixed gas mixed with natural water) and a sacrificial film 28, for example, Cl 2 gas capable of removing an aluminum oxide film. In this case, CHF 3 may be used as the methane fluoride gas, and CF 4 may be used as the carbon fluoride gas.

Here, in order to form the spacer 27A having a more uniform thickness, that is, to suppress the loss of the spacer 27A, in particular, the sidewall direction loss of the spacer 27A, a high bias power, for example, A bias power in the range of 100W to 200W can be applied. As a result, the loss of the spacer 27A can be suppressed by improving the vertical etching characteristic during the etching process.

The above etching process is preferably performed in a high density plasma etching apparatus, and as a high density plasma etching apparatus, TCP (Transformer Coupled Plasma), ICP (Inductive Coupled Plasma), DPS (Decoupled Plasma Source) or ECR (ECR) Electron Cyclotron Resonance) can be used.

As shown in FIG. 2C, the second impurity region 29 is formed on the substrate using the gate pattern 25 and the stacked patterns formed on both sidewalls of the gate pattern 25 as ion implantation barriers. In this case, the second impurity region 29 may include boron (B) when forming a PMOS transistor, and may include phosphorus (P) or arsenic (As) when forming an NMOS transistor.

In addition, the doping concentration of the second impurity region 29 may be formed to be greater than the doping concentration of the first impurity region 26, and thus, an LDD including the first impurity region 26 and the second impurity region 29. Source and drain regions having a structure can be formed.

As shown in FIG. 2D, the sacrificial layer pattern 28A is removed. In this case, the sacrificial layer pattern 28A may be removed using BOE (Buffered Oxide Etchant).

Since the sacrificial film pattern 28A is formed of a metal oxide film, for example, an aluminum oxide film, it is preferable to remove the sacrificial film pattern 28A because the interface property between the interlayer insulating film and the spacer 27A to be formed through a subsequent process may be lowered.

On the other hand, in the case of forming the source and drain regions of the PMOS transistor and the NMOS transistor in the peripheral circuit region, it is preferable to form the ion implantation mask without removing the sacrificial film pattern 28A. This is because the spacer 27A may be exposed to the etching environment and be damaged in the process of removing the ion implantation mask of the PMOS transistor and the NMOS transistor. Therefore, the spacer 27A is formed in the process of removing the ion implantation mask by forming the source and drain regions of the PMOS transistor and the NMOS transistor through ion implantation, removing the ion implantation mask, and then removing the sacrificial layer pattern 28A. Loss can be prevented.

As described above, the present invention forms the sacrificial film pattern 28A on the spacer 27A, thereby preventing the loss of the spacer 27A during the etching process for forming the spacer 27A, thereby preventing the loss of the spacer 27A in the entire region of the substrate 21. The spacer 27A having a uniform thickness may be formed, and thus the threshold voltage variation may be suppressed.

In addition, the present invention forms the sacrificial film pattern 28A on the spacer 27A to remove the ion implantation mask for forming the source and drain regions of the PMOS transistor and the NMOS transistor in the peripheral circuit region. ) Can be prevented from deteriorating electrical characteristics of the semiconductor device.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view showing a semiconductor device having an LDD structure according to the conventional radix.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device having an LDD structure according to an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21 substrate 22 gate insulating film

23: gate conductive film 24: gate hard mask film

25 gate pattern 26 first impurity region

27: spacer insulating film 27A: spacer

28: sacrificial film 28A: sacrificial film pattern

29: second impurity region

Claims (10)

Forming a gate pattern on the substrate; Forming a spacer insulating film on the entire surface of the resultant including the gate pattern; Forming a sacrificial film on the spacer insulating film; Etching the sacrificial layer and the spacer insulating layer to form a stacked pattern in which spacers and sacrificial layer patterns are stacked on both sidewalls of the gate pattern; And Removing the sacrificial layer pattern Method of manufacturing a semiconductor device comprising a. The method of claim 1, The sacrificial film is a semiconductor device manufacturing method of forming a metal oxide film. The method of claim 1, The sacrificial film is a manufacturing method of a semiconductor device formed of an aluminum oxide film. The method of claim 1, The spacer insulating film is formed of a single film composed of an oxide film or a nitride film, or a semiconductor film manufacturing method of forming a laminated film of them. The method of claim 1, The thickness of the sacrificial film is less than the thickness of the spacer insulating film manufacturing method of a semiconductor device. The method of claim 1, Forming the laminated pattern, A method of manufacturing a semiconductor device using a fluorocarbon gas or a mixed gas in which methane fluoride gas and Cl 2 gas are mixed. The method of claim 1, Forming the laminated pattern, A semiconductor device manufacturing method using a high density plasma etching apparatus. The method of claim 1, Forming the laminated pattern, A method of manufacturing a semiconductor device using any device selected from the group consisting of: Transformer Coupled Plasma (TCP), Inductive Coupled Plasma (ICP), Decoupled Plasma Source (DPS), and Electron Cyclotron Resonance (ECR). The method of claim 1, The removing of the sacrificial layer pattern is performed using a BOE (Buffered Oxide Etchant). The method of claim 1, After forming the gate pattern, forming a first impurity region on the substrate on both sides of the gate pattern; After forming the stacked pattern, forming a second impurity region on the substrate on both sides of the stacked pattern; And a doping concentration of the second impurity region is greater than a doping concentration of the first impurity region.
KR1020070111343A 2007-11-02 2007-11-02 Method for manufcturing semiconductor device KR20090045496A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252235B2 (en) 2012-09-21 2016-02-02 Samsung Electronics Co., Ltd. Semiconductor devices and methods of forming the same
KR20220136522A (en) 2021-03-30 2022-10-11 김주동 Air sterilization and indoor air ionizing micro-matter sterilization cleaner

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252235B2 (en) 2012-09-21 2016-02-02 Samsung Electronics Co., Ltd. Semiconductor devices and methods of forming the same
US9548389B2 (en) 2012-09-21 2017-01-17 Samsung Electronics Co., Ltd. Semiconductor devices and methods of forming the same
US10181525B2 (en) 2012-09-21 2019-01-15 Samsung Electronics Co., Ltd. Semiconductor devices and methods of forming the same
KR20220136522A (en) 2021-03-30 2022-10-11 김주동 Air sterilization and indoor air ionizing micro-matter sterilization cleaner

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