KR20090002549A - Semiconductor device with recess gate and method for manufacturing the same - Google Patents

Semiconductor device with recess gate and method for manufacturing the same Download PDF

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Publication number
KR20090002549A
KR20090002549A KR1020070065978A KR20070065978A KR20090002549A KR 20090002549 A KR20090002549 A KR 20090002549A KR 1020070065978 A KR1020070065978 A KR 1020070065978A KR 20070065978 A KR20070065978 A KR 20070065978A KR 20090002549 A KR20090002549 A KR 20090002549A
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KR
South Korea
Prior art keywords
field concentration
gate electrode
semiconductor device
layer
film
Prior art date
Application number
KR1020070065978A
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Korean (ko)
Inventor
김영진
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070065978A priority Critical patent/KR20090002549A/en
Publication of KR20090002549A publication Critical patent/KR20090002549A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

The present invention relates to a semiconductor device having a recess gate and a method of manufacturing the same. To this end, the present invention provides a semiconductor substrate including a recess pattern; A gate insulating film formed on the semiconductor substrate; A first gate electrode embedded in the recess pattern on the gate insulating layer; Providing a semiconductor device including a field concentration relaxing layer formed on the gate insulating layer to cover both edges of the recess pattern, and a second gate electrode formed on the first gate electrode to cover a portion of the field concentration relaxing layer, According to the present invention described above, the electric field concentration phenomenon in the edge region of the recess pattern can be alleviated to prevent deterioration of electrical characteristics of the semiconductor device.

Description

A semiconductor device having a recess gate and a method of manufacturing the same {SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a recess gate (RG) and a method of manufacturing the same.

In recent years, as semiconductor devices become smaller and smaller, gate channel lengths become shorter, and as the doping concentrations of impurity regions such as source and drain regions increase, electrical characteristics of semiconductor devices are caused by leakage currents due to an increase in electric field. Difficult to secure.

In order to improve this, a semiconductor device having a recess gate has been proposed. Here, the recess gate is a gate formed after the recess is etched from the semiconductor substrate, thereby increasing the channel length and reducing the doping concentration of the impurity region, thereby improving the electrical characteristics of the semiconductor device.

FIG. 1A is a scanning electron microscope (SEM) image showing a cross-section of a semiconductor device having a recess gate according to the prior art, and FIG. 1B is a gate voltage V G of the semiconductor device shown in FIG. 1A. It is a graph showing the gate current (I G ) characteristics.

Referring to FIG. 1A, a semiconductor device having a recess gate according to the related art includes a semiconductor substrate 11 having a recess pattern 12, a gate insulating layer 13 formed on an entire surface of the recess pattern 12, and a gate insulating layer. And a gate electrode 14 formed on 13. In this case, the gate electrode 14 fills the recess pattern 12, and a part of the gate electrode 14 protrudes on the surface of the semiconductor substrate 11.

In the above-described prior art, it is understood that the profile of both edges of the recess pattern is very sharp, and the thickness of the gate insulating film formed on both edge regions of the sharp recess pattern is also weak compared to the bottom and sidewalls of the recess pattern. (See " A " in FIG. 1A) This causes field concentration in both edge regions of the recess pattern. This field concentration phenomenon has a problem of deteriorating electrical characteristics of the semiconductor device by generating a leakage current, as shown in Figure 1b.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a semiconductor device and a method for manufacturing the same, which can prevent the leakage current of the semiconductor device due to electric field concentration in both edge regions of the recess pattern. The purpose is.

According to one aspect of the present invention, a semiconductor device includes: a semiconductor substrate having a recess pattern formed thereon; A gate insulating film formed on the semiconductor substrate; A first gate electrode embedded in the recess pattern on the gate insulating layer; The field concentration relaxing layer is formed on the gate insulating layer to cover both edges of the recess pattern, and the second gate electrode is formed on the first gate electrode to cover a portion of the field concentration relaxing layer. Further, a spacer may be further formed on both sidewalls of the second gate electrode on the field concentration mitigating layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a semiconductor substrate having a recess pattern; Forming a gate insulating film on the semiconductor substrate; Forming a first gate electrode to fill the recess pattern; Forming a field concentration relaxing layer on the gate insulating layer to cover both edge regions of the recess pattern and to expose a surface of the first gate electrode, and to cover a portion of the field concentration relaxing layer and to be connected to the first gate electrode; Forming a second gate electrode. The method may further include forming spacers on both sidewalls of the second gate electrode on the field concentration relaxing layer.

The recess pattern of the present invention can be applied to both polygonal, bulb type, or saddle type.

According to the present invention, the field concentration mitigating layer is formed in both edge regions of the recess pattern, thereby reducing the electric field concentration, thereby preventing deterioration of electrical characteristics of the semiconductor device.

In addition, the field concentration mitigating layer of the present invention is located between the spacer and the gate insulating film, thereby reducing the stress between the spacer and the gate insulating film.

In addition, the field concentration relaxing layer of the present invention can be applied to a semiconductor device having a recess pattern of various forms, there is an advantage that the application range is wide.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a cross-sectional view illustrating a semiconductor device having a recess gate according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the semiconductor substrate 21 having the recess pattern 23 formed thereon, the gate insulation film 26A formed on the semiconductor substrate 21, and the gate insulation film 26A formed on the recess pattern 23 are formed. Part of the field concentration-relaxing layer 28B and the field concentration-relaxing layer 28B formed so as to cover both edge regions of the recess pattern 23 on the first gate electrode 27A and the gate insulating film 26A embedded in the And a second gate electrode 30 formed on the first gate electrode 27A. In addition, the semiconductor device may further include a spacer 31A formed on both sidewalls of the second gate electrode 30 on the gate insulating layer 26A.

The field concentration mitigating layer 28B is to alleviate the field concentration phenomenon occurring at both edge regions of the recess pattern 23, and may be formed of an insulating film such as an oxide film series or a nitride film series. As the oxide layer, a silicon oxide layer (SiO 2 ), a high temperature low pressure deposition (HLD), or a tetra-ethoxy ortho silicate (TEOS) may be used.

In addition, the field concentration relaxing layer 28B may be applied to a polygonal recess pattern in addition to the rectangular recess pattern 23 shown in FIG. 2, and may be a bulb type or saddle type recess pattern. Applicable to Here, the bulb type means a recess pattern having a structure wider than the upper part, and generally the lower part has a round shape. In addition, the saddle type means a recess pattern in which protrusions such as fins are formed on the bottom surface.

The spacer 31A may be formed of an insulating film, for example, any one selected from the group consisting of an oxide film series, a nitride film series, and an oxynitride.

The first gate electrode 27A may be formed of a polysilicon film, and the second gate electrode 30 may be formed of a structure in which a polysilicon film, a tungsten silicide film WSi x , and a gate hard mask film are stacked.

As described above, the present invention forms a field concentration alleviating layer in both edge regions of the recess pattern in which the field concentration phenomenon occurs in the semiconductor device having the recess gate, thereby preventing the occurrence of leakage current due to the field concentration phenomenon. It is possible to prevent deterioration of the electrical characteristics of the device.

In addition, the field concentration mitigating layer of the present invention may be located between the gate insulating film and the spacer, thereby reducing stress between the spacer and the gate insulating film.

In addition, the field concentration mitigating layer of the present invention can be applied to a semiconductor device having a recess pattern of various forms has a wide range of applications.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

As shown in FIG. 3A, a device isolation film 22 having a trench structure is formed in a region where device isolation is to be formed on the semiconductor substrate 21. In this case, as is well known, the device isolation layer 22 forms the device isolation layer 22 using a ShalloW Trench Isolation (STI) process. Here, the semiconductor substrate except for the device isolation layer 22 is defined as the active region 21A by the device isolation layer 22, and the pad oxide film used in the device isolation process is left.

Subsequently, after the first photoresist layer pattern 25 is formed on the pad oxide layer of the semiconductor substrate 21 on which the device isolation layer 22 is formed, the pad oxide layer is etched using the first photoresist layer pattern 25 as an etch barrier. Thus, the surface of the active region 21A of the semiconductor substrate 21, which is supposed to be a recess gate, is exposed.

Subsequently, the recess pattern 23 is formed using the etched pad oxide layer 24 as an etch barrier. At this time, the shape of both edge portions of the recess pattern 23 is sharply formed (see " A " in Fig. 1A).

Here, the recess pattern 23 may be formed as a polygonal, bulb type, or saddle type recess pattern in addition to the rectangular recess pattern 23 illustrated in FIG. 3A. The bulb type refers to a recess pattern having a structure having a lower portion than the upper portion. In general, the lower portion has a rounded shape. In addition, the saddle type means a recess pattern in which protrusions such as fins are formed on the bottom surface.

As shown in FIG. 3B, the gate insulating layer 26 is formed on the entire surface of the semiconductor substrate 21 on which the recess pattern 23 is formed. In this case, the gate insulating layer 26 may be formed of a silicon oxide layer (SiO 2 ) by thermal oxidation.

Subsequently, a first gate electrode conductive film 27 is deposited to fill the recess pattern 23 on the gate insulating film 26. In this case, the first gate electrode conductive film 27 may be formed of a silicon-containing film, for example, a polysilicon film.

As shown in FIG. 3C, the conductive film 27 for the first gate electrode is planarized until the surface of the gate insulating film 26 formed on the semiconductor substrate 21 other than the recess pattern 23 is exposed. The first gate electrode 27A embedded in the recess pattern 23 is formed. At this time, the planarization process is to form a subsequent field concentration mitigating layer, it may be used a chemical mechanical polishing (CMP) or etchback (etchback) process.

Next, the field concentration mitigating layer 28 is formed on the entire surface of the semiconductor substrate 21. In this case, the field concentration relaxing layer 28 may be formed of an insulating film, for example, an oxide film series or a nitride film series. As the oxide film series, a silicon oxide film, HLD or TEOS may be used. When the field concentration relaxing layer 28 is formed of an oxide film series, it may be formed using a dry oxidation method or a radical oxidation method.

As shown in FIG. 3D, after the second photoresist layer pattern 29 is formed on the field concentration-relaxation layer 28, the field concentration-relaxation layer 28 is etched using the second photoresist layer pattern 29 as an etch barrier. . In this case, the line width defined by the second photoresist pattern 29 may be the same as the line width defined by the first photoresist pattern 25 or may be smaller than the line width defined by the first photoresist pattern 25. That is, the line width defined by the second photoresist layer pattern 29 may be the same as the line width of the recess pattern 23 or may be smaller than the line width of the recess pattern 23. Thus, the etched field concentration relaxing layer 28A is formed to cover both edge regions of the recess pattern 23, and at the same time, a part of the surface of the first gate electrode 27A is exposed.

As shown in FIG. 3E, a second gate electrode is formed on the entire surface of the semiconductor substrate 21. In this case, the second gate electrode may have a structure in which a polysilicon layer, tungsten silicide (WSi x ), and a gate hard mask layer are stacked.

Subsequently, the second gate electrode 30 is formed by selectively etching the conductive film for the second gate electrode to be connected to the first gate electrode 27A and covering a part of the field concentration relaxing layer 28A.

Subsequently, an insulating film 31 for spacers is formed on the entire surface of the semiconductor substrate 21 on which the second gate electrode 30 is formed. In this case, the spacer insulating layer 31 may be formed of any one selected from the group consisting of an oxide film series, a nitride film series, and a nitride oxide film.

As shown in FIG. 3F, the spacer insulating layer 31 is etched through the front surface etching process to form spacers 31A on both sidewalls of the second gate electrode 30. Subsequently, the field concentration relaxing layer 28A and the gate insulating film 26 are sequentially etched to form a recess gate. In this case, the field concentration relaxing layer 28B is positioned between the gate insulating film 26A and the spacer 31A.

As described above, in the semiconductor device having the recess gate, the field concentration relaxing layer is formed at both edge regions of the recess pattern in which the field concentration phenomenon occurs, thereby preventing the occurrence of leakage current due to the field concentration phenomenon. It is possible to prevent the electrical characteristics of the deterioration.

In addition, the field concentration relaxing layer of the present invention is formed to be located between the gate insulating film and the spacer, thereby reducing the stress between the spacer and the gate insulating film.

In addition, the field concentration mitigating layer of the present invention can be applied to a semiconductor device having a recess pattern of various forms has a wide range of applications.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A is an SEM image of a cross section of a semiconductor device having a recess gate according to the prior art.

FIG. 1B is a graph showing gate current (I G ) characteristics of the gate voltage (V G ) of the semiconductor device illustrated in FIG. 1A.

2 is a cross-sectional view illustrating a semiconductor device having a recess gate in accordance with an embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21 semiconductor substrate 22 device isolation film

23: recess pattern 26, 26A: gate insulating film

27A: first gate electrode 28, 28A, 28B: field concentration mitigating layer

30: second gate electrode 31A: spacer

Claims (19)

A semiconductor substrate on which a recess pattern is formed; A gate insulating film formed on the semiconductor substrate; A first gate electrode embedded in the recess pattern on the gate insulating layer; An electric field concentration relaxation layer formed on the gate insulating layer to cover both edges of the recess pattern; And A second gate electrode formed on the first gate electrode and covering a portion of the field concentration relaxing layer Semiconductor device comprising a. The method of claim 1, The field concentration relaxing layer is formed of an insulating film. The method of claim 1, The field concentration relaxing layer is a semiconductor device formed of an oxide film series or a nitride film series. The method of claim 1, The field concentration mitigating layer is a semiconductor device formed of any one selected from the group consisting of a silicon oxide film, high temperature low pressure deposition (HLD) and Tetra Ethyle Ortho Silicate (TEOS). The method of claim 1, And a spacer formed on both sidewalls of the second gate electrode on the field concentration relaxing layer. The method of claim 5, The spacer is formed of any one selected from the group consisting of oxide film, nitride film and oxynitride (oxynitride). The method of claim 1, The recess pattern may be formed of any one of a polygon, a bulb type, and a saddle type. The method of claim 1, The first gate electrode is a semiconductor device formed of a polysilicon film. The method of claim 1, The second gate electrode has a structure in which a polysilicon film, a tungsten silicide film, and a gate hard mask film are stacked. Forming a semiconductor substrate having a recess pattern; Forming a gate insulating film on the semiconductor substrate; Forming a first gate electrode to fill the recess pattern; Forming an electric field concentration relaxation layer on the gate insulating layer to cover both edge regions of the recess pattern and partially expose the surface of the first gate electrode; And Forming a second gate electrode to cover a portion of the field concentration relaxing layer and to be connected to the first gate electrode; Method of manufacturing a semiconductor device comprising a. The method of claim 10, The field concentration relaxing layer is a semiconductor device manufacturing method of forming an insulating film. The method of claim 10, The field concentration relaxing layer is a semiconductor device manufacturing method of forming an oxide film series or a nitride film series. The method of claim 10, The field concentration relaxing layer is a semiconductor device manufacturing method of forming any one selected from the group consisting of silicon oxide film, HLD and TEOS. The method of claim 10, The field concentration relaxing layer is a method of manufacturing a semiconductor device is formed by using a dry oxidation (radical oxidation) or radical oxidation (radical oxidation) method. The method of claim 10, And forming spacers on both sidewalls of the second gate electrode on the field concentration relaxing layer. The method of claim 15, The spacer may be formed of any one selected from the group consisting of an oxide film series, a nitride film series, and a nitride oxide film. The method of claim 10, The recess pattern may be formed of any one of a polygon, a bulb type, and a saddle type. The method of claim 10, The first gate electrode is formed of a polysilicon film. The method of claim 10, The second gate electrode has a structure in which a polysilicon film, a tungsten silicide film, and a gate hard mask film are stacked.
KR1020070065978A 2007-07-02 2007-07-02 Semiconductor device with recess gate and method for manufacturing the same KR20090002549A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9023703B2 (en) 2011-11-21 2015-05-05 SK Hynix Inc. Method of manufacturing semiconductor device using an oxidation process to increase thickness of a gate insulation layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9023703B2 (en) 2011-11-21 2015-05-05 SK Hynix Inc. Method of manufacturing semiconductor device using an oxidation process to increase thickness of a gate insulation layer

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