KR20090044914A - Method for manufacturing a nonvolatile memory device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a nonvolatile memory device including a device isolation film having a trench structure, thereby improving buried characteristics to suppress voids in the device isolation film, thereby improving device reliability. To provide a method of manufacturing a non-volatile memory device that can be made, the present invention to form a tunneling insulating film and a conductive film for the floating gate on the substrate, and to partially etch the conductive film, the tunneling insulating film and the substrate Forming trenches, performing an ion beam treatment process to break the non-uniform lattice bonds, and performing a cleaning process to etch and homogenize the trench inner walls where the lattice bonds are broken. And forming an insulating film for device isolation so that the trench is buried. A method of manufacturing a memory device is provided.

Nonvolatile Memory Devices, NAND Flash Memory Devices, Device Separators

Description

Manufacturing method of nonvolatile memory device {METHOD FOR MANUFACTURING A NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a nonvolatile memory device, and more particularly, a method of forming an isolation layer of a nonvolatile memory device.

NAND type flash memory device, which is a nonvolatile memory device, is composed of a plurality of cells connected in series to form a unit string for high integration. A memory stick and a USB driver (Universal Serial Bus) are mainly used. Drivers and hard disk (hard disk) to replace the device is expanding the field of application.

Currently, in the method of manufacturing a NAND flash memory device, a floating gate forming method is an ASA-STI (Advanced Self Aligned-Shallow Trench Isolation) process according to a reduction in an overlay margin between an active region and a floating gate. Is applying.

1A to 1D are cross-sectional views illustrating a conventional ASA-STI process.

First, as shown in FIG. 1A, a tunneling insulating film 101, a floating gate conductive film 102, and a hard mask 103 are sequentially formed on the semiconductor substrate 100.

Subsequently, as illustrated in FIG. 1B, a trench 104 is formed by partially etching the hard mask 103A, the conductive film 102A, the tunneling insulating film 101A, and the substrate 100A.

Subsequently, as shown in FIG. 1C, a sidewall compensation film 105 is formed along the inner surface of the trench 104 (see FIG. 1B).

Subsequently, as shown in FIG. 1D, an insulating film 106 for device isolation film is deposited to fill the trench 104 (see FIG. 1B).

Subsequently, although not shown, the insulating film 106 is planarized to form an element isolation film.

However, the ASA-STI process according to the prior art has the following problems.

First, as shown in FIG. 1B, a stepped portion is generated at the boundary of each layer due to the difference in etching selectivity between the layers 100A, 101A, 102A, and 103A during the trench 104 forming process. That is, the lower layer remains larger than the upper layer so that the inner wall of the trench 104 as a whole has the tunneling insulating film 101A and the substrate as in the boundary of each of the layers 100A, 101A, 102A, 103A, particularly at the 'A' site. It has a negative slop having a step at the boundary of 100A.

In this structure, when the sidewall compensation film 105 is formed by performing an oxidation process as shown in FIG. 1C, the stepped portions formed at the boundary between the tunneling insulating film 101A and the substrate 100A react more with oxygen (O ₂ ). The oxidation rate of the substrate 100A is increased compared to other portions. Accordingly, as shown in FIG. 1C, an overhang phenomenon occurs in which the sidewall compensation layer 105 is formed thicker at the 'B' portion than the bottom of the trench 104, thereby causing the trench 104 to be closed.

As a result, the insulating film 106 is not completely buried in the trench 104 which is closed by the overhang during the deposition process of the device isolation film 106 performed in FIG. 1D, and thus voids C are formed therein. Is generated. These voids degrade the isolation characteristics of the device, causing leakage current between cells, which in turn degrades the reliability of the device.

FIG. 2 is a SEM (Scanning Electron Microscope) photograph showing a cross section of a device manufactured by a method of manufacturing a nonvolatile memory device according to the prior art. FIG. 2A is a cross-sectional view after the sidewall compensation film 105 is formed, and FIG. 2B is a cross-sectional view after the insulating film 106 is deposited.

As shown in (a) of FIG. 2, the sidewall compensation film 105 may be formed relatively thick at the boundary (see B) of the tunneling insulating film and the substrate among the inner walls of the trench, which is illustrated in (b). As can be seen, voids C are generated in the insulating film 106.

Therefore, the present invention is proposed to solve the problems of the prior art, in the manufacturing method of a nonvolatile memory device including a device isolation film having a trench structure, by improving the buried characteristics to suppress the generation of voids in the device isolation film Accordingly, an object of the present invention is to provide a method of manufacturing a nonvolatile memory device, which can improve device reliability.

According to an aspect of the present invention, a tunneling insulating layer and a floating gate conductive layer are formed on a substrate, and the conductive layer, the tunneling insulating layer, and the substrate are partially etched to form trenches. And performing an ion beam treatment process to destroy the non-uniform lattice coupling of the trench inner wall, and performing a cleaning process to etch and homogenize the trench inner wall where the lattice bonding is broken, to uniformize the trench. It provides a method of manufacturing a nonvolatile memory device comprising the step of forming an insulating film for a device isolation film to be buried.

According to the present invention having the above-described configuration, an ion beam treatment process is performed on the trench inner wall to partially destroy the lattice bonds of the trench inner wall, and then a cleaning process is performed to form the portion where the lattice bond is broken, that is, formed in the trench. By removing the stepped portion, the inner wall forms a smooth (uniform) profile to improve the embedding characteristics of the device isolation layer, thereby suppressing the generation of voids in the device isolation layer, thereby improving the reliability of the device.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

Example

3A through 3H are cross-sectional views illustrating manufacturing processes in order to explain a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention. As an example, a method of manufacturing a NAND flash memory device using the ASA-STI process will be described.

First, as shown in FIG. 3A, triple n-type wells (not shown) are formed in a semiconductor substrate 200, for example, a p-type substrate, and then p-type wells ( Not shown).

Subsequently, an ion implantation process for adjusting the threshold voltage is performed in the channel region in the p-well.

Subsequently, a tunneling insulating film 201 is formed on the substrate 200. In this case, the tunneling insulating film 201 may be formed of an oxide film, for example, silicon oxide film (SiO ₂ ), or after the silicon oxide film is formed, a heat treatment process using nitrogen, for example, N ₂ gas, is performed to nitride the silicon oxide film and the substrate 200. It may also form a layer. In addition, it may be formed of a high dielectric film having a dielectric constant of 3.9 or more, such as a metal oxide such as an aluminum oxide film (Al ₂ O ₃ ), a hafnium oxide film (HfO ₂ ), or a zirconium oxide film (ZrO ₂ ). The tunneling insulating film 201 may be formed to a thickness of about 50 ~ 100Å.

For example, when the tunneling insulating film 201 is formed of a silicon oxide film, the manufacturing method may be a dry oxidation, a wet oxidation process or an oxidation process using radical ions. It is preferable to carry out dry oxidation or wet oxidation instead of the oxidation process using radical ions. On the other hand, the heat treatment process using nitrogen gas can be carried out using a furnace (furnace) equipment.

Subsequently, a floating gate conductive film 202 is formed on the tunneling insulating film 201. In this case, the conductive film 202 may be made of any conductive material. For example, the conductive film 202 may be formed of any one material selected from polycrystalline silicon, transition metal, and rare earth metal. For example, the polysilicon film may be an un-doped polysilicon film that is not doped with impurity ions or a doped polysilicon film that is doped with impurity ions, and in the case of an undoped polysilicon film, Impurity ions are implanted separately through an ion implantation process. The polysilicon film is formed by a low pressure chemical vapor deposition (LPCVD) method, wherein a silane (SiH ₄ ) gas is used as a source gas, and phosphine (PH ₃ ), 3 is used as a doping gas. Fluorine chloride (BCl ₃ ) or giborane (B ₂ H ₆ ) gas is used. As the transition metal, iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti) and the like are used. Erbium (Er), Ytterium (Yb), Samarium (Sm), Yttrium (Y), Lanthanum (La), Cerium (Ce), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), and Tolium ( Tm), lutetium (Lu) and the like.

Subsequently, a hard mask 206 may be formed on the conductive film 202. At this time, the hard mask 206 is to compensate for the lack of thickness of the photoresist pattern (not shown) to be formed through a subsequent process, it may be formed in a single layer or a laminated structure. In the case of a single layer, it may be formed of a nitride film such as silicon nitride film (Si ₃ N ₄ ). In the case of lamination, the silicon nitride film 203, the silicon oxide film 204, and the silicon oxynitride film (SiON) 205 may be formed in a stacked structure.

Meanwhile, a buffer film (not shown) may be further formed between the conductive film 202 and the hard mask 206. In this case, the buffer film (not shown) may be formed by a subsequent process of depositing the hard mask 206. And to prevent the conductive film 202 from being damaged during the removal process, and may be formed of a material having a high etching selectivity with the hard mask 206. For example, when the hard mask 206 is formed of a silicon nitride film single layer, the hard mask 206 is formed of a silicon oxide film.

Subsequently, as illustrated in FIG. 3B, the hard mask 206A, the conductive film 202A, and the tunneling insulating film 201A are partially etched to expose the substrate 200. Specifically, after the hard mask 206A is etched first, the conductive layer 202A and the tunneling insulating film 201A are etched using the etched hard mask 206A as an etching mask. In this case, the substrate 200 may also be partially etched.

Subsequently, the STI ion implantation process 207 may be performed on the exposed substrate 200 to form the ion implantation layer 208 at a predetermined depth in the substrate 200. At this time, the STI ion implantation process 207 is to compensate for the doping concentration of the channel region lost in the previous or subsequent process. For example, the STI ion implantation process is carried out with an energy of 20 to 30 keV using arsenic (As), boron (B), and phosphorus (P).

Subsequently, as shown in FIG. 3C, the substrate 200A is etched to form the trench 209 in the substrate 200A. At this time, the depth and width of the trench 209 may be appropriately controlled in consideration of the separation characteristics between the devices.

Next, as shown in FIG. 3D, an ion beam treatment process 210 is performed on the inner wall of the trench 209. In this case, the ion beam treatment process 210 may be performed without an angle, but in view of effect, the ion beam treatment may be performed at an angle within a range not exceeding 30 °, preferably at an ion beam irradiation angle of 10 °. At this time, any one selected from arsenic (As), phosphorus (P), boron (B) or oxygen (O ₂ ) is used as the ion beam.

Next, as shown in FIG. 3E, a cleaning process is performed on the inner wall of the trench 209 (see FIG. 3D). The reason for this is to form an inner wall of the trench 209 smoothly (evenly) by etching the inner wall of the trench 209, in particular, the stepped portion, which is primarily degraded through the ion beam treatment process 210. That is, the stepped portion of the trench 209 is much lower in durability by the ion beam treatment process 210 than other portions, and is easily etched relative to other portions in subsequent cleaning processes. As a result, the negative slope may be smoothly formed by removing the stepped portion formed on the inner wall of the trench 209A as shown in FIG. 3C and B in FIG. 3E.

At this time, the washing step may be performed sequentially using a B, F, R, N solution or at least two or more of these solutions. For example, the B solution is a solution in which H ₂ SO ₄ and H ₂ O ₂ are mixed, and their mixing ratio (H ₂ SO ₄ : H ₂ O ₂ ) is 4: 1 to 110 to 130 ° C, preferably 120 ° C. At a temperature of. The F solution is a solution in which HF and de-ionized water (DIW) are mixed, and their mixing ratio (HF: DIW) is 100: 1, and is performed at a temperature of 25 ° C. The R solution is a solution in which H ₂ SO ₄ and H ₂ O ₂ are mixed, and the mixing ratio (H ₂ SO ₄ : H ₂ O ₂ ) of 50: 1 is 80 to 100 ° C, preferably 90 ° C. To be carried out in The N solution is a solution in which NH ₄ OH, H ₂ O ₂ and H ₂ O are mixed, and their mixing ratio (NH ₄ OH: H ₂ O ₂ : H ₂ O) is 1: 4: 2 at a temperature of 25 ° C. To be carried out in

Subsequently, as shown in FIG. 3F, a sidewall compensation film 211 may be formed in the trench 209A (see FIG. 3E). In this case, the sidewall compensation film 211 may be formed by an oxidation process, for example, an oxidation process using radical ions, and the thickness thereof may be formed in a range of 10 to 100 μm in consideration of buried characteristics.

Subsequently, as illustrated in FIG. 3G, the first insulating layer 212 for the isolation layer may be formed on the sidewall compensation layer 211 along the inner surface of the trench 209A (see FIG. 3E). In this case, the first insulating layer 212 is formed to have a thickness of about 800 to 1200 Å (based on the trench bottom) in the form of a liner in which the bottom of the trench 209A is thicker than the sidewall. The first insulating film 212 may be formed of a USG (Un-doped Silicate Glass) film (hereinafter referred to as HDP film) using a high density plasma-chemical vapor deposition (HDP-CVD) method having excellent embedding characteristics even at a high aspect ratio. , HTO (High Temperature Oxide) film can be formed.

Subsequently, a plasma treatment process may be performed to densely improve the film quality of the first insulating film 212. At this time, the plasma treatment process is performed for 20-30 seconds using an oxygen (O ₂ ) plasma.

Subsequently, as shown in FIG. 3H, the second insulating film 213 for the isolation layer is formed to fill the trench 209A (see FIG. 3E). In this case, the second insulating film 213 may be formed of an HDP film, and may be formed in a deposition-etch-deposition (DED) or deposition-etch-deposition-etch-deposition (DEDED) method to improve the embedding characteristics. . That is, instead of depositing the HDP film at once, the HDP film is partially deposited, and then the HDP film is partially etched to extend the inlet of the trench 209A, and then the HDP film is deposited again.

Next, although not shown, the second insulating film 213 is planarized. In this case, the planarization process may be performed by an etching process (eg, etch back) or chemical mechanical polishing (hereinafter, referred to as CMP). For example, in the CMP process, the second insulating film 213 is selectively polished using the hard mask 206A as the polishing stop film.

Next, the hard mask 206A is removed.

Next, although not shown, the first and second insulating layers 213 and 212 in the cell region are recessed to adjust the effective height of the device isolation layer, that is, the effective field oxide height (EFH). At this time, the etching process for adjusting the EFH is possible both dry etching or wet etching.

Since the process is the same as the general process, description thereof will be omitted.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the present invention has been described using the ASA-STI process as an example, the present invention may also be applied to a shallow trench isolation (STI), a self-aligned-floating gate (SA-FG), or a self-aligned-sti (SA-STI) process. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the prior art.

FIG. 2 is a SEM (Scanning Electron Microscope) photograph showing a cross section of a device manufactured by a method of manufacturing a nonvolatile memory device according to the prior art.

3A to 3H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 100A, 200, 200A: semiconductor substrate

101, 101A, 201, 201A: tunneling insulating film

102, 102A, 202, 202A: conductive film for floating gate

103, 103A, 206, 206A: Hard Mask

104, 209: Trench

105, 211: sidewall protective film

106: insulating film for device isolation film

208: Ion implantation layer

203, 203A: nitride film (silicon nitride film)

204, 204A: oxide film (silicon oxide film)

205 and 205A: oxynitride film (silicon oxynitride film)

212: first insulating film for device isolation film

213: second insulating film for device isolation film

Claims (10)

Forming a tunneling insulating film and a floating gate conductive film on the substrate; Etching a portion of the conductive layer, the tunneling insulating layer, and the substrate to form a trench; Performing an ion beam treatment process to break the lattice bond of the non-uniform trench inner wall; Performing a cleaning process to etch and equalize the trench inner wall where the lattice bond is broken; And Forming an insulating film for a device isolation layer to fill the trench Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, The ion beam treatment process is performed by using any one of the ion beam selected from arsenic, phosphorus, boron or oxygen. The method of claim 2, A method of manufacturing a nonvolatile memory device, wherein the irradiation angle of the ion beam is performed within a range not exceeding 30 ° while exceeding O °. The method of claim 1, The cleaning process is a method of manufacturing a non-volatile memory device using a B, F, R, N solution or a solution selected from these solutions sequentially. The method of claim 1, Forming the insulating film for the device isolation film, Depositing a first insulating film in a liner shape on an inner surface of the trench; Depositing a second insulating film on the first insulating film to fill the trench; And Planarizing the first and second insulating layers Method of manufacturing a nonvolatile memory device comprising a. The method of claim 5, wherein And the first insulating film is formed of an HTO film, and the second insulating film is formed of an HDP film. The method of claim 5, wherein After depositing the first insulating film, And performing a plasma treatment process on the first insulating film. The method of claim 1, After etching the trench inner wall, And forming a sidewall compensation layer by performing an oxidation process on the inner wall of the trench. The method of claim 1, After forming the conductive film, And forming a hard mask on the conductive layer. The method of claim 9, The hard mask is formed of a silicon nitride film, or a silicon nitride film, a silicon oxide film and a silicon oxynitride film manufacturing method of a non-volatile memory device to form a stacked structure laminated.

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