KR20090044897A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR20090044897A
KR20090044897A KR1020070111180A KR20070111180A KR20090044897A KR 20090044897 A KR20090044897 A KR 20090044897A KR 1020070111180 A KR1020070111180 A KR 1020070111180A KR 20070111180 A KR20070111180 A KR 20070111180A KR 20090044897 A KR20090044897 A KR 20090044897A
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film
forming
semiconductor device
tungsten
device manufacturing
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KR1020070111180A
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Korean (ko)
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오상원
강명희
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 제조 방법을 제공하기 위한 것으로, 이를 위해 기판상에 게이트절연막, 폴리실리콘막 및 시드층을 순차적으로 형성하는 단계, 상기 시드층 상에 개방영역을 갖는 희생막패턴을 형성하는 단계, 상기 개방영역의 일부를 채우는 텅스텐막을 형성하는 단계, 상기 텅스텐막이 형성된 개방영역의 나머지를 채우는 게이트하드마스크막을 형성하는 단계, 상기 희생막패턴을 제거하는 단계 및 상기 게이트하드마스크막을 식각장벽으로 상기 시드층 및 폴리실리콘막을 식각하는 단계를 포함하여 이루어지므로써, 식각공정을 생략한 채로 수직형상을 갖는 텅스텐막을 형성할 수 있다.The present invention is to provide a method for manufacturing a semiconductor device, for this purpose to sequentially form a gate insulating film, a polysilicon film and a seed layer on the substrate, forming a sacrificial film pattern having an open area on the seed layer Forming a tungsten film filling a portion of the open region, forming a gate hard mask layer filling the remainder of the open region where the tungsten film is formed, removing the sacrificial layer pattern, and forming the gate hard mask layer as an etch barrier. By etching the seed layer and the polysilicon film, a tungsten film having a vertical shape may be formed while the etching process is omitted.

텅스텐막, 시드층, 희생막패턴, 개방영역, 폴리실리콘막 Tungsten film, seed layer, sacrificial film pattern, open area, polysilicon film

Description

반도체 소자 제조 방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자 제조 기술에 관한 것으로, 특히 반도체 소자 제조 방법에 관한 것이다.The present invention relates to a semiconductor device manufacturing technology, and more particularly to a semiconductor device manufacturing method.

DRAM(Dynamic Random Access Memory) 소자의 게이트패턴(gate pattern)은 기판상에 게이트절연막, 폴리실리콘막과 텅스텐막이 적층된 게이트전도막 및 게이트하드마스크막을 순차적으로 형성한 후에 위에서 아래로 식각해 내려오는 탑-다운식각(top down etch)공정으로 형성한다.A gate pattern of a DRAM (Dynamic Random Access Memory) device is formed by sequentially forming a gate insulating film, a gate conductive film in which a polysilicon film and a tungsten film, and a gate hard mask film are sequentially etched from the top to the bottom thereof. It is formed by a top down etch process.

이와 같은 탑-다운식각공정은 게이트패턴의 형성을 용이하게 하며, 공정 단계도 감소시킬 수 있어서 현재까지 널리 사용되고 있다.This top-down etching process is easy to form the gate pattern and can reduce the process step is widely used to date.

그러나, 현재는 게이트패턴의 피치(pitch)가 미세화됨에 따라 수직형상(vertical profile)을 갖는 텅스텐막을 형성하기 어려운 실정이다.However, at present, it is difficult to form a tungsten film having a vertical profile as the pitch of the gate pattern is miniaturized.

도 1은 종래기술에 따른 게이트패터닝후의 텅스텐막을 촬영한 전자현미경사진이다.1 is an electron micrograph of a tungsten film after gate patterning according to the prior art.

도 1을 참조하면, 텅스텐막(11)에 보잉(bowing)현상이 발생된 것을 확인할 수 있다. 즉, 탑-다운식각공정에서 텅스텐막(11) 자체의 결정립 크기(grain size)로 인해 국부적으로 보잉형상을 갖게 된다. 이렇게 텅스텐막(13)이 보잉형상을 갖을 경우는 게이트저항(Rs) 특성이 저하되는 문제점이 된다.Referring to FIG. 1, it can be seen that bowing occurs in the tungsten film 11. That is, in the top-down etching process, the tungsten film 11 itself has a local boeing shape due to the grain size of the tungsten film 11 itself. Thus, when the tungsten film 13 has a bowing shape, the gate resistance (Rs) characteristics are deteriorated.

또한, 게이트의 시트저항 특성을 향상시키기 위해서 텅스텐막 증착 전에 어닐(anneal)공정을 실시할 수 있는데, 이때 도 2의 전자현미경사진과 같이 텅스텐막(21)의 결정립 크기가 더욱 커져 보잉형상을 더욱 심화시킬 수 있으며, 나아가 패턴을 파괴시키는 문제점이 된다.In addition, in order to improve the sheet resistance of the gate, an annealing process may be performed before deposition of the tungsten film. At this time, the grain size of the tungsten film 21 becomes larger as shown in the electron micrograph of FIG. It can be deepened, and furthermore, it becomes a problem of destroying the pattern.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 보잉없이 텅스텐막의 형상을 확보할 수 있는 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device capable of securing the shape of a tungsten film without bowing.

또한, 게이트의 시트저항을 감소시킬 수 있는 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the sheet resistance of the gate.

상기의 목적을 달성하기 위한 본 발명의 반도체 소자 제조 방법은 기판상에 게이트절연막, 폴리실리콘막 및 시드층을 순차적으로 형성하는 단계, 상기 시드층 상에 개방영역을 갖는 희생막패턴을 형성하는 단계, 상기 개방영역의 일부를 채우는 텅스텐막을 형성하는 단계, 상기 텅스텐막이 형성된 개방영역의 나머지를 채우는 게이트하드마스크막을 형성하는 단계, 상기 희생막패턴을 제거하는 단계 및 상기 게이트하드마스크막을 식각장벽으로 상기 시드층 및 폴리실리콘막을 식각하는 단계를 포함하여 이루어짐을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of sequentially forming a gate insulating film, a polysilicon film and a seed layer on a substrate, forming a sacrificial film pattern having an open area on the seed layer Forming a tungsten film filling a portion of the open region, forming a gate hard mask film filling a remainder of the open region in which the tungsten film is formed, removing the sacrificial layer pattern, and forming the gate hard mask film as an etch barrier. And etching the seed layer and the polysilicon film.

상술한 바와 같은 과제 해결 수단을 바탕으로 하는 본 발명은 식각공정을 생략한 채로 수직형상을 갖는 텅스텐막을 형성할 수 있다.The present invention based on the problem solving means described above can form a tungsten film having a vertical shape without the etching process.

따라서, 텅스텐막의 식각에 따른 결함을 방지할 수 있어서 안정성 및 신뢰성 높은 반도체 소자를 제조할 수 있으며, 나아가 반도체 소자의 수율을 향상시킬 수 있는 효과를 갖는다.Therefore, it is possible to prevent defects due to the etching of the tungsten film, thereby manufacturing a semiconductor device having high stability and reliability, and further, it has an effect of improving the yield of the semiconductor device.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위해 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

도 3a 내지 도 3f는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정단면도이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a에 도시된 바와 같이, 기판(31) 상에 게이트절연막(32), 폴리실리콘막(33) 및 시드층(34)을 순차적으로 형성한다. As shown in FIG. 3A, the gate insulating film 32, the polysilicon film 33, and the seed layer 34 are sequentially formed on the substrate 31.

게이트절연막(32)은 실리콘산화막(SiO2)이며, 산화(oxidation)공정을 통해 형성한다. 그리고, 폴리실리콘막(33)은 인(P)과 같은 불순물이 도핑되며, 이에 따라 전도성을 갖는다.The gate insulating film 32 is a silicon oxide film (SiO 2 ), and is formed through an oxidation process. In addition, the polysilicon layer 33 is doped with impurities such as phosphorus (P), thereby having conductivity.

시드층(34)은 후속 텅스텐막을 형성하기 위한 베리어메탈(barrier metal)로서, 텅스텐실리사이드(WSi), 텅스텐질화막(WN), 텅스텐실리사이드질화막(WSiN), 티타늄막(Ti), 티타늄질화막(TiN), 금(Au) 및 백금(Pt)으로 이루어진 그룹 중에서 선택된 적어도 어느 하나일 수 있다. 예를 들면, 티타늄질화막과 텅스텐질화막의 적 층구조일 수 있다. 그리고, 시드층(34)은 100~400Å의 두께로 형성한다.The seed layer 34 is a barrier metal for forming a subsequent tungsten film, and includes tungsten silicide (WSi), tungsten nitride film (WN), tungsten silicide nitride film (WSiN), titanium film (Ti), and titanium nitride film (TiN). , Gold (Au) and platinum (Pt) may be at least one selected from the group consisting of. For example, it may be a laminated structure of a titanium nitride film and a tungsten nitride film. The seed layer 34 is formed to a thickness of 100 ~ 400Å.

이어서, 시드층(34) 상에 희생막과 포토레지스트패턴(36)을 순차적으로 형성한 후에, 포토레지스트패턴(36)을 식각장벽으로 희생막을 식각한다. 이로써 개방영역(37)을 갖는 희생막패턴(35)이 형성된다.Subsequently, after the sacrificial layer and the photoresist pattern 36 are sequentially formed on the seed layer 34, the sacrificial layer is etched using the photoresist pattern 36 as an etch barrier. As a result, the sacrificial layer pattern 35 having the open area 37 is formed.

개방영역(37)을 갖는 희생막패턴(35)은 후속 텅스텐막의 성장시 틀을 잡아주는 박막으로 절연막 특히, 산화막으로 형성하는데, 자세하게는 SOD(Spin On Dielectric)막, TEOS(Tetra Ethyl Ortho Silicate)막 또는 BPSG(Boron Phosphorus Silicate Glass)막일 수 있다. 그리고, 희생막은 1000~4000Å의 두께로 형성한다.The sacrificial film pattern 35 having the open area 37 is a thin film that guides the growth of a subsequent tungsten film. The sacrificial film pattern 35 is formed of an insulating film, particularly an oxide film. Specifically, a SOD (Spin On Dielectric) film and TEOS Film or BPSG (Boron Phosphorus Silicate Glass) film. Then, the sacrificial film is formed to a thickness of 1000 ~ 4000Å.

이어서, 포토레지스트패턴(36)을 제거한다.Next, the photoresist pattern 36 is removed.

도 3b에 도시된 바와 같이, 개방영역(37)의 일부를 채우는 텅스텐막(38)을 형성한다.As shown in FIG. 3B, a tungsten film 38 filling a part of the open area 37 is formed.

이때, 텅스텐막(38)은 전기도금(electroplate) 방식으로 성장된다.At this time, the tungsten film 38 is grown by an electroplating method.

도 3c에 도시된 바와 같이, 텅스텐막(38)이 형성된 개방영역(37A)의 나머지를 채우도록 게이트하드마스크막(39)을 형성한다.As shown in FIG. 3C, the gate hard mask film 39 is formed so as to fill the rest of the open area 37A in which the tungsten film 38 is formed.

게이트하드마스크막(39)은 개방영역(37A)이 채워지도록 절연막, 특히 실리콘질화막(Si3N4)을 형성한 후에, 화학적기계적연마(CMP) 또는 에치백(etch back) 공정을 진행하여 형성한다.The gate hard mask film 39 is formed by forming an insulating film, particularly a silicon nitride film (Si 3 N 4 ) to fill the open area 37A, and then performing a chemical mechanical polishing (CMP) or etch back process. do.

도 3d에 도시된 바와 같이, 희생막패턴(35)을 제거한다.As shown in FIG. 3D, the sacrificial layer pattern 35 is removed.

희생막패턴(35)은 습식(wet) 또는 건식(dry) 식각공정으로 제거한다.The sacrificial layer pattern 35 is removed by a wet or dry etching process.

도 3e에 도시된 바와 같이, 게이트하드마스크막(39)을 식각장벽으로 시드층(34)과 폴리실리콘막(33)을 식각한다. 이때, 폴리실리콘막(33)은 일부만이 식각되며, 일부는 잔류하게 된다.As shown in FIG. 3E, the seed layer 34 and the polysilicon layer 33 are etched using the gate hard mask layer 39 as an etch barrier. At this time, only a part of the polysilicon film 33 is etched, and some remain.

이어서, 기판(31) 전면에 캡핑막(40)을 형성한다.Subsequently, a capping film 40 is formed over the entire surface of the substrate 31.

캡핑막(40)은 후속 열공정에서 텅스텐막(38)이 산화되는 현상을 방지하기 위해 형성한다. 이를 위해 캡핑막(40)은 절연막 특히, 질화막으로 형성된다.The capping film 40 is formed to prevent the tungsten film 38 from being oxidized in a subsequent thermal process. To this end, the capping film 40 is formed of an insulating film, in particular a nitride film.

도 3f에 도시된 바와 같이, 캡핑막(40)을 식각장벽으로 잔류하는 폴리실리콘막(33A) 및 게이트절연막(32)을 식각하여 게이트패턴을 형성한다.As shown in FIG. 3F, the gate pattern is formed by etching the polysilicon layer 33A and the gate insulating layer 32, the capping layer 40 remaining as an etch barrier.

이후, 재산화 공정을 진행하여 노출된 폴리실리콘막(33B) 및 게이트절연막(32)의 측벽에 보호막(41)을 형성한다.Thereafter, the passivation process is performed to form the passivation layer 41 on the exposed sidewalls of the polysilicon layer 33B and the gate insulating layer 32.

전술한 바와 같은 본 발명의 실시예는 희생막패턴(35)을 이용하여 텅스텐막(38)의 틀을 잡아준다. 때문에 텅스텐막(38)을 패터닝하기 위한 식각공정은 생략된채 수직형상을 갖는 텅스텐막(38)을 형성할 수 있다.As described above, the tungsten film 38 is framed using the sacrificial film pattern 35. Therefore, the etching process for patterning the tungsten film 38 may be omitted and the tungsten film 38 having a vertical shape may be formed.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

예를 들어, 도 3e에서 폴리실리콘막(33)의 일부를 식각하는 것이 아니라, 폴리실리콘막(33)을 완전식각하여 게이트패턴을 형성할 수 있다. 이러한 방식으로 게이트패턴을 제조할 경우에도, 텅스텐막의 패터닝은 식각방식이 아니기 때문에 종래 의 문제점을 해결할 수 있다.For example, instead of etching part of the polysilicon layer 33 in FIG. 3E, the gate pattern may be formed by completely etching the polysilicon layer 33. Even when the gate pattern is manufactured in this way, the conventional problem can be solved because the patterning of the tungsten film is not an etching method.

도 1은 보잉현상이 발생된 텅스텐막을 촬영한 전자현미경사진.1 is an electron microscope photograph of a tungsten film in which the bowing phenomenon is generated.

도 2는 보잉현상이 더욱 심화된 텅스텐막을 촬영한 전자현미경사진.2 is an electron micrograph of a tungsten film in which the Boeing phenomenon is further enhanced.

도 3a 내지 도 3f는 본 발명의 실시예에 따른 게이트패턴의 형성 방법을 나타낸 공정단면도.3A to 3F are cross-sectional views illustrating a method of forming a gate pattern according to an exemplary embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

31 : 기판 32 : 게이트절연막31 substrate 32 gate insulating film

33 : 폴리실리콘막 34 : 시드층33 polysilicon film 34 seed layer

35 : 희생막패턴 37 : 개방영역35: sacrificial film pattern 37: open area

38 : 텅스텐막38: tungsten film

Claims (7)

기판상에 게이트절연막, 폴리실리콘막 및 시드층을 순차적으로 형성하는 단계;Sequentially forming a gate insulating film, a polysilicon film, and a seed layer on the substrate; 상기 시드층 상에 개방영역을 갖는 희생막패턴을 형성하는 단계;Forming a sacrificial layer pattern having an open region on the seed layer; 상기 개방영역의 일부를 채우는 텅스텐막을 형성하는 단계;Forming a tungsten film filling a portion of the open area; 상기 텅스텐막이 형성된 개방영역의 나머지를 채우는 게이트하드마스크막을 형성하는 단계;Forming a gate hard mask film filling the remainder of the open region in which the tungsten film is formed; 상기 희생막패턴을 제거하는 단계; 및Removing the sacrificial layer pattern; And 상기 게이트하드마스크막을 식각장벽으로 상기 시드층 및 폴리실리콘막을 식각하는 단계Etching the seed layer and the polysilicon layer using the gate hard mask layer as an etch barrier 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 텅스텐막은 전기도금방식으로 형성하는 반도체 소자 제조 방법.The tungsten film is a semiconductor device manufacturing method formed by the electroplating method. 제1항에 있어서,The method of claim 1, 상기 시드층은 텅스텐실리사이드(WSi), 텅스텐질화막(WN), 텅스텐실리사이드 질화막(WSiN), 티타늄막(Ti), 티타늄질화막(TiN), 금(Au) 및 백금(Pt)으로 이루어진 그룹 중에서 선택된 적어도 어느 하나로 형성하는 반도체 소자 제조 방법.The seed layer is at least selected from the group consisting of tungsten silicide (WSi), tungsten nitride film (WN), tungsten silicide nitride film (WSiN), titanium film (Ti), titanium nitride film (TiN), gold (Au) and platinum (Pt). A semiconductor device manufacturing method formed by any one. 제1항에 있어서,The method of claim 1, 상기 희생막은 산화막으로 형성하는 반도체 소자 제조 방법.The sacrificial film is a semiconductor device manufacturing method of forming an oxide film. 제1항에 있어서,The method of claim 1, 상기 희생막은 SOD(Spin On Dielectric)막, TEOS(Tetra Ethyl Ortho Silicate)막 또는 BPSG(Boron Phosphorus Silicate Glass)막으로 형성하는 반도체 소자 제조 방법. The sacrificial film is a semiconductor device manufacturing method of forming a spin on dielectric (SOD) film, a tetra ethyl ortho silicate (TEOS) film or a boron phosphorus silicate glass (BPSG) film. 제1항에 있어서,The method of claim 1, 상기 폴리실리콘막을 식각하는 단계는 Etching the polysilicon film is 상기 폴리실리콘막의 일부만을 식각하는 단계;Etching only a part of the polysilicon film; 상기 기판 전면에 캡핑막을 형성하는 단계;Forming a capping film on the entire surface of the substrate; 에치백 공정으로 캡핑막을 식각하는 단계; 및Etching the capping film by an etch back process; And 상기 폴리실리콘막을 식각하는 단계Etching the polysilicon film 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제6항에 있어서,The method of claim 6, 상기 캡핑막은 질화막으로 형성하는 반도체 소자 제조 방법.The capping film is a semiconductor device manufacturing method of forming a nitride film.
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