KR20090044823A - Nonvolatile memory device and method for fabricating the same - Google Patents

Abstract

The present invention is to provide a nonvolatile memory device and a method of manufacturing the same to improve the coupling ratio (coupling ratio) and to reduce the interference between the floating gates, for this purpose the present invention is to recess one side on the substrate A nonvolatile memory device including a floating gate formed in a U-shaped pattern, a dielectric film and a control gate sequentially formed while filling a concave portion of one side of the floating gate on top and one side of the floating gate.

Nonvolatile Memory Devices, Interference, Coupling Ratios

Description

Non-volatile memory device and method of manufacturing the same {NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a nonvolatile memory device and a method of manufacturing the same.

A nonvolatile memory device is a memory device that can maintain a write state even when a power supply is interrupted. A nonvolatile memory device generally includes a floating gate capable of accumulating charge in a MOS transistor structure. It is included.

That is, the nonvolatile memory device has a structure in which a floating gate is formed on a substrate through a thin gate insulating film called a tunneling insulating film, and a control gate is formed on the floating gate through a dielectric film. The floating gate is tunneled. The insulating film and the dielectric film are electrically insulated from the substrate and the control gate.

The above-described data programming method of a nonvolatile memory device includes a method using FN tunneling and a method using hot electron injection. Among them, FN tunneling is a method in which a high voltage is applied to a tunneling insulating layer by applying a high voltage to a control gate of a nonvolatile memory device, whereby electrons of the substrate are injected into the floating gate through the tunneling insulating layer, thereby writing data. to be. On the other hand, a method using hot electron injection is a method of writing data by applying a high voltage to the control gate and the drain and injecting hot electrons generated near the drain into the floating gate through the tunneling insulating film.

Therefore, both FN tunneling and hot electron injection methods require high electric fields to be applied to the tunneling insulating film. In this case, in order to apply a high electric field to the tunneling insulating layer, a high coupling ratio is required.

Coupling ratio refers to the ratio of the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the substrate. In order to increase the coupling ratio, it is necessary to increase the contact area between the control gate and the floating gate. However, in the conventional art of forming the floating gate in a flat structure, there is a limit to increasing the coupling ratio. have.

In addition, as the integration of nonvolatile memory devices increases, the distances between the cells of the nonvolatile memory devices become narrower. As a result, parasitic capacitance between the floating gates increases, thereby increasing the interference between the floating gates, thereby increasing the program threshold voltage. (Vt) The problem of unstable distribution occurs.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a nonvolatile memory device capable of increasing the coupling ratio and reducing interference between floating gates and a method of manufacturing the same.

According to an aspect of the present invention, a floating gate formed in a U-shaped pattern having one side concave on a substrate, and a concave portion of one side of the floating gate formed on an upper side and one side of the floating gate. A nonvolatile memory device including a dielectric film and a control gate sequentially formed while filling is provided.

According to another aspect of the present invention, a tunneling insulating film, a first conductive film for a floating gate, and a sacrificial film are sequentially formed on a substrate, patterning the sacrificial film, and including the sacrificial film. Forming a second conductive film for the floating gate on the entire surface, patterning the second conductive film for the floating gate and the sacrificial film to form the second conductive film for the floating gate in a? -Shaped pattern, and removing the sacrificial film And sequentially forming a dielectric film and a control gate conductive film on the floating gate first and second conductive films, patterning the control gate conductive film, the dielectric film, and the floating gate first conductive film. To provide a method of manufacturing a nonvolatile memory device comprising the step of forming a gate.

According to the present invention, a floating gate is formed by dividing the floating gate into a flat first conductive film and a second conductive film having a? -Shaped shape, and forming a control gate in an internal space between the first conductive film and the second conductive film. It is possible to increase the coupling ratio of the device by increasing the junction area between the gates. In addition, since only the area corresponding to the thickness of the first conductive film causes interference with adjacent floating gates, interference between floating gates can be reduced.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

1A to 1G are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to the present invention.

First, as shown in FIG. 1A, the tunneling insulating layer 11, the first conductive layer 12 for the floating gate, and the sacrificial layer 13 are sequentially formed on the substrate 10.

The first conductive layer 12 for the floating gate may be formed of a doped polysilicon layer doped with impurities, and the sacrificial layer 13 may be formed of an oxide layer or a nitride layer.

Subsequently, as illustrated in FIG. 1B, the sacrificial layer 13 is patterned by a photolithography process to form the sacrificial layer pattern 13A.

Subsequently, as shown in FIG. 1C, the second conductive layer 14 for the floating gate is formed on the entire surface including the sacrificial layer pattern 13A.

The second conductive film 14 for the floating gate may be formed of a doped polysilicon film. The second conductive film 14 for the floating gate may be formed to have the same impurity concentration as the first conductive film 12 for the floating gate, or may be formed by varying the impurity concentration in consideration of electrical characteristics.

After the second conductive film 14 for floating gate is formed, a planarization process for flattening the surface of the second conductive film 14 for floating gate may be performed.

Subsequently, as illustrated in FIG. 1D, the second conductive layer 14 and the sacrificial layer pattern 13A for the floating gate are patterned by a photolithography process.

At this time, the sacrificial film pattern 13A is exposed on one side of the etched surface and the sacrificial film pattern 13A is not exposed on the other side of the substrate, so that the second conductive layer 14 for the floating gate is formed in a Γ pattern.

Subsequently, as shown in FIG. 1E, the sacrificial layer pattern 13A is removed. When the sacrificial film pattern 13A is formed of a nitride film, it is preferable to use a wet etching process when removing the sacrificial film pattern 13A.

As the sacrificial layer pattern 13A is removed, an empty space is formed between the first conductive layer 12 for the floating gate and the second conductive layer 14 for the floating gate.

Next, the dielectric film 15 and the control gate conductive films 16A and 16B are sequentially formed on the first and second conductive films 12 and 14 for the floating gate.

The dielectric film 15 is preferably formed of an oxide oxide (ONO) structure in which the first oxide film, the nitride film, and the second oxide film are sequentially stacked. However, the dielectric film 15 may be formed using only an oxide film or a material having a high dielectric constant. . The thickness of the dielectric film 15 is preferably smaller than half of the critical dimension of the internal empty space of the first and second conductive films 12 and 14 for the floating gate. That is, it is preferable to form so that the internal empty space of the 1st, 2nd conductive films 12 and 14 for floating gates may not be completely filled with the dielectric film 15. FIG.

In the control gate conductive films 16A and 16B, all of the internal empty spaces of the floating gate first and second conductive films 12 and 14 and the dielectric film 15 are filled, and the first and second conductive films for the floating gate are filled. It is preferable to form the film 12 and 14 to have a predetermined thickness. The control gate conductive films 16A and 16B are preferably formed by laminating the polysilicon film 16A and the tungsten silicide films WSix and 16B, but may be formed as a single film of the polysilicon film.

Subsequently, as illustrated in FIG. 1F, the gates 17 are formed by patterning the control gate conductive films 16B and 16A, the dielectric film 15, and the floating gate first conductive film 12 by a photolithography process. do.

By the patterning process, the first conductive film 12 for the floating gate is left in a flat pattern under the second conductive film 14 for the gate having a Γ pattern, and the second conductive film 14 for the floating gate The first conductive film 12 for the floating gate operates as one floating gate. Therefore, the floating gate is formed of a U-shaped pattern due to the straight pattern of the first conductive film 12 for the floating gate and the Γ-shaped pattern of the second conductive film 14 for the floating gate. Meanwhile, the control gate conductive films 16A and 16B remain while filling the recessed portions on the upper side and the recessed side of the floating gate. Thus, the junction area between the floating gate and the control gate is increased by corresponding to the concave inner surface area of the floating gate.

Thereafter, as shown in FIG. 1G, spacers 18 may be formed on both sides of the gate 17 and the source and drain 19 may be formed on both substrates 10 of the gate 17 using a conventional device fabrication process. .

In the nonvolatile memory device formed as described above, since only the area corresponding to the thickness of the first conductive film 12 for the floating gate causes interference with the adjacent floating gate, the threshold voltage disturbance caused by the inter-floating gate interference can be reduced. .

In addition, since the control gate is formed not only on the upper portion of the second conductive film 14 for floating gate but also on the concave side of the U-shaped floating gate, filling the concave interior, the junction area between the floating gate and the control gate increases, so that the coupling ratio is increased. This increases the electrical characteristics of the device.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1G are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10: substrate

11: tunneling insulating film

12: first conductive film for floating gate

13: sacrificial film

13A: Sacrifice Pattern

14 second conductive film for floating gate

15: dielectric film

16A, 16B: conductive film for control gate

17: gate

18: spacer

19: source and drain

Claims (6)

A floating gate formed in a U-shaped pattern in which one side is concave on the substrate; A dielectric film and a control gate that are sequentially formed while filling the concave portion of one side of the floating gate on the top and one side of the floating gate. Nonvolatile memory device comprising a. The method of claim 1, The floating gate may include a first conductive film for a floating gate having a flat structure; And a second conductive film for floating gate having a? -Shaped structure formed on the first conductive film for floating gate. The method of claim 1, And the dielectric film is formed to have a thickness thinner than 1/2 of the critical dimension of the concave portion of the floating gate. Sequentially forming a tunneling insulating film, a first conductive film for a floating gate, and a sacrificial film on a substrate; Patterning the sacrificial layer; Forming a second conductive layer for the floating gate on the entire surface including the sacrificial layer; Patterning the second conductive layer for the floating gate and the sacrificial layer to form the second conductive layer for the floating gate in a Γ pattern; Removing the sacrificial layer; Sequentially forming a dielectric film and a control gate conductive film on the floating gate first and second conductive films; Forming a gate by patterning the control gate conductive layer, the dielectric layer, and the floating conductive first conductive layer Method of manufacturing a nonvolatile memory device comprising a. The method of claim 4, wherein The method of claim 1, wherein the sacrificial layer is formed of a nitride layer or an oxide layer. The method of claim 5, When the sacrificial layer is formed of a nitride layer, a method of manufacturing a nonvolatile memory device using a wet etching process when removing the sacrificial layer.

Images