KR20090043211A - Power management unit controlling wake-up sequence and method thereof - Google Patents

Abstract

The present invention relates to a wake up sequence controllable power management apparatus and method. The present invention provides at least one regulator for generating a separate output power from a common power supply to the outside / supply; An interrupt controller which receives an interrupt including a wakeup interrupt from an external device and delivers the interrupt to a main processor; A register bank in which a block to be powered up in a wake-up sequence and an order thereof are defined; And a power management controller for controlling the regulator power output supply / disconnection according to a wake-up sequence set in the register bank when a preset wake-up interrupt occurs.

According to the present invention, the wakeup sequence of the main processor and the peripheral device may be adjusted according to a preset wakeup sequence, thereby performing an efficient wakeup process in consideration of device characteristics.

PMUs, Power Management Units, Wake-up Sequences, Regulators, Sleep

Description

Power Management Unit controlling Wake-up Sequence and Method

The present invention relates to a power management device capable of controlling a wake-up sequence and a control method thereof. In particular, the wake-up sequence of the main processor and the peripheral device can be adjusted according to a preset wake-up sequence, thereby providing an efficient wake-up process in consideration of device characteristics. It relates to a wake-up sequence controllable power management device that can be performed and a control method thereof.

In general, electronic products receive a common voltage through a battery or an AC power supply, and use differentiated / transformed power to each device through an integrated power management device called a power management unit (PMU).

1 is a block diagram illustrating a system to which a general power management apparatus is applied. As shown in FIG. 1, a typical system consists of a main processor 110, a power management device 130, and devices 121-124.

The main processor 110 is a central processing unit of the system and controls the operation of system components including the power management device 130 and the devices 121 to 124.

The devices 121 to 124 are powered by the power management device 130 and operate under the control of the main processor 110. The types of devices 121 to 124 include an interrupt generating device, a memory, a real time clock (RTC), and a communication block. Etc.

The devices 121 to 124 may be broadly classified into a device that always requires power supply, a device that requires on / off control of power, or a device that requires one-time power supply.

First, a device that always needs to be powered on is a device that has a long setup time, loses internal data when a power is not supplied, or receives a command from a user.For example, internal information is erased when the power is cut off. There is an SDRAM, a wake-up interrupt generator device for waking up the main processor 110 in a sleep mode, an input device for receiving a user's command, and a real time clock (RTC) for notifying a system time.

Secondly, most devices that require on / off control of power supply are of this type, such as NAND flash which stores a large amount of data, and a communication block that wakes up and communicates at a specific time.

Third, a device that requires a one-time power supply is a device that is used only once by a specific need, and typically, there is a NOR flash that contains system boot data.

The power management device 130 receives the common power and generates or outputs an individual output power whose voltage level is adjusted, and supplies or cuts it.

The operating mode of the system to which the power management device 130 is applied is powered only on the blocks required for the active mode or the normal operating mode and the wake up to supply or cut off power of a specific device as necessary. There is a power save mode or a sleep mode to supply the power supply.

Before the system switches from the active mode to the sleep or power saving mode, the system removes power to unnecessary devices through the power management device 130 and then enters the sleep or power saving mode.

In contrast, the system wakes up from a sleep or sleep mode by a wake-up interrupt, causing the power management device 130 to deliver an interrupt to the main processor 110 and supply power to the necessary devices.

An example of a power management device according to the prior art is the IC LP3970, which consists of eleven linear regulators and two buck regulators, a power transformer block and a programmable register.

However, the output voltage change and power supply / shutdown through the LP3970 are controlled by an external processor (for example, a CPU) in an active mode, such that a power management device such as a sleep and a power-save mode is external to the power management device. If it is disconnected from, there is a problem that it cannot be controlled.

As such, the function of the power management device (PMU) according to the prior art is limited to supplying or interrupting power by transforming a common voltage to a specific power level.

2 is a time diagram illustrating a power-up sequence of a system to which a power management apparatus according to the prior art is applied. As shown in FIG. 2, the power management apparatus according to the related art may first change the device # 1 131 in the set order only after the main processor 110 wakes up t1 when switching from the sleep mode to the active mode. The device # 2 132 wakes up (t2, t3).

In other words, since the power-up sequence operates under the control of the main processor 110, the main processor 110 wakes up from the sleep state and wakes up other devices in the order set in the active state (t1) ( t2, t3).

That is, since the main processor and each device wake-up cannot be performed in parallel, the overall wake-up time is long and the power consumption rate is high.

The present invention provides a wake-up sequence controllable power management apparatus capable of adjusting an wake-up sequence of a main processor and a peripheral device according to a preset wake-up sequence and performing an efficient wake-up process in consideration of device characteristics. The purpose is to provide.

In order to achieve the above object, a wake-up sequence controllable power management apparatus according to the present invention includes an interrupt controller which receives an interrupt including a wake-up interrupt from an external device and delivers the interrupt to a main processor; A register bank in which an internal block to be powered up in a wake-up sequence and an order thereof are defined; When the predetermined wake-up interrupt occurs, it is characterized in that it comprises a power management control unit for controlling the supply of power output to the outside by operating the internal block according to the wake-up sequence set in the register bank.

At this time, the wake-up sequence controllable power management device is one or more regulators for generating an individual output power from the common power supply to the outside / cut off; The switch existing between each device from the external power supply may further include a general purpose input output block (GPIO) for outputting a control signal.

The wake-up sequence controllable power management device is further configured to transmit a timer to activate the timer to increase a timer value when the wake-up interrupt occurs and to transmit the preset wake-up interrupt to the interrupt controller in the sleep mode. The apparatus further includes a wake-up waiting block for causing a power management controller to perform an operation of starting a wake-up sequence, and a communication block for arbitrating communication between the main processor and the register bank in an active mode operating under control of the main processor.

Here, the wake-up sequence is to enter the active mode that receives the preset wake-up interrupt in the sleep mode not under the control of the main processor and operates under the control of the main processor.

According to another aspect of the invention, (a) if the wake-up interrupt occurs in the sleep mode, determining whether or not a predetermined wake-up interrupt; (b) starting to wake up according to a preset wakeup sequence if the result of the determination is a preset wakeup interrupt; (c) driving the timer to increase the timer value by a predetermined unit; (d) providing a wake-up sequence controllable power management method, characterized in that if the timer value is equal to a set value, performing a wake-up in a processor and an individual regulator according to a preset wake-up sequence; do.

At this time, the step of pre-set the wake-up sequence before step (a); It is preferable to further include the step of shutting off unnecessary power supplied to the inner block, and switching to the sleep mode.

Here, the pre-setting includes setting a wake-up time of the inner block and the processor.

Meanwhile, in step (a), the preset wakeup interrupt is an interrupt for instructing an operation of an internal block in which a wakeup time is set, and in step (d), the individual regulator wakeup (d-1) turns off the regulator power output. Producing and supplying to the outside.

Here, the wakeup is a process of entering the active mode under the control of the processor in the sleep mode.

According to the present invention, a wakeup sequence controllable power management apparatus and a control method thereof may adjust a wakeup sequence of a main processor and a peripheral device according to a preset wakeup sequence to perform an efficient wakeup process in consideration of device characteristics. have.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments are provided to those skilled in the art to fully understand the present invention, can be modified in various forms, the scope of the present invention is limited to the embodiments described below no.

3 is a block diagram illustrating a wakeup sequence controllable power management apparatus according to an exemplary embodiment of the present invention. As shown in FIG. 3, the wake-up sequence controllable power management device may include one or more regulators 110 that generate individual output powers from a common power supply and supply / block externally; An interrupt controller 120 receiving an interrupt including a wakeup interrupt from an external device and transferring the interrupt to a main processor; A register bank 130 in which a block to be powered in an wake-up sequence and an order thereof are defined; When a preset wakeup interrupt occurs, the PMU controller is configured to control the regulator power output supply / disable according to the wakeup sequence set in the register bank.

The regulator 110 generates individual output power from a common power supply and supplies / blocks it to an external device.

Here, the regulator 110 converts the AC common voltage into a DC voltage and then transforms it into a predetermined individual power output, or receives a DC common voltage including a battery, converts the power into a predetermined individual power output, and supplies / blocks it.

The interrupt controller 120 receives an interrupt including a wakeup interrupt from the outside and delivers the interrupt to the main processor.

In detail, in the sleep mode, only the wakeup interrupt is input. In the active mode operating under the control of the main processor, all interrupts supplied to the power management device are received and transmitted to the main processor.

The register bank 130 is a group of registers in which a block to be powered up and a sequence thereof are defined in a wake-up sequence, and the setting is made by a command of the main processor through the communication block 170.

The power management controller 140 is an internal center for controlling components including the regulator 110, the interrupt controller 120, and the register bank 130, which are internal components of the wake-up sequence controllable power management apparatus according to the present invention. Processing device.

The wakeup sequence controllable power management device further includes a timer 150, a wakeup wait block 160, and a communication block 170.

The timer 150 is activated when a wake-up interrupt occurs to increase the timer value. The timer value is a reference time controlled by the power management controller 140 for each block of the power management apparatus according to the present invention.

The wake-up waiting block 160 transmits the preset wake-up interrupt to the interrupt controller in the sleep mode to perform the operation of starting the wake-up sequence.

Meanwhile, in the active mode, the wake-up wait block 160 functions as a general interrupt input block.

The communication block 170 mediates communication between the main processor and the register bank 130 in the active mode.

In the wake-up sequence, a wake-up sequence receives a preset wake-up interrupt in the sleep mode and proceeds to wake up the main processor and the peripheral device. When the wake-up is completed, the system state becomes an active mode.

In other words, the wake-up sequence controllable power management apparatus according to the present invention has evolved from the power management apparatus according to the prior art to control the power supply process (power-up sequence) to reserve the wake-up sequence of devices including the main processor, and It has the advantage of being controllable.

4 is a block diagram illustrating a system to which a wake-up sequence controllable power management device is applied according to an embodiment of the present invention. The power management device of FIG. 4 further includes a GPIO block (not shown), and includes an external power supply # 1 411 and an external power supply # 2 412 and devices 431 to 434 powered therefrom. Outputs a signal to control the on / off of the power switch (421 to 424) existing between the power supply to the device or cut off.

In this case, since the power management device outputs high and low signals to control the switches 421 to 424 on / off, a regulator block for generating power among internal components may be omitted.

FIG. 5 is a flowchart illustrating a wake up sequence of a wakeup sequence controllable power management apparatus according to an exemplary embodiment of the present invention. A description with reference to FIG. 5 is as follows.

When the wakeup interrupt occurs in the sleep mode, it is determined whether the interrupt is a preset wakeup interrupt (S410).

Meanwhile, the main processor presets the wakeup sequence through internal register setting, cuts off unnecessary power, and enters the sleep mode.

Interrupts other than the preset wakeup interrupt are ignored and the wakeup sequence of the power management device is started (S410) by receiving the preset wakeup interrupt (S410).

In operation S430, the timer is increased by driving the timer along with the start of the wake-up sequence.

Thereafter, the timer value is compared with the set value (S440), and the wakeup operation is performed by the processor and the individual regulator according to the preset wakeup sequence (S450).

In detail, the power management device delivers a wake-up interrupt to the processor and generates and outputs a regulator output power to the processor according to a preset wake-up sequence.

At this time, the wakeup process continues until all of the preset wakeup sequences are executed.

FIG. 6 is a time diagram illustrating a wake up sequence of a wakeup sequence controllable power management apparatus according to an exemplary embodiment of the present invention. 6 is a diagram illustrating a case where a wake-up sequence is reserved in the order of t1, t2, and t3.

A power management apparatus capable of controlling a wake up sequence according to the present invention receives a preset wake up interrupt such as a main processor, device # 1, and / or device # 2 wake up interrupt, and according to a preset wake up sequence, Performs an operation of waking up # 1 and device # 2.

Specifically, the power management device delivers a wakeup interrupt to the main processor, and operates a regulator to supply a power output to perform an operation of waking up the devices # 1 and # 2.

As shown in FIG. 6, the power management apparatus according to the present invention may wake up another device first before the main processor wakes up, thereby enabling various applications and reducing wakeup time and power consumption.

7 is a waveform diagram of a signal generated during a wake up sequence of a wake up sequence controllable power management apparatus according to an embodiment of the present invention.

When a signal indicating to enter the sleep mode in the active mode is received (610), the unnecessary output of the regulator power output is turned off at the same time as the wake-up sequence starts.

Specifically, regulator # 1 (650), regulator # 2 (660), and regulator # 3 (670) set to unnecessary power in the sleep mode are turned off, and regulator # 4 set to the power required in the sleep mode. 680 remains state without turning off.

When the preset wake-up interrupt comes in 620, the timer 150 operates to increase the timer value (630).

When the timer value is equal to the turn on timer value of each regulator, the regulator turns on to generate and supply a power output.

In detail, the regulator # 1 650 turns on when the timer value is 6, and the regulator # 2 660 turns on when the timer value is 273 to output power.

When the timer value is equal to the preset final value, the timer is reset and turned off and the power management device operates in the active mode.

In FIG. 7, the wake-up process is terminated when the timer value reaches 278 because the preset final value is 278.

At this time, the regulator # 3 670 maintains the off state because the wake-up setting is not made.

On the other hand, the wakeup state 640 signal indicates whether the wakeup sequence is in progress. If the value is 1, the wakeup sequence is in progress. If the value is 0, the wakeup sequence is in progress.

The configuration of the present invention has been described above through the preferred embodiments and the accompanying drawings. However, these are only examples and are not used to limit the scope of the present invention. Those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom, and the true scope of protection of the present invention should be determined by the technical spirit of the appended claims.

1 is a block diagram illustrating a system to which a general power management apparatus is applied.

2 is a time diagram illustrating a wake-up sequence of a system to which a power management apparatus according to the prior art is applied.

Figure 3 is a block diagram showing a wake up sequence controllable power management apparatus according to the present invention.

4 is a block diagram illustrating a system to which a wake-up sequence controllable power management device according to the present invention is applied;

5 is a flowchart illustrating a wake-up sequence of the wake-up sequence controllable power management apparatus according to the present invention;

6 is a time diagram illustrating a wake-up sequence of the wake-up sequence controllable power management apparatus according to the present invention;

7 is a waveform diagram of signals generated during a wake up sequence of a wake up sequence controllable power management device in accordance with one embodiment of the present invention;

<Description of main parts of drawing>

110: regulator 120: interrupt control

130: register bank 140: power management control unit

150: timer 160: wake-up waiting block

170: communication block

Claims (13)

An interrupt controller which receives an interrupt including a wakeup interrupt from an external device and delivers the interrupt to a main processor; A register bank in which an internal block to be powered up in a wake-up sequence and an order thereof are defined; When a preset wakeup interrupt occurs, the power management control unit controls whether the power output is supplied to the outside by operating an internal block according to a wakeup sequence set in the register bank. Wake-up sequence controllable power management device comprising a. The method of claim 1, One or more regulators generating individual output power from a common power supply and supplying / blocking the external power; Wake-up sequence controllable power management device further comprising. The method of claim 1, GPIO block that outputs control signal to control switch existing between each device from external power supply Wake-up sequence controllable power management device further comprising. The method of claim 1, When the wake-up interrupt occurs, the timer is activated to perform the operation of increasing the timer value Wake-up sequence controllable power management device further comprising. The method of claim 1, Wake-up waiting block for delivering the preset wake-up interrupt to the interrupt controller in the sleep mode to cause the power management controller to start the wake-up sequence. Wake-up sequence controllable power management device further comprising. The method of claim 1, A communication block that arbitrates communication between the main processor and the register bank in an active mode operating under the main processor control Wake up sequence controllable power management device further comprising. The wakeup sequence of claim 1, Wake up sequence controllable power management device, characterized in that to enter the active mode operating under the control of the main processor receives the predetermined wake-up interrupt in the sleep mode not under the control of the main processor. (a) determining whether the wakeup interrupt is a preset wakeup interrupt when the wakeup interrupt occurs in the sleep mode; (b) receiving the wakeup interrupt if the wakeup interrupt is preset; (c) driving a timer with the input to increase a timer value by a predetermined unit; (d) waking up the main processor and the individual regulator when the timer value and the value set in the sequence are the same according to a preset wakeup sequence;  Wake-up sequence controllable power management method comprising a. According to claim 8, Before the step (a), Presetting the wakeup sequence; Cutting off unnecessary power supplied to the internal block and switching to sleep mode Wake up sequence controllable power management method further comprising. The method of claim 9, wherein the pre-setting comprises: Setting a wakeup time of the inner block and the main processor; Wake-up sequence controllable power management method comprising a. The method of claim 8, wherein the preset wakeup interrupt in step (a), Interrupt indicating operation of inner block with wakeup time set Wake-up sequence controllable power management method characterized in that. The method of claim 8, wherein the individual regulator wake-up in the step (d), (d-1) generating and supplying the regulator power output to the outside Wake-up sequence controllable power management method comprising a. The method of claim 8, wherein the wake-up sequence, In order to control the internal block in the process of entering the active mode under the control of the main processor in the sleep mode. Wake-up sequence controllable power management method characterized in that.

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