KR20090043049A - Method for caulking bonding using solder bumps - Google Patents

Abstract

The present invention relates to a caulking bonding method using a solder bump, and more particularly, by forming a junction between chips using a solder bump instead of the existing Au stud bump, shortening the process time The present invention relates to a caulking bonding method using solder bumps, which can minimize damage between chips and form not only mechanical joints but also metallurgical joints at the same time, thereby improving strength and electrical properties of the joints.

for teeth,

Forming a solder bump on the first wafer;

Forming a through via hole electrode on the second wafer;

Bonding a solder bump on the first wafer and a through-via hole electrode on the second wafer;

It provides a caulking bonding method using a solder bump, characterized in that configured to include.

 Solder bumps, gold stud bumps, through via hole electrodes, junctions, caulking.

Description

Method for Caulking Bonding Using Solder Bumps}

The present invention relates to a caulking bonding method using solder bumps, and more particularly, by forming a junction between chips using solder bumps instead of the existing Au stud bump, shortening the process time, chip-to-chip The present invention relates to a caulking bonding method using solder bumps, which minimizes damage and simultaneously forms metallurgical joints as well as mechanical joints, thereby improving strength and electrical properties of the joint.

In general, the most important technique for implementing 3D chip stacking is to electrically connect the stacked chips. By implementing stacking in three dimensions, more chips can be mounted in a limited space and can be used for smaller products and all products requiring intensive chips. Several processes have been developed to stack chips, among them, a method of making electrical connections between chips using metal bumps and through-via hole electrodes (Pub. No .: US 2005). / 0263869 A1) has the following advantages.

First, the electrical connection between the chips using conventional metal bump and through-via hole electrodes is chemical mechanical polishing (CMP) or through-via hole (through via). Filling process is required to fill the metal bump in the hole, but this process can be omitted, which simplifies the process,

Secondly, process costs can be reduced due to fewer process steps,

Third, the bonding can be performed at room temperature or at low temperature.

In particular, by implementing chip stacking based on this process, more needles can be mounted in a limited space and can be used for smaller products and all products requiring intensive chips.

Prior art as described above (Related Patent-Pub.No .: US 2005/0263869 A1, Related Articles-N. Tanaka, Y. Yoshimira, et al, "Low Cost Through-hole Electrode Interconnection for 3D-SiP Using Room- temperature bonding ") forms Au stud bumps on one side of the chip and through-via hole electrodes on the opposite side, thereby flipping the chip such as flip chip. Through multiple stacking techniques.

In other words, the conventional technique is a method in which a gold stud bump on one side of a chip is inserted into a side where a through-via hole electrode of another chip exists and is joined to each other. It is a technique of mechanical caulking.

This prior art is described in US 2005/0263869 A1, the content of which is a method of forming a metal bump on one side of one semiconductor chip, and connecting a plurality of chips having a through hole formed on the opposite side of the chip. A double layer design is described in which an electrode is formed inside a hole through which the electrode is formed, and the formed electrode and the metal bump are connected to form a structure for transmitting an electric signal.

However, the technique of stacking chips using the Au stud bump as described above,

First, the process takes longer because of the batch process that forms each bump separately.

Second, since the gold stud bump is relatively hard, if mis-alignment occurs during bonding between the chips, damage may occur, such as cracking of the chip.

Third, there is a problem in that the strength and the electrical characteristics of the joint is weak because only the mechanical bonding at room temperature or low temperature when bonding the chip.

The present invention has been made in view of the above, by stacking a chip using a solder bump (solder bump) instead of the existing gold stud bump (Au stud bump),

First, all bumpers can be manufactured on the wafer at the same time, reducing process time compared to conventional technologies,

Second, the solder is softer than gold, minimizing damage to the top and bottom chips that can occur during bump mis-alignment.

Third, better chip-to-chip interconnection is achieved through self-alignment of solder during chip-to-chip bonding.

Fourth, an object of the present invention is to provide a caulking bonding method using solder bumps, which can improve not only mechanical bonding but also metallurgical bonding at the same time, thereby improving the strength and electrical properties of the joint.

Calling joining method using the present invention reflow tin-based bumps as described above,

(a) forming a solder bump on the first wafer;

(b) forming a through via hole electrode on the second wafer;

(c) bonding the solder bumps on the first wafer and the through-via hole electrodes on the second wafer;

Characterized in that comprises a.

In particular, step (a),

(a-1) depositing a metal lower layer on the first wafer;

(a-2) forming metal wirings of the metal lower layer;

(a-3) forming a via hole for bump formation;

(a-4) forming copper bumps in the formed via holes;

(a-5) forming solder bumps on the copper bumps;

(a-6) heating the tin bumps above the melting point to form reflowed solder bumps;

Characterized in that comprises a.

In addition, the solder bump is characterized in that the tin bump.

The copper bumps may be formed to have a thickness of 2 µm or more and 80 µm or less, and the solder bumps may have a thickness of 10 µm or more and 500 µm or less.

In addition, the step (b),

(b-1) depositing a metal lower layer on a top side of the second wafer;

(b-2) forming metal wirings of the metal lower layer;

(b-3) forming a through via hole by etching a back side of the second wafer until reaching the metal wiring;

(b-4) forming an electrode in the formed through-via hole;

Characterized in that comprises a.

In addition, the step (c),

The solder bump on the first wafer is inserted into the through-via hole electrode on the second wafer by applying a physical force to the first wafer and the second wafer.

At this time, the physical force is characterized in that less than 0.1 MPa 100 MPa.

In a preferred embodiment, step (c) is

(c-1) contacting the solder bumps on the first wafer and the through-via hole electrodes on the second wafer;

(c-2) raising the junction temperature of the solder bumps and the through-via hole electrode to a melting point of the solder bumps above room temperature;

Characterized in that comprises a.

In a preferred embodiment, step (c) is

(c-1) raising the temperature of the solder bumps on the first wafer above room temperature to below the melting point of the solder bumps;

(c-2) contacting the solder bumps on the first wafer and the through-via hole electrodes on the second wafer;

Characterized in that comprises a.

In a more preferred embodiment, after the step (c-2),

(c-3) raising the temperature of the solder bumps on the first wafer above the melting point of the solder bumps;

Characterized in that further comprises.

According to the caulking bonding method using the solder bump of the present invention as described above,

First, solder bumps can be processed at the wafer level, reducing process time compared to conventional technologies.

Second, plastic deformation of solder bumps can minimize damage between chips that can occur during bump mis-alignment.

Third, due to the nature of the solder bumps having a low melting point, the solder self-aligns at the time of chip bonding, and can achieve better chip-to-chip interconnection,

Fourth, by inducing a reaction between the solder and the metal electrode to bond at high temperature, not only mechanical bonding but also metallurgical bonding can be formed at the same time to improve the strength and electrical properties of the joint,

Fifth, if lead (Pb) is prohibited or restricted due to environmental issues, lead-free solder can be used to solve environmental problems.

Sixth, significant commercial and economic effects are expected as it can be applied to various portable electronic products such as mobile phones and laptops in the future.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. A singular expression includes a plural expression unless the context clearly indicates otherwise. In this application, the terms “comprises” or “having” are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other It is to be understood that the present invention does not exclude the possibility of the presence or the addition of features, numbers, steps, operations, components, parts, or a combination thereof.

The present invention relates to a technique for stacking chips using solder bumps instead of using conventional gold stud bumps.

In general, in the case of solder, the plastic deformation is easy, and the melting point has a low melting point, it is an object of the present invention to solve the problems of the existing process by using such properties.

In particular, in the case of Au stud bumps, the batch process of forming each bump separately using a wire bonder increases the processing time, but in the case of solder bumps, all the wafers are at the wafer level. The process is possible, so the process time can be shortened.

In addition, since the gold stud bump is relatively hard, if the alignment error occurs during bonding, the chip may be damaged or the chip may be damaged, but in the case of solder bump, the alignment error may be poor. When generated, it is much softer than gold, so plastic deformation is easy to reduce chip damage.

In addition, as shown in FIG. 9, even when an alignment error occurs, when the joining temperature is raised above the melting point (232 ° C.) of tin during reflow bonding, the tin turns into a liquid phase and is caused by the surface tension of the liquid solder. Being self-aligned allows for better interconnection.

In addition, the conventional technology is only mechanical bonding at room temperature or low temperature, but the present invention is well reacted between the solder and the electrode to form a mechanical joint and metallurgical joint at the same time to improve the strength of the joint, electrical Can improve the characteristics.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a specimen in which solder / copper bumps are formed and reflowed using electroplating on a wafer on which a metal lower layer (UBM) is formed using a general thin film process, and a through-via hole ( After fabricating an electrode specimen having through via holes formed thereon, the two specimens are bonded by using a flip chip bonder.

In this case, the solder bumps may be tin bumps as a preferred embodiment.

Mechanical bonding by caulking at room temperature can be bonded without increasing the temperature.In case of temperature higher than room temperature and lower than melting point, mechanical bonding and metallurgical bonding by solid phase diffusion are simultaneously performed. After contacting below the melting point and raising the temperature above the melting point, metallurgical bonding by liquid solder is achieved. In addition, the bonding above the melting point is a metallurgical bonding by the liquid solder.

Hereinafter, a process of forming a solder bump will be described with reference to FIGS. 1 to 4.

First, the wafer is prepared and cleaned (11), and then the metal lower layer is deposited (12). Thereafter, metal wires are formed on the metal lower layer (13). Next, via holes for bump formation are formed (14), copper bumps and tin bumps are sequentially formed (15 and 16), and then reflow is performed to form solder bumps. (17).

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 2.

First, a SiO ₂ / Si wafer is prepared to form solder bumps (21). Trichlorethylene (TCE), acetone (Acetone, AEC), methanol (Methanol, MET) in ultrasonic treatment for 5 minutes in order to remove the organic matter and impurities on the SiO ₂ / Si wafer surface. The final wash is then done with DI water and the surface is blown with N ₂ gas.

Next, an under bump metallurgy (UBM) is deposited (22). Adhesive layer, Ti (50 nm) / Au (50 nm) / Cu (1 μm) / Ti (50) using a thin film deposition apparatus, a DC magnetron sputtering system as a preferred embodiment, to form a metal underlayer nm) are deposited sequentially. The titanium layer is used to prevent the spread of the reflowed solder bumps in the test chip measuring the connection resistance and is used only when necessary in the actual chip.

After the deposition as described above, a photo-lithography process 23 and chemical etching 24 using thin PR were used to make a wiring layer pattern for resistance measurement of bumps on the specimen. Metal lines are formed (25).

Next, a via hole for forming a solder bump is formed on the specimen on which the metal line is formed (26). In order to form via-holes, via-holes are formed using a photo-lithography process using thick PR and chemical etching.

Thereafter, copper bumps (Cn bump) and tin bumps (Sn bumps) are sequentially formed (27). First, copper bumps (2-80 μm) are formed by electroplating on a specimen in which metal lines and via holes are formed, and copper bumps are formed. The Sn bumps (10-500 μm) are formed by electroplating on the specimens with which the is formed.

The thickness of the copper bumps and the solder bumps may vary depending on the size of the bumps. As shown in FIG. 12, when the ductility of the solder is important, the thickness of the solder is larger than that of copper (120), and excessive deformation of the solder may be a problem. In the fine pitch, the thickness of the copper is made thick and the solder is formed relatively thin (121).

Finally, a reflowed solder bump is formed 28. That is, the tin (Sn) (20 μm) / copper (Cu) (5 μm) bumps formed using electro-plating are reflow tin bumps using rapid temperature annealing. Sn bump) is formed.

The solder bumps may be tin bumps as a preferred embodiment, thus forming a reflowed sn bump.

FIG. 3 shows an SEM image of a reflowed tin bump manufactured through the above process. It can be seen that hemispherical reflow tin bumps are formed on the wafer.

FIG. 4 is a diagram illustrating a process in which a semispherical tin bump is formed by reflow.

Hereinafter, a process of forming a through via hole electrode will be described with reference to FIGS. 5 to 7.

The "top side" below refers to the opposite side where the via hole is formed, and the "back side" refers to the side where the via hole is formed.

First, the wafer is prepared and cleaned (51), and then a thin film is deposited on the top side (52). After depositing the thin film, a metal line is formed (53), and a through-via hole is formed through etching on the back side (54). Finally, an electrode is formed in the formed through-via hole to complete the process (55).

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 6.

First, a silicon wafer (Si wafer) having a thickness of 100 μm is prepared to form a through-via hole electrode (61). To clean the specimen, sonicate for 5 minutes in the order of trichloroethylene (TCE), acetone (Acetone, AEC), methanol (Methanol, MET). The final wash is then done with DI water and the surface is blown with N ₂ gas.

Next, Au (50 nm) / Cu (1) using a DC magnetron sputtering system on the topside of a Si wafer to form a through-via hole electrode. Μm) / Ta (50 nm) are deposited sequentially (62).

Next, a thin PR process for forming a metal line is performed (63). A photo-lithography process to form a back side pattern on the specimen deposited at Au (50 nm) / Cu (1 μm) / Ta (50 nm) on the top side Chemical etching is performed.

Next, after attaching the glass for handling the thin substrate (64), the back side patterned specimen was subjected to a reactive hole etching method to form a via hole having a diameter of about 50 µm and a depth of 100 µm. (65).

Next, an electrode is formed in the formed via hole 66. In order to form an electrode in the specimen in which the via hole was formed, Ta was used as an adhesion layer using a DC magnetron sputtering system on the inner sidewall of the via hole. Cu (1 μm) was deposited as a wetting layer (50 nm), and then Cu (2 to 5 μm) was again formed by electroplating, followed by Au (50 nm) as an antioxidant layer. Deposit.

Finally, a pattern of the backside electrode is formed through chemical etching (67).

FIG. 7 shows an optical picture of a through-via hole formed through the above process.

Hereinafter, the bonding process of the chip will be described in detail with reference to FIGS. 8 to 12.

The bonding process of the chip is performed through the bonding process of the upper chip and the lower chip as shown in FIG.

At this time, the method of bonding the upper chip and the lower chip is largely divided into four as follows.

First, a method of inserting solder bumps on a first wafer into a through-via hole electrode on a second wafer by applying only physical force between the first and second wafers, in which case only pure mechanical bonding is achieved. At this time, the physical force has a value of 0.1 MPa or more and 100 MPa or less as a preferred embodiment.

Second, after contacting the solder bump on the first wafer and the through-via hole electrode on the second wafer, the method of raising the junction temperature of the solder bump and the through-via hole electrode below a melting point of the solder bump above room temperature; Through this, mechanical joints and metal chemical joints can be simultaneously formed.

Third, after the temperature of the solder bumps on the first wafer is raised above the melting point of the solder bumps above room temperature, the solder bumps on the first wafer and the through-via hole electrodes on the second wafer are contacted. It is possible to simultaneously form mechanical and metal chemical joints.

Fourth, after performing the bonding of the upper chip and the lower chip by the third method, by raising the temperature of the solder bump above the melting point of the solder bump, so that the solder bump can be melted into the electrode, through Maximize metal chemical bonding.

In this case, in general, melting points of main solders include tin (Pure Sn): 232 ° C, Sn-Ag: 221 ° C, Sn-Bi: 138 ° C, In: 156.6 ° C, and In-Ag: 141 ° C. Therefore, in order to generate a liquid phase bonding, bonding is performed considering the melting point.

Hereinafter, an embodiment of the bonding process will be described with reference to Tables 1, 10, and 11.

In the case of the tin-based bumps used in this example, the bonding load was 20 to 40 N, the bonding temperature proceeded from room temperature to 270 ° C. and the bonding time from 30 sec to 60 sec.

Table 1 shows the bonding conditions and the electrical properties of the junction where the specimen with reflow tin bumps and the through via hole electrode were bonded using a flip chip bonder. Indicates resistance. The experiment was carried out by varying the bonding load, the bonding temperature, and the bonding time. In all cases, it can be seen that the junction is well and has a low junction resistance.

10 shows a SEM photograph of the bonding (bonding at room temperature) by Sample 3 above. The photo on the left shows the overall joint, and the photo on the right shows the joint for one bump. As shown in FIG. 10, when bonding at room temperature, only mechanical bonding is performed by plastic deformation of the solder.

FIG. 11 shows an SEM photograph of the junction (junction at high temperature) by Sample 1. FIG. The photo on the left shows a reflow Sn bump observed at a magnification of 1500 times, and the photo on the right shows a reflow Sn bump observed at a magnification of 3000 times.

As shown in FIG. 11, the intermetallic compound (IMC) of Cu ₆ Sn ₅ is formed by the high temperature (270 ° C.) heat, and it can be seen that mechanical bonding and metallurgical bonding are simultaneously performed.

In addition, as mentioned above, when the temperature is raised above the melting point (232 ° C.) of the tin in the bonding process, the tin turns into a liquid phase and becomes self-aligned due to the surface tension of the liquid solder. Interconnetion can be implemented.

While the invention has been shown and described with respect to certain preferred embodiments, the invention is not limited to these embodiments, and those of ordinary skill in the art claim the invention as claimed in the appended claims. It includes all the various forms of embodiments that can be implemented without departing from the spirit.

1 is a flow chart illustrating a step of forming a reflow tin bump according to the present invention;

2 is a view showing a step of forming a reflow tin bump according to an embodiment of the present invention;

3 is a SEM photograph of the reflow tin bumps according to an embodiment of the present invention;

4 is a view showing that a hemispherical bump is formed by reflow,

5 is a flowchart illustrating a step of forming a through-via hole according to the present invention;

6 is a view showing a step of forming a through-via hole according to an embodiment of the present invention;

7 is a SEM photograph of a through-via hole according to an embodiment of the present invention;

8 is a view illustrating a bonding process of an upper chip and a lower chip;

9 is a diagram illustrating a self-aligning process of annotations;

10 is a SEM photograph of the room temperature junction of the upper chip and the lower chip,

11 is a SEM photograph of the 270 ℃ junction of the upper chip and the lower chip,

12 is a view illustrating shapes of solder bumps and tin bumps in various forms.

Claims (19)

(a) forming a solder bump on the first wafer; (b) forming a through via hole electrode on the second wafer; (c) bonding the solder bumps on the first wafer and the through-via hole electrodes on the second wafer; Caulking bonding method using a solder bump, characterized in that comprising a. The method according to claim 1, In step (a), (a-1) depositing a metal lower layer on the first wafer; (a-2) forming metal wirings of the metal lower layer; (a-3) forming a via hole for bump formation; (a-4) forming copper bumps in the formed via holes; (a-5) forming solder bumps on the copper bumps; (a-6) heating the tin bumps above the melting point to form reflowed solder bumps; Caulking bonding method using a solder bump, characterized in that configured to include. The method according to claim 2, The solder bump is a corrugated bonding method using a solder bump, characterized in that the tin bump. The method according to any one of claims 1 to 3, Step (a-1), Caulk bonding method using a solder bump, characterized in that for depositing the adhesive layer, the solder wet layer, and the antioxidant layer in order using a thin film deposition apparatus. The method according to any one of claims 1 to 3, Step (a-2), A method for caulking a solder bump using a solder bump, characterized in that to form the metal wiring using a photolithography process using a thin PR and chemical etching. The method according to any one of claims 1 to 3, Step (a-3), A method of caulking bonding using solder bumps, wherein the via holes are formed using a photolithography process using a thick PR and a chemical etching. The method according to any one of claims 1 to 3, The copper bumps are formed in a thickness of not less than 2㎛ 80㎛, the solder bumps 10㎛ not more than 500㎛ thickness caulking bonding method using a solder bump. The method according to any one of claims 1 to 3, In step (b), (b-1) depositing a metal lower layer on a top side of the second wafer; (b-2) forming metal wirings of the metal lower layer; (b-3) forming a through via hole by etching a back side of the second wafer until reaching the metal wiring; (b-4) forming an electrode in the formed through-via hole; Caulking bonding method using a solder bump, characterized in that comprising a. The method according to claim 8, Step (b-1), Caulk bonding method using a solder bump, characterized in that the deposition on the upper surface of the second wafer, the adhesive layer, the solder wet layer, the antioxidant layer in order. The method according to claim 8, Step (b-2), Corrugated bonding method using a solder bump, characterized in that to form a metal wiring of the metal lower layer using a photolithography process and chemical etching. The method according to claim 8, The etching method of the step (b-3) is a caulking bonding method using a solder bump, characterized in that the reactive ion etching method. The method according to claim 8, Step (b-4) is, A method of caulking bonding using solder bumps, comprising depositing an adhesive layer, a wet layer, and an anti-oxidation layer on an inner sidewall of a through-via hole using the thin film deposition apparatus. The method according to any one of claims 1 to 3, In step (c), And a solder bump on the first wafer is inserted into the through-via hole electrode on the second wafer by applying a physical force to the first wafer and the second wafer. The method according to claim 13, The physical force is caulking bonding method using a solder bump, characterized in that less than 0.1MPa 100MPa. The method according to any one of claims 1 to 3, In step (c), (c-1) contacting the solder bumps on the first wafer and the through-via hole electrodes on the second wafer; (c-2) raising the junction temperature of the solder bumps and the through-via hole electrode to a melting point of the solder bumps above room temperature; Caulking bonding method using a solder bump, characterized in that comprising a. The method according to any one of claims 1 to 3, In step (c), (c-1) raising the temperature of the solder bumps on the first wafer above room temperature to below the melting point of the solder bumps; (c-2) contacting the solder bumps on the first wafer and the through-via hole electrodes on the second wafer; Caulking bonding method using a solder bump, characterized in that comprising a. The method according to claim 16, After the step (c-2), (c-3) raising the temperature of the solder bumps on the first wafer above the melting point of the solder bumps; Caulking bonding method using a solder bump, characterized in that further comprises a. The method according to any one of claims 1 to 3, Solder bumps formed using the caulking bonding method using the solder bumps. The method according to claim 18, A plurality of chips stacked using the formed solder bumps.

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