KR20090033996A - Organic light emitting display - Google Patents

Abstract

An organic electroluminescent display device is provided to reduce the capacitance component generated between the wirings and improve the quality and reliability of display. The substrate(110) comprises a plurality of sub pixels(120). The first interconnection is located on the surface of substrate. The interlayer insulating film is positioned in order to cover the first interconnection. The second wiring is positioned in order to intersect with the first interconnection on the interlayer insulating film. Dummy insulation films(140a,140b) are positioned in one or more among the top or the lower part of the interlayer insulating film. The first interconnection is made of the scan wiring(130a) supplying the scan signal to a plurality of sub pixels.

Description

Organic Light Emitting Display

The present invention relates to an organic light emitting display device.

The organic light emitting display device used in the organic light emitting display device was a self-light emitting device having a light emitting layer formed between two electrodes.

In addition, the organic light emitting device has a top emission type and a bottom emission type depending on the direction in which light is emitted, and a passive matrix type and an active matrix type depending on the driving method. (Active Matrix), etc.

Here, the subpixel of the organic light emitting display device adopting the active matrix type includes one or more transistors, capacitors, and organic light emitting diodes, and generally has a circuit structure of 2T (transistor) 1C (capacitor) or more.

Here, the gate, source and drain electrodes of the transistor are located in the form of a thin film on the substrate. The transistor is driven by receiving a scan signal, a data signal, a power supply, and the like through a driving driver.

On the other hand, since the subpixels located on the substrate are positioned in a matrix, the wirings for supplying signals (scan signals, data signals) or power to the subpixels are interconnected. In this case, there is a problem that the display quality is deteriorated due to the capacitance component formed in the area where the wiring and the wiring cross each other, and improvement thereof is required.

SUMMARY OF THE INVENTION An object of the present invention for solving the above-mentioned problems of the background art is to reduce capacitance components occurring between crossing lines in order to improve display quality and reliability of an organic light emitting display device.

The present invention as a means for solving the above problems, the substrate comprising a plurality of sub-pixels; A first wiring positioned on the substrate; An interlayer insulating film positioned to cover the first wiring; A second wiring positioned to intersect the first wiring on the interlayer insulating film; And a dummy insulating layer disposed on at least one of an upper portion and a lower portion of an interlayer insulating layer positioned at an area where the first and second wirings cross each other.

The dummy insulating layer may be positioned to correspond to a region where the first wiring and the second wiring cross each other.

The first wiring may be a scan wiring for supplying a scan signal to the plurality of subpixels.

The second wiring may be a data wiring for supplying a data signal to the plurality of sub pixels.

The second wiring supplies power to the plurality of sub pixels. It may be a power wiring.

The dummy insulating film may be an organic or inorganic insulating film.

The thickness of the dummy insulating film may be thicker than the thickness of the insulating film.

The dummy insulating layer may have a thickness of 0.1 μm to 5 μm.

A plurality of sub pixels; One or more transistors, capacitors, and organic light emitting diodes, the transistors may be top gate or batam gate type.

The transistor may be one of an a-Si transistor, a poly-Si transistor, an oxide transistor, and an organic transistor.

The present invention provides a structure capable of reducing capacitance components generated between crossing wirings, thereby improving display quality and reliability of an organic light emitting display device.

Specific details for carrying out the invention will be described below with reference to the accompanying drawings.

1 is a plan view of an organic light emitting display device according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, a plurality of subpixels 120 may be positioned on a substrate 110 in a matrix form. The plurality of sub pixels 120 may emit light in one or more directions of the substrate 110 or the direction opposite to the substrate 110. The circuit configuration and structure of the subpixel will be described in more detail with reference to the accompanying drawings.

First, the circuit configuration of the subpixel will be described in more detail with reference to FIG. 2.

FIG. 2 is a circuit diagram illustrating a subpixel illustrated in FIG. 1.

As illustrated in FIG. 2, the sub pixel circuit shown in FIG. 1 may include a first transistor T1 having a gate connected to the scan line SCAN and a first electrode connected to the data line DATA. In addition, the second transistor T2 may include a gate connected to the second electrode of the first transistor T1 and a second electrode connected to the second power line GND. In addition, a capacitor Cst having one end connected to the gate of the second transistor T2 and the other end connected to the second power line GND may be included. In addition, the organic light emitting diode D includes a first electrode (eg, an anode) connected to the first power line VDD and a second electrode (eg, a cathode) connected to the first electrode of the second transistor T2. can do.

In such a sub pixel circuit, when the scan signal is supplied through the scan line SCAN, the first transistor T1 may be turned on. When the data signal is supplied through the data line DATA, the data voltage may be stored in the capacitor Cst through the turned on first transistor T1. Then, the second transistor T2 is turned on by the data voltage stored in the capacitor Cst, and the organic light emitting diode D connected to the first power line VDD may emit light.

Next, the structure of the subpixel having the subpixel circuit configuration as shown in FIG. 2 will be described in more detail with reference to FIG. 3.

3 is a cross-sectional view of the Z-Z region illustrated in FIG. 1.

As shown in FIG. 3, the substrate 110 may be located. The substrate 110 may be selected as a material for forming an element having excellent mechanical strength or dimensional stability. As the material of the substrate 110, a glass plate, a metal plate, a ceramic plate or a plastic plate (polycarbonate resin, acrylic resin, vinyl chloride resin, polyethylene terephthalate resin, polyimide resin, polyester resin, epoxy resin, silicone resin, fluorine) Resin, etc.) is mentioned.

The buffer layer 111 may be positioned on the substrate 110. The buffer layer 111 may be formed to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the substrate 110. The buffer layer 111 may use silicon oxide (SiO ₂ ), silicon nitride (SiNx), or the like.

The semiconductor layer 112 may be positioned on the buffer layer 111. The semiconductor layer 112 may include amorphous silicon or polycrystalline silicon obtained by crystallizing the same. Although not shown here, the semiconductor layer 112 may include a channel region, a source region, and a drain region, and the source region and the drain region may be doped with P-type or N-type impurities.

The gate insulating layer 113 may be positioned on the substrate 110 including the semiconductor layer 112. The gate insulating layer 113 may be selectively formed using silicon oxide (SiO ₂ ), silicon nitride (SiNx), or the like.

The gate electrode 114 may be positioned on the gate insulating layer 113 to correspond to the channel region of the semiconductor layer 112. The gate electrode 114 includes aluminum (Al), aluminum alloy (Al alloy), titanium (Ti), silver (Ag), molybdenum (Mo), molybdenum alloy (Mo alloy), tungsten (W), tungsten silicide (WSi). It may include any one of ₂ ).

An interlayer insulating film 115 may be positioned on the substrate 110 including the gate electrode 114. The interlayer insulating film 115 may be an organic film or an inorganic film, or may be a composite film thereof.

When the interlayer insulating film 115 is an inorganic film, the interlayer insulating film 115 may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), or SOG (silicate on glass). On the other hand, the organic film may include an acrylic resin, a polyimide resin or a benzocyclobutene (BCB) resin. First and second contact holes 115a and 115b may be disposed in the interlayer insulating layer 115 and the gate insulating layer 113 to expose a portion of the semiconductor layer 112.

The first electrode 116a may be positioned on the interlayer insulating film 115. The first electrode 116a may be an anode and may be formed in a two-layer or three-layer structure including a conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO). The description thereof will be described in more detail with reference to the accompanying drawings.

Source and drain electrodes 116b and 116c may be positioned on the interlayer insulating film 115. The source electrode and the drain electrode 116b and 116c may be electrically connected to the semiconductor layer 112 through the first and second contact holes 115a and 115b. A portion of the drain electrode 116c may be positioned on the first electrode 116a and electrically connected to the first electrode 116a.

The source and drain electrodes 116b and 116c may include a low resistance material to lower the wiring resistance. Here, the source and drain electrodes 116b and 116c may be formed of aluminum (Al), almineri (Alnd), molybdenum (Mo), chromium (Cr), titanium oxide (TiN), and molybdenum nitride (MoN). Or a metal layer such as chromium nitride (CrN).

The transistor located on the ideal substrate 110 may include a gate electrode 114, a source electrode, and a drain electrode 116b and 116c, and a transistor array having a plurality of transistors and capacitors may be electrically connected to the following organic light emitting diodes. have. (However, the structure of the capacitor is omitted) And the transistor formed here may be one of a-Si transistor, poly-Si transistor, Oxide transistor, Organic transistor.

The insulating layer 117 exposing a part of the first electrode 116a may be positioned on the first electrode 116a (eg, an anode).

The insulating layer 117 may include an organic material such as benzocyclobutene (BCB) resin, acrylic resin, or polyimide resin.

The organic light emitting layer 118 may be disposed on the exposed first electrode 116a, and the second electrode 119 (eg, a cathode) may be positioned on the organic light emitting layer 118. The second electrode 119 may be a cathode for supplying electrons to the organic light emitting layer 118, and may include magnesium (Mg), silver (Ag), calcium (Ca), aluminum (Al), or an alloy thereof. .

The organic light emitting diode connected to the source or drain electrodes 116b and 116c of the transistor included in the transistor array on the ideal substrate 110 includes the first electrode 116a, the organic light emitting layer 118, and the second electrode 119. ) May be included.

However, the first electrode 116a positioned on the source or drain electrodes 116b and 116c may be positioned on the planarization film that planarizes the surface of the transistor array. In addition, the structure of the transistor included in the transistor array may vary depending on whether the gate structure is a top gate or a batam gate. In addition, the structure of the transistor may vary depending on the number of masks used in forming the transistor array and the semiconductor layer material. Therefore, the structure of the sub pixel is not limited to this.

Referring back to FIG. 1, first and second wirings electrically connected to the plurality of sub pixels 120 and wired to cross each other may be positioned on the substrate 110. An interlayer insulating layer 113 may be positioned between the first and second wirings. The interlayer insulating film 113 may be positioned to cover the first wiring.

In addition, the dummy insulating layers 140a and 140b may be positioned on at least one of the lower part and the upper part of the interlayer insulating layer 113 positioned between the areas where the first and second wirings cross each other. In addition, the dummy insulating layers 140a and 140b may be positioned to correspond to regions where the first and second wires cross each other.

Therefore, the dummy insulating layers 140a and 140b may be positioned to cover a wide area where the first and second wires cross, or may be slightly narrower to correspond to the area where the first and second wires cross.

In this case, the first wiring may be a scan wiring 130a for supplying a scan signal to the plurality of sub pixels 120. The second wiring may include a data wiring 130b for supplying data signals to the plurality of subpixels 120 and a power wiring 130c for supplying positive power to the plurality of subpixels 120. However, depending on the manufacturing method, the first wiring may be the data wiring 130b and the power wiring 130c, and the second wiring may be the scanning wiring 130a.

Hereinafter, the structures of the dummy insulating layers 140a and 140b will be described in more detail with reference to the accompanying drawings for clarity of understanding, but are provided between the regions where the scan wiring 130a and the power wiring 130c cross each other. One dummy insulating film 140a will be described as an example.

4 is a diagram illustrating an example of the Y-Y region illustrated in FIG. 1.

As shown in FIG. 4, the buffer layer 111 may be positioned on the substrate 110, and the scan wiring 130a may be positioned on the buffer layer 111. In addition, the interlayer insulating layer 113 may be positioned on the scan wiring 130a, and the first dummy insulating layer 140a may be positioned on the interlayer insulating layer 113. In addition, the power wiring 130c may be positioned on the first dummy insulating layer 140a such that the scan wiring 130a and a partial region cross each other.

5 is another exemplary view of the Y-Y region shown in FIG. 1.

As shown in FIG. 5, the buffer layer 111 may be positioned on the substrate 110, and the scan wiring 130a may be positioned on the buffer layer 111. In addition, the first dummy insulating layer 140a may be positioned on the scan wiring 130a, and the interlayer insulating layer 113 may be positioned on the first dummy insulating layer 140a. In addition, the power line 130c may be positioned on the interlayer insulating layer 113 such that the scan line 130a and some regions intersect each other.

As shown in FIGS. 4 and 5, the first dummy insulating layer 140a may be located below or above the interlayer insulating layer 113. However, the first dummy insulating layer 140a may be located at both the lower and upper portions of the interlayer insulating layer 113.

As described above, when the first dummy insulating layer 140a is formed on at least one of the upper and lower portions of the interlayer insulating layer 113 positioned between the regions where the scan wiring 130a and the power wiring 130c intersect, parasitic capacitance is generated. Can solve the problem.

On the other hand, the parasitic capacitance generated above is because when the scan wiring 130a and the power supply wiring 130c are formed, the interlayer insulating film 113 positioned between the metal materials used as these materials serves as a capacitor.

However, when the first dummy insulating film 140a is formed on the interlayer insulating film 113 as in the present invention, the metal, insulating film, and metal structures forming the capacitor can be modified or prevented. It can solve the problem of parasitic capacitance.

As the material of the first dummy insulating layer 140a used herein, an organic or inorganic insulating layer may be selected. Here, when the interlayer insulating layer 113 is an organic insulating layer, the first dummy insulating layer 140a may be selected as an inorganic insulating layer, and when the interlayer insulating layer 113 is an inorganic insulating layer, the first dummy insulating layer 140a may be selected as an organic insulating layer. Can be. In contrast, the first dummy insulating layer 140a may be formed of the same material as the interlayer insulating layer 113.

Meanwhile, the thickness of the first dummy insulating layer 140a may be thicker than the thickness of the interlayer insulating layer 113. In this regard, the thickness of the first dummy insulating layer 140a may be 0.1 μm to 5 μm.

If the thickness of the first dummy insulating layer 140a is 0.1 μm or more, the thickness of the first dummy insulating layer 140a is greater than that of the interlayer insulating layer 113, thereby reducing the amount of parasitic capacitance generated between the scan wiring 130a and the power supply wiring 130c.

On the other hand, if the thickness of the first dummy insulating layer 140a is 5 μm or less, the scan wiring 130a and the power wiring 130c may be spaced apart as far as possible without falling down the step coverage of the power wiring 130c. have.

As a result, the amount of parasitic capacitance generated between the scan wiring 130a and the power wiring 130c is reduced. In addition, when the thickness of the first dummy insulating layer 140a exceeds a predetermined range, parasitic capacitance may be prevented even when the interlayer insulating layer 113 and the first dummy insulating layer 140a use the same material.

Therefore, the organic light emitting display device according to the present invention can provide a structure that can reduce the capacitance component generated between the wiring crossing each other on the substrate can exhibit an effect of improving display quality and reliability.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is a plan view of an organic light emitting display device according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram of the subpixel illustrated in FIG. 1. FIG.

3 is a cross-sectional view of the Z-Z region shown in FIG.

4 is a cross-sectional view of the Y-Y region shown in FIG.

<Explanation of symbols on main parts of the drawings>

110: substrate 120: subpixel

130a: scan wiring 130b: data wiring

130c: power supply wiring 140a: first dummy insulating film

140b: second dummy insulating film

Claims (10)

A substrate including a plurality of sub pixels; A first wiring disposed on the substrate; An interlayer insulating film positioned to cover the first wiring; A second wiring disposed on the interlayer insulating film so as to cross the first wiring; And And a dummy insulating layer disposed on at least one of an upper portion and a lower portion of the interlayer insulating layer positioned at an area where the first and second wirings cross each other. The method of claim 1, The dummy insulating film, And an organic light emitting display device corresponding to an area where the first and second wirings cross each other. The method of claim 1, The first wiring is, And a scan wiring for supplying scan signals to the plurality of sub-pixels. The method of claim 1, The second wiring is, And a data line for supplying data signals to the plurality of sub-pixels. The method of claim 1, The second wiring is, Supplying power to the plurality of subpixels An organic light emitting display device characterized in that the power supply wiring. The method of claim 1, The dummy insulating film, An organic light emitting display device which is an organic or inorganic insulating film. The method of claim 1, The thickness of the dummy insulating film, An organic light emitting display device thicker than the thickness of the interlayer insulating film. The method of claim 7, wherein The thickness of the dummy insulating film, An organic light emitting display device having a thickness of 0.1 μm to 5 μm. The method of claim 1, The plurality of subpixels; One or more transistors, capacitors and organic light emitting diodes, The transistor is an organic light emitting display device having a top gate or batam gate type. The method of claim 9, The transistor, An organic light emitting display device which is one of a-Si transistor, poly-Si transistor, oxide transistor, and organic transistor.

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