KR20090033435A - Rf rx front end module for picocell and microcell base station transceivers - Google Patents

Abstract

An RF Rx module adapted for direct surface mounting to the top surface of the front end of the motherboard of a picocell. The module comprises a printed circuit board having a plurality of direct surface mounted discrete electrical components defining a receive (Rx) section and path for RF signals. The signal receive section is defined by at least the following elements located under a lid which is attached to the surface of the board: a duplexer, a receive low pass filter, a low-noise amplifier, and a receive bandpass filter. At least one aperture in the board is adapted to accept a screw or the like for securing the module to the motherboard of the picocell.

Description

RF Rx FRONT END MODULE FOR PICOCELL AND MICROCELL BASE STATION TRANSCEIVERS for picocell and microcell base station transceivers

The present invention relates to a module, and more particularly, to a radio frequency reception module for use in front of a picocellular or microcellular communication base station.

Cross Reference of Related Application

This application is part of United States Application No. 11 / 452,800, filed June 14, 2006, which claims the benefit of that priority, all of which are incorporated herein by reference.

Currently, there are three types of cellular communication base stations or systems used for transmitting and receiving WCDMA and UMTS-based cellular communication signals, macrocells, microcells, and picocells. Macrocells are located on top of today's cellular towers and operate at about 1,000 watts. Macrocell coverage is several miles. Microcells are smaller than macrocells, for example, located on top of a telephone pole and covered by a number of blocks. The microcell operates at about 20 watts. Smaller microcells require about 5 watts of operating power. Picocells are base stations (approximately 8 "x 18") in size and are used inside buildings such as shopping malls and office buildings and output about 0.25 watts of power. Picocell's coverage is about 50 yards.

All picocells and microcells in use today include "motherboards" on which various electronic components are mounted. The front end of the motherboard (ie the RF transceiver part approximately located between the picocell antenna and the mixer) is currently known in the art as a "node B local area front end," ie a picocell or microcell in which radio frequency controlled electrical components are mounted. It is said to be part of.

The present invention replaces RF Rx (receive) components typically used in Node B local area Rx (receive) paths and / or complements existing RF Rx (receive) components to provide dual Rx diversity. Provides a small shear RF component module.

The present invention is used at the front end of a picocell or microcell base station comprising a printed circuit board having a plurality of individual electrical components directly mounted thereon, the antenna of the picocell or microcell at one end and the picocell or micro at the other end. A module for receiving a cellular signal between each output pad on a cell's motherboard.

In one embodiment, the module includes at least a duplexer, a receive low pass filter, an optional attenuator pad, a low noise amplifier, and a receive band pass filter. The duplexer, receive bandpass filter and low noise amplifier are all preferably located under the cover. The duplexer, receive low pass filter, and receive band pass filter provide distributed filtering of the received cellular signal, i.e., the cellular signal received via the picocell or microcell antenna. Openings in the substrate accommodate screws and the like for securing the module to the consumer's motherboard.

Other advantages and features of the present invention will become more readily apparent from the following detailed description of the preferred embodiments, the accompanying drawings and the claims.

These and other features of the present invention will be fully understood from the following description of the accompanying drawings.

1 is a simplified block diagram illustrating the flow of cellular signals through various RF components that define the shear receiving module of the present invention.

2 is an enlarged perspective view of the shear receiving module according to the present invention.

3 is an enlarged plan view of the shear receiving module with the cover removed from FIG.

4A and 4B are top and bottom perspective views, respectively, of the front end receiving module cover of the present invention.

5 is an enlarged bottom view of the shear receiving module of the present invention.

6 is a schematic diagram of the electrical circuit of the shear receiving module of the present invention.

7 is a graph of the receive gain performance of the receiving module of the present invention.

8 is an enlarged simplified plan view of a printed circuit board of the front end module of the present invention.

While the invention may be embodied in many different forms, the specification and drawings illustrate only one preferred embodiment for use in picocells as an example of the invention. However, the invention is not intended to be limited to the described embodiments, but is also extended to, for example, microcells.

In the selected figures, a single block or cell may represent several individual components and / or circuits that collectively perform a single function. Likewise, one line may represent several individual signal or energy transfer paths for performing a particular operation.

1 is a simplified block diagram of a radio frequency (RF) shear receiving module, constructed in accordance with the present invention and generally indicated by reference numeral 20, used with a picocell or microcell.

As will be described in detail below, the receiving module 20 comprises three separate RF filters, i.e., a duplexer 34, a low pass filter (LPF) 36, of the receive path (i.e., the RF signal receive path) and Distributed filtering is performed using a receive band pass filter (Rx BPF) 40. The module 20 is used in particular in the 3G broadband CDMA market, in particular in the Universal Mobile Telecommunications Service (UMTS).

Module 20 replaces the RF receiving component used in the receive path in front of the UMTS Node B local area (and / or complements according to the desired application as described in detail below). Module 20 complies with the TS25.104 R6 standard and allows the consumer to select different values for receiver sensitivity, selectivity and output power. In addition, module 20 is RoHS compliant and lead-free. Some features of module 20 as described above and described in more detail below include isolation and harmonic suppression with a low noise amplifier including a bypass mode that increases receive linearity. Includes an excellent distributed filtering configuration.

7 shows the receive gain performance characteristics of the module 20 of the present invention. Basic module operating parameters providing the performance shown in FIG. 7 are summarized in Tables A-D as follows.

Referring now to FIG. 1, module 20 is understood to be defined by a plurality of individual RF receiving electrical components and pins defining an RF signal receiving section or receive path.

The receiving unit or receiving path of a signal (ie, a received signal) received from a picocell or microcell antenna (not shown) and a signal transmitted through the module 20 will be described with reference to FIG. A first pass through a pin and a duplexer 34 of the type manufactured by CTS, Indiana, Elkhart, and received from the picocell or microcell antenna (not shown), transmitted from left to right, that is, clockwise.

The duplexer 34 is, of course, configured to pass the received signal clockwise of the received low pass filter 36. According to the present invention, the receive low pass filter 36 reduces the harmonics of the duplexer 34 to ensure that any spurious response up to 12.75 GHz is attenuated above -30 dB. The received signal from the low pass filter 36, generally indicated by arrow 41, can optionally pass through a 3 dB attenuator pad 37 (consisting of individual resistors R5, R6 and R8, as detailed below). Then, it passes through a low noise amplifier (LNA) 39.

According to the invention, the attenuator pad 37 is optional and makes the receive chain less sensitive and makes the receiver more linear, ie an environment in which other devices operate very close to the picocell, for example. Node B may be used to decompress the receive chain. If the sensitivity is to be increased at the expense of linearity, the pad 37 may have a different value. Of course, the pad 37 may optionally be omitted entirely. All 3GPP specifications are met even when placing a 3dB pad 37.

The low noise amplifier 39 is connected to the VLNA (LNA supply voltage) pin 9 and the LNA (low noise amplifier) gain select pin 10. The LNA has a noise figure of 1.3 dB and a gain of 14 dB in normal or bypass mode, and typically has a 4.3 dB NF and -3 dB gain. LNAs are designed to operate within a very linear and distributed duplexer architecture.

The received signal is then transmitted from the low noise amplifier 39 and also via an Rx BPF (receive bandpass ceramic filter) 40 of the type manufactured and sold by CTS of Elkhart, Indiana. The receive signal 41 passes through the six receive output signal pins from the receive bandpass filter 40, which pins correspond to the corresponding receive output signal pads on the motherboard of the picocell or microcell as described below. And extends between the top and bottom surfaces of the module 20 for direct surface coupling.

In accordance with the present invention, receive bandpass filter 40 operates in conjunction with duplexer 34 to provide greater than 80 dB of reception for transmit isolation. In addition, filter 40 assists in providing the close-in blocking necessary to comply with the TS25.104 R6 standard. One of the most challenging aspects of the TS25.104 R6 standard is the blocking requirement from 15dB to 20dB shear attenuation at 1.9GHz and 2GHz.

2-5 and 8 show one embodiment of a module 20. As a background, the module 20 shown in FIG. 2 has dimensions of about 25.0 mm in width, 30.5 mm in length, and a maximum of 6.75 mm in height (including the attached cover), and as described above, in a building such as a shopping mall or an office building. It is understood that it is mounted on a motherboard of 8 inches by 18 inches of picocell, which is used as a cellular signal transmission base station. Typical output power of picocells is about 250 mW. The frequency of the received signal received by the picocell is between about 1920 and 1980 MHz and the low noise amplifier supply voltage is between about 4.5 and 5.5 volts and typically about 5.0 volts.

In the illustrated embodiment, the module 20 first comprises a printed circuit board or substrate 22 consisting of four layers of dielectric material such as GETEK® in the illustrated embodiment and having a thickness of about 1 mm (ie, 0.040 inch). do. Certain areas of the substrate 22 are covered with a material such as copper and a solder mask material, both of which are applied to the substrate and / or selectively removed as known in the art to provide various copper, dielectric materials. And a solder mask region is formed on the substrate 22. The metallization system is preferably electroless nickel / immersion gold (ENIG) on copper.

The lid 45 covering about two thirds of the area of the printed circuit board 22 is Cu / Ni / Sn (copper / nickel / tin) for ROHS compliance purposes as detailed below and as detailed in FIGS. 4A and 4B. It is preferably a brass alloy comprising this plated material. The region of the upper surface of the substrate 22 located above the copper wire or strip 47 defines a portion of the substrate 22 covered with the lid 45 as described in detail below. The cover 45 functions as a dust shield and a Faraday shield.

The substrate 22, which is usually rectangular, has an upper surface 23 (FIGS. 3 and 8), a lower surface 27 (FIG. 5), and an upper or lower surface 42 or 44 and side or edges 46 and 48 ( It has an outer peripheral edge defining FIGS. 3 and 5). Although not described in greater detail, in a preferred embodiment, the substrate 22 is well known in the art, such as, for example, a bottom RF ground plane layer, an RF intermediate signal layer, a top RF ground layer, and a top DC layer and a ground layer. It is understood that a plurality of layers are stacked of appropriate dielectric materials located between each layer of conductive material.

Castellations 35 and 37 are defined and located near the outer periphery of the substrate 22. The castelation 35 defines the various ground and DC input and output pins of the module 20, while the slots or castels 37 receive tabs of the lid 45 as described in detail below. do.

Module 20 defines all 13 pins in Table E which summarize the symbols and functions.

The castelation 35 is defined as a metallized semicircular groove recessed at each edge 42, 44, 46, 48 and extends between the upper and lower surfaces 23, 27 of the substrate 22, respectively. do. In the illustrated embodiment, the castelation 35 is defined as a plated through-hole cut in half at the time of manufacture of the substrate from the array. The castellation 35 extends in parallel and spaced apart along the longitudinal direction of each edge of the substrate 22. In the embodiment shown in FIGS. 3 and 8, the upper edge 42 has four spaced castels 35, and the lower edge 44 has three spaced castels 35, the side edges ( 46 and 48 each define one castellation 35, respectively.

Each of the lateral edges 46, 48 defines a pair of metallized castels 37 spaced opposite each other. Each castellation 37 is defined by an elliptical groove extending or extending into each substrate side edge 46, 48. All castels are located on copper wire or copper strip 47.

The outer surface of each castel 35, 37 is coated with a conductive material such as a copper layer by electroplating or the like, which material is first known during the manufacturing process of the substrate 22 as is known in the art. Is applied to all sides of the substrate 22 and removed from optional portions of the surface to define the copper coated castels 35, 37. The castels 35, 37 and in particular the copper thereon form an electrical path between the upper surface 23 and the lower surface 27 of the substrate 22.

The castelation 37 may be grounded. Copper extends around the upper and lower edges of each of the castels 35 and surrounds the upper surface 23 of the substrate 22 and surrounds the upper edges of each castel 35, such as copper. A band or pad of 35a is defined (FIGS. 3 and 8), and a plurality of generally rectangular strips 35b extend inwardly from the bottom edge of each castel 35 so that the bottom of the substrate 22 is lower. A plurality of pads defined on the face 27 are defined (FIG. 5).

All pads and castels defined on the bottom surface 27 of the substrate 22 are directly reflow soldered or the like to the corresponding pads where the module 20 is located on the surface of the motherboard of the picocell (not shown). Allow surface mount. All pads and castels form a suitable electrical path between the upper and lower substrate surfaces.

According to the present invention, as described in detail below, the pads 35a and 35b of the castels 35 defining pins 9 and 10 are not ground pins and thus are not covered with a material such as copper. Each region (35c in FIG. 8, 35d in FIG. 5) of the upper and lower surfaces of the substrate 22 is surrounded by a region of the substrate dielectric material.

Each castellation 37 is formed on the upper surface 23 and the lower surface 27 of the substrate 22, respectively, and a conductive material such as copper surrounding the upper and lower peripheral edges of the respective castellation 37, respectively. The band or pad of (37a in FIG. 3, 37b in FIG. 5) is further defined.

Each of the upper castels 37 further extends from each copper strip 37a to enclose each upper castel 37 and edge strips of conductive material such as copper extending around the upper edge of the substrate 22. (corner strip) (37c in FIG. 3), while the strips 37a of each lower castelation 37 are spaced apart and parallel to the upper and lower substrate edges 42 and 44, respectively, and extend therebetween. Are connected to the ends of each expanded copper strip or line 47. The edge strip 37c on the left side of the substrate is spaced apart from the strip 35a of the castel 35 that defines the LNA gain select pin 10.

A strip of material such as copper 37e (FIG. 3) is formed between the castel 35 extending along the left substrate edge 48 and the upper castel 37 also extending along the left substrate edge 48. Extends at and electrically connects the castelation 35 to the upper castelation 37.

A strip of copper or the like material 37f (FIG. 3) extends along the right substrate edge 46 between the castel 35 and the lower castel 37, defining ground pin 5, to electrically connect them. Connect it. In addition, an extension band 37g (FIG. 3) of a conductive material such as copper defines one end of the right edge band 37c along the upper substrate edge 42 and the VLNA pin 9 as described in detail below. It will be appreciated that it extends between the other ends of the castelation 35. The strip 37g extends along the edge strip 37c, the castration 37 of the right substrate edge 46, and the upper peripheral substrate edge 42, and grounds 7 and 8 as detailed below. It is electrically connected to the two castels 35 defining the pins (FIG. 3).

However, the left end of the strip 37g is spaced apart from the castel 35, which defines pin 9 VLNA and is not electrically connected thereto. Another short strip 37h of copper or the like material (FIG. 3) defines the castelation 35 defining VLNA pin 9 and the LNA gain select pin 10 extending along the upper peripheral substrate edge 42. It is spaced apart without contact between the castels 35 and extends along the upper peripheral substrate edge 42.

Each of the right and left edges 46 and 48 also has a pair of spaced apart conductive vias defining pins 4, 6, 12 and 13 of the module 20 as described in detail below. (38) is defined and included. The via 38 is spaced from each edge and extends through the substrate 22 between the top and bottom surfaces 23 and 27 and, as is known in the art, an inner cylinder plated with a conductive material such as copper. Define the surface. According to the present invention, a constant 50 ohm is achieved by using vias 38 spaced from the edges 46 and 48 of each substrate instead of the castels 35 defined at the edges 46 and 48 of each substrate. Ensure the characteristic impedance. Each upper opening of the via 38 is an area 38a of dielectric substrate material (FIGS. 3 and 8), i.e., the substrate 22 from which the conductive copper material has been removed by etching, laser treatment, or the like, well known in the art. Surrounded by the area of.

The bottom opening of each via 38 on the bottom surface 27 of the substrate 22 is surrounded by a conventional rectangular pad 38b (FIG. 5) of a conductive material such as copper. The pad 38b is surrounded by the area 38c of the bottom surface 27 of the substrate 22 from which the copper material has been removed, as is known in the art during the manufacturing of the substrate 22.

Thus, as shown in FIG. 3, all of the castels 35, castels 37, and vias 38 are spaced apart along the edges 46, 48 of each substrate. Each of 35 and vias 38 is located between the castellation 37 pairs and all of the copper strips 47 described above, and the lower via 38 is located below the copper strips 47. Lower vias 38 of each side edge 46, 48 are located oppositely.

The duplexer 34, receive low pass filter 36, receive band pass filter 40, and receive low noise amplifier 39 are all mounted on the top surface area of the substrate 22 over the expansion copper strip 47 to cover. To cover with (45).

In particular, as shown in FIG. 3, the receive bandpass filter 40 is located in the upper right corner of the substrate 22 and is generally in the longitudinal direction adjacent to and parallel to the upper longitudinal edge 42 of the substrate 22. Extends. The sixth received signal output pin is located adjacent to the side substrate edge 46 generally opposite the right end face of the filter 40. Ground pins 7 and 8 are located along the upper edge 42 in a direction generally opposite the longitudinal upper edge of the filter 40.

Ground pin 1, pin 2 N / C (no connection) and pin 3 N / C (all defined by each castelation 35) each have a lower longitudinal edge 44 of the substrate 22 It is located from left to right along the street.

Each of the 4th Tx I / P (transmit input) pin, the 5th ground pin, and the 6th receive output pin are positioned spaced from bottom to top along the right extended edge 46 of the substrate 22. The 4th N / C pin is located below the copper strip 47. The sixth receive output pin and the fourth N / C pin are located above the copper strip 47 and defined by each of the vias 38 described above, while the ground pin 5 is defined by one of the castels 35. Is defined. The castration 37 is defined at the edge 46 between the band 47 and the castelation 35 defining pin # 5. Another castellation 37 is defined at the edge 46 between the upper substrate edge 42 and the via 38 defining pin 6.

Each of the GND 7 (GND) pin, GND 8 (GND) pin, VLNA (Voltage Low Noise Amplifier) pin 9, and LNA gain select pin 10 (FIG. 3) are each spaced from right to left to the top of the substrate 22 It extends along the longitudinal edge 42. Pins 7, 8, 9 and 10 are each defined by each castel 35 as described above.

Each of the 11 GND (ground) pin, 12 antenna pin, and 13 N / C (no connection) pins extend along the left edge 48 of the printed circuit board 22 from top to bottom. As described above, pins 12 and 13 are defined by each via 38, and pin 11 is defined by the castelation 35. Pin 13 is located below the copper strip 47. Pins 12 and 13 are located above the copper strip 47.

Pins 2, 3, 4 and 13 define the unused / disconnected pins of the transmit path / part of module 20.

The duplexer 34, where a ceramic monoblock configuration with a insertion loss of about 1.3 dB at the receiving side, is preferred, is generally adjacent to and parallel to the left edge 48 of the substrate 22 and above the copper strip 47. Located parallel to the top surface of the substrate. RF antenna pin 12 is located adjacent to the substrate edge 48 and generally located opposite the duplexer 34.

The receive low noise amplifier 39 is spaced apart from the left side of the receive passband filter 40 and is generally located in the upper left corner of the substrate 22 and is located adjacent to the left edge 48 of the substrate 22 and spaced apart from the duplexer. Above it at 34; The VLNA pin 9 and the LNA gain select pin 10 are generally located above the receiving low noise amplifier 39 and defined along the substrate edge 42. Receive low noise amplifier 39 has a noise figure of 1.3 dB and a gain of 14 dB in normal mode or bypass mode, and typically has a 4.3 dB NF and -3 dB gain. The low noise amplifier 39 is designed to operate within a linear, distributed duplexer architecture.

As a background, it is known that the local area Node B needs to have a reception sensitivity of at least -107 dBm (12.2 Kbps) to meet the TS25.104 R6 standard. This is equivalent to a system noise figure of about 19dB (actual noise figure requirements vary with the degree of other system damage). Local area Node B needs to have higher input linearity compared to wide area Node B. To meet the TS25.104 R6 standard, the system IIP3 needs to be about -10dBm (add some dB margin for deviation in the receive chain). However, if the environment deployed for the local area Node B is very rough in terms of interference, the system IIP3 close to 0 dB is more likely to be a common goal.

The receive low pass filter 36 is generally slightly spaced between the receive low noise amplifier 39 and above the duplexer 34 and spaced apart and parallel to each of the amplifier 39 and the duplexer 34, slightly at the right edge of the amplifier 39. It is located on the upper surface of the substrate 22 to the right. Ground pin 11 is generally defined at the edge 48 opposite the filter 36. Filter 36 reduces the harmonic response of duplexer 34. This ensures that any spurious up to 12.75 GHz is attenuated by -30 dB or more.

The filters 34, 36, and 40 are used together to define a distributed filtering scheme that provides the necessary "blocking" functionality. As a background, one of the most challenging aspects of the UMTS standard is known to be " blocking " in the reception design, i. In a typical wireless system design, the duplexer provides more than 30 dB of out of band attenuation with attenuation of at least 20 dB from 0 Hz to 1.9 GHz and from 2.0 GHz to 12.75 GHz to protect the radio signal from "blocking". Of course, this is difficult for a 60 MHz wide filter, which typically has an insertion loss of less than 1 dB. Most duplexers that can provide this feature have eight poles and can be 11 inches by 9 inches by 3 inches (28 cm by 23 cm by 7.6 cm). Of course, module 20 is not large enough to accommodate such a large duplexer, so "blocking" and the required close in rejection are achieved using the three dispersion filters 34, 36, 40 described above.

Referring now to FIGS. 4A and 4B, the cover 45 includes a top wall or roof 46, a pair of top and bottom walls 49a and 49b and a pair of side walls 51a and 51b extending vertically downwards therefrom. Each includes. The walls 49a, 49b, 51a, 51b define the lower longitudinal edge 53. The lower longitudinal edge 53 of each sidewall 51a, 51b defines at least two spacing tabs 50 protruding downward therefrom and fitting to each through-slot or castel 37 ( fitting to position and secure lid 45 to substrate 22 and a substrate 22 in a grounded relationship, and to the lower longitudinal edge 53 of each lid wall 49a, 49b, 51a, 51b. ) Is placed on the copper strip 47, the copper pad 35a of the castel 35, the copper pad 37a of the castel 37 and the copper strips 37c, 37e, 37f, 37h, 37g. A grounded lid 45 is provided.

The lower longitudinal edge 53 of each wall further defines a plurality of individual notches 54. In particular, notches 54a and 54b are defined between tabs 50 at each sidewall 51a and 51b. Two additional notches 54c and 54d are defined in the upper wall 49a adjacent to the side wall 51a and one additional notch 54e is defined in the lower wall 49b.

6 is a schematic diagram of the electrical circuit of the front end module 20 of the present invention. Reference numerals and descriptions for each of the illustrated electrical components are defined in Table F below and shown in FIGS. 3, 6, and 8.

The circuit of the module 20 will be described with reference to FIGS. 3, 6 and 8. First, although not shown, the received signal received through the antenna pad and the antenna pad of the motherboard of the picocell or microcell on which the module 20 is seated first receives the lower pad 38b of antenna pin 12 of the module 20. It is understood that it is passed through the substrate 22 and through the circuit line 118 to the input terminal 3 of the duplexer 34 located on the upper surface of the module 20. The input terminal 4 of the duplexer 34 is connected to ground through a circuit line 117.

Input terminal 1 of duplexer 34 is also connected to ground through circuit line 117a. Resistor R7 extends through circuit line 117a between input terminal 1 and ground. This 50 ohm resistor R7 properly terminates the unused transmit port of duplexer 34 to ground. The received signal passes through the duplexer 34 (F1) and is input to the second input terminal of the received low pass filter 36 (F3) via the second output terminal and the circuit line 58. Ground terminal 3 of the second circuit line 56 or receive low pass filter 36 at the input stage connects the filter 36 to ground.

Although not described in greater detail, it will be understood that the terms "circuit line" and / or "ground" as used herein refer in some cases to circuit elements such as suitable pads on the surface of the substrate 22.

Receive low pass filter 36 includes two output circuit lines 60, 61 extending from output terminals 4 and 1, respectively. The output line 60 connects the output terminal 4 of the filter 36 to the ground pin 11. In addition, the circuit line 60 is connected to the ground through the circuit line 62 connected to the circuit line 60 at the node N1. Node N1 is located on circuit line 60 between output terminal 4 and ground pin 11 of receive low pass filter 36. The output line 61 extends between the first output terminal of the filter 36 and the third input terminal of the amplifier 39 (U2).

From the output terminal 1 of the filter 36, the received signal passes through the circuit lines 61 and goes through resistors R5, R6, R8 to form an optional attenuator pad 37. The resistor R6 extends along the circuit line 61. Resistor R5 extends between node N1a and ground on a circuit line 61a located above resistor R6, and resistor R8 extends between node N1b and ground under resistor R6. It extends on the circuit line 61b.

Inductor L7 extends on circuit line 61c extending between node N1c and ground under resistor R8. The capacitor C14 is located between the resistor R6 and the third input terminal of the low noise amplifier 39 on the circuit line 61. Node N1c is located on circuit line 61 between capacitor C14 and node N1b.

The low noise amplifier 39 has additional terminals 1, 2, 4, 5 and 6. The input terminal 2 of the amplifier 39 is connected to the ground pin 8 through the node N2 on the circuit line 61d extending between the input terminal 2 and the ground pin 8. The input terminal 1 of the amplifier 39 is connected to the VLNA pin 9 through the circuit line 63. Capacitor C2 is connected between node N3 on circuit line 63 and ground. Capacitor C3 connected in parallel with capacitor C2 extends between node N4 on circuit line 63 and ground. Capacitor C3 is located between capacitor C2 and pin 9 VLNA. The resistor R2 is connected between the node N4 and the VLNA pin 9 on the circuit line 63. The node N3 is located between the input terminal 1 of the low noise amplifier 39 and the node N4 on the circuit line 63. The node N4 is located between the node N3 and the resistor R2 on the circuit line 63. The resistor R2 is located between the node N4 and the node N5 on the circuit line 63. The node N5 is positioned between the resistor R2 and the VLNA pin 9 on the circuit line 63.

Resistors R5, R6, and R8 are all located above the duplexer 34 on the substrate 22. The inductor L7, which forms part of the matching network for the low noise amplifier 39, is located above the resistor R8 on the substrate 22. Capacitors C2, C3 and C14 are located above resistor R6 and to the left of amplifier 39 on substrate 22. The resistor R2 is located between the upper substrate edge 42 and the amplifier 39 and to the right of the capacitor C3 in the substrate 22.

Terminal 4 of the low noise amplifier 39 (ie, the reception signal output terminal) is connected to the input terminal 1 of the reception band pass filter 40 through the circuit line 70. Capacitor C4 is connected between node N6 on circuit line 70 and ground. The inductor L4 and the capacitor C16 are connected in series between the node N7 on the circuit line 70 and the ground through the circuit line 72. The inductor L1 and the capacitor C13 are connected in series between the node N7 and the first input terminal of the reception band pass filter 40 on the circuit line 70. In addition, the resistor R4 is connected between the node N9 on the circuit line 72 and the node N5 on the circuit line 63 through the circuit line 74. The node N6 is positioned between the output terminal 4 of the low noise amplifier 39 and the node N7 on the circuit line 70. Inductor L1 is located between node N6 and node N7 on circuit line 70. Node N9 is located between inductor L4 and capacitor C16 on circuit line 72. The node N5 is located between the resistor R2 and the VLNA pin 9 on the circuit line 63.

Capacitor C15 is connected between node N10 on circuit line 74 and ground. Node N10 is located between node N9 and resistor R4 on circuit line 74.

Output terminal 5 of the low noise amplifier 39 is connected to ground through a circuit line 76.

An output terminal 6 of the low noise amplifier 39 is connected to a gain selecting pin 10 through a circuit line 84. The resistor R1 is connected between the sixth output terminal of the low noise amplifier 39 and the tenth gain select pin on the circuit line 84. Capacitor C1 is connected between node N11 on circuit line 86 and ground. Node N11 is located between resistor R1 and gain select pin 10 on circuit line 86.

Capacitor C1 and resistor R1 are positioned between substrate edge 42 and amplifier 39 at substrate 22. Resistor R4, capacitors C15 and C16, inductor L4 and capacitor C4 are all located on the substrate 22 between the right edge of amplifier 39 and the left edge of duplexer 40. Inductor L1 and capacitor C13 are both located below the lower left edge corner of duplexer 40 on substrate 22.

The input terminals 3, 5, 7, 9, 11 and 13 of the filter 40 (F5) are all connected to the ground through a common circuit line. The received signal passes through the output terminal 2 of the receive band pass filter 40 and is input to the receive output pin 6 through the circuit line 78. Output terminals 4, 6, 8, 10, 12, and 14 of the filter 40 are all connected to the ground pin 7 through the common circuit line 81.

Although not described in more detail herein, the various copper regions and bands identified and described above may remove copper material from selected portions at the top and bottom surfaces 23 and 27 of the substrate 22 during substrate fabrication, as is well known in the art. It will be understood that it is defined and formed as a result of removal and / or applying a layer or strip of solder mask material over a preselected portion of the copper layer.

As shown in FIGS. 3, 5, and 8, the selection region on the substrate 22 includes a region of the substrate dielectric material, the other selection region on the substrate 22 includes a region of the substrate, and the copper material It will be appreciated that another selected area of the area is covered with the silver solder mask material and includes the area where the copper material is exposed.

The choice of copper connection pads, strips and regions allows soldering of the terminals of various electronic components of the module 20 of the present invention directly to the top surface 23 of the substrate 22 and the bottom surface 27 of the substrate 22. Several terminals and pads are used for solder attachment directly to the terminals and pads on the top surface of the motherboard of the picocell or microcell. In other words, the choice of exposed copper pads, strips, and regions allows solder to be applied thereto, as is well known in the art.

In particular, although not shown, the printed circuit board 22 includes a plurality of different sizes and shapes located below the receive pass band filter 40, the low noise amplifier 39, the low pass filter 36, and the duplexer 34. It is understood that the same is provided with connecting copper pads (not shown) to allow surface solder mounting directly to the substrate 22. Copper connection pads (not shown) of different sizes and shapes are also suitably located under each resistor and capacitor constituting the circuit of the module 20.

The substrate 22 also extends between the top surface 23 and the bottom surface 27 of the substrate 22, as is well known in the art, and grounds between the top and bottom surfaces and any intermediate metal layers that make up the substrate 22. A plurality of first ground through holes 134 (FIG. 8) are electrically connected to each other. Each inner surface of the through hole or via 134 is coated with a conductive material layer, such as copper, by treatment such as electroplating, as is well known in the art. The through holes 134 are dispersed over the surface of the substrate 22.

Referring to FIG. 5, it will be understood that the bottom surface 27 of the substrate 22 further defines a plurality of copper pads 138 that are generally rectangular. The copper pads 138 are separated by strips 140 of solder mask material.

Substrate 22 also includes at least one opening 150 defining a through-way for a heat sink and screws or the like (not shown) that secure module 20 to the consumer's motherboard. Define to improve the thermal contact between the motherboard and the module 20. In the present embodiment, the opening 150 is located below the copper strip 47 and to the left of the power amplifier 26.

The process of assembling the module 20 involves the following steps. After fabricating the substrate 22, i.e., forming all of the appropriate copper castellation, copper strips, copper vias, copper pads, and copper through holes thereon, Ag / Sn (silver / tin) solder, as described above. Is applied onto a 2.6 " x4.6 " printed circuit board array, in particular a layer and strip of solder mask material as is well known in the art, followed by screen printing on each surface of the appropriate solder pads and strips defined on the array. The solder is applied to all surfaces of the designated copper strips, pads and regions, and then all electrical components, including all filters defining module 20, are properly placed and positioned on the array.

Next, the lid 45 is placed on the appropriate portion of the substrate 22 and soldered as described above, and a suitable castelization / slot defined at each side edge 46, 48 of the substrate 22 37, fitting the tab 50 so that the lower edge of the lower wall 49b of the lid 45 rests on the copper strip defining line 47, and the lower edge of the upper wall 49a is the upper substrate edge 42. Adjacent each other and extending above each copper strip and pads 35a, 37c, 37g, 37h as defined above, the lower edge of each sidewall 51a, 51b of the lid 45 being the edge of each opposing substrate. The lid 45 is properly positioned and secured to the substrate 22 so as to rest on each copper strip and pads 35a, 37a, 37c, 37e extending along 46 and 48. Of course, placing the lid 45 in contact with a preselected area of copper strips and pads on the substrate 22 defines the module 20 to which the lid 45 is electrically grounded.

The notches 54 defined at the lower peripheral edges of the walls 49 and 51 of the cover 45 provide a continuous ground plane around the cover 45, while simultaneously covering the cover 45 and the exposed dielectric material or solder mask. A gap is provided between selected portions of such a substrate 22 comprising material, which selection portions are located over individual vias 38 that define, for example, antenna pin 12 and receive pin 6 receiving output pins. Such as notches 54a and 54b, located above the areas surrounding pins 8 and 9 and notches 54c and 54d, and notches 54e located above the selected circuit line, i.e., the area not to be grounded. Will also be understood. The module 20 is then reflow soldered at a temperature of up to 260 ° C. to connect all components and the lid 45 to the substrate.

Finally, the array is cut as is well known in the art, and the individual modules 20 are finally checked and "tape and reel" ready for shipment.

While the present invention has been described with particular reference to embodiments of modules used in the front end of picocells, those skilled in the art may vary in form and detail without departing from the spirit and scope of the invention as defined in the appended claims. It will be recognized. The described embodiments are to be considered in all respects only as illustrative and not restrictive.

For example, at least the following non-exclusive exemplary embodiments, that is, the described embodiment in which the receiving module 20 is used in place of the individual receiving components typically used for the Node B local area front end receive path; An alternative embodiment wherein the receiving module 20 is intended to be used in conjunction with, i.e., complementary to, the individual receiving components now commonly used in the Node B local area front end receive path to provide dual receive diversity in the second dual receive path; Receive module 20 is used in conjunction with the front-end module described in pending US patent application Ser. No. 11 / 452,800, filed June 14, 2006, to provide a dual receive diversity operation in a second dual receive path. Yes; And another RF component of the receiving module 20, which is also included in the RF frontend module described in pending US patent application Ser. No. 11 / 452,800, filed June 14, 2006, to provide dual receive diversity operation. It will be understood that the examples are included.

In these applications where a limited area on the motherboard is a factor, the present invention extends below the copper strip 47 and includes a portion of the printed circuit board 22 that includes and defines an unused / unconnected transmitter of the module 20. It will be appreciated that the module 20 includes embodiments that are manufactured so as not to include them. In such an embodiment, the lower substrate edge 42 will be positioned adjacent the strip 47.

Claims (12)

In an RF module that is directly surface-mounted to the front end of the picocell (microco) or microcell motherboard, Cellular signals are provided between the antenna of the picocell or microcell at one end and each output pad on the motherboard of the picocell or microcell at the other end with a plurality of individual electrical components mounted on the surface. An RF module comprising a printed circuit board to be received. The RF module of claim 1 comprising at least a duplexer, a receive band pass filter and a receive low pass filter all surface mounted directly on the surface of the printed circuit board of the module. The RF module of claim 2 further comprising a low-noise amplifier directly surface mounted to the surface of the printed circuit board of the module. 4. The RF module of claim 3 wherein the duplexer, the receive low pass filter, the low noise amplifier and the receive band pass filter define a receive path for RF signals. 5. The RF module of claim 4 further comprising an attenuator pad in the receive path between the receive low pass filter and the low noise amplifier. 5. The RF module of claim 4 further comprising a lid covering at least the duplexer, the low noise amplifier and the receive band pass filter. An RF module that is surface mounted directly in front of a motherboard of a picocellular or microcellular base station and receives RF signals, An RF module comprising a printed circuit board that mounts at least individual electrical components on a surface, such as a duplexer, a receive low pass filter, a low noise amplifier, and a receive band pass filter. 8. The RF module of claim 7, wherein the RF signals pass through the duplexer, the receive low pass filter, the low noise amplifier, and the receive band pass filter in succession. 8. The RF module of claim 7, wherein the duplexer, the receive band pass filter, the receive low pass filter, and the low noise amplifier are all located under a cover attached to a surface of the printed circuit board. 8. The printed circuit board of claim 7, wherein the printed circuit board includes a bottom surface, the bottom surface having a plurality of electrically conductive pads formed thereon, wherein the printed circuit board is formed on a motherboard of the picocell. RF module for direct surface mount. An RF module that is directly surface-mounted on the front end of a picocell motherboard, A substrate comprising an upper surface and a lower surface, the upper surface defining a plurality of electrically connected connection pads, circuit lines and pins, the lower surface being connected to the upper surface of the motherboard of the picocell; Defines a plurality of electrically conductive connection pads for direct mounting of the module-, An RF on the substrate that defines a receive path for the RF signals and includes at least a section on the substrate that directly surface mounts an individual electrical component such as a duplexer, a receive low pass filter, a low noise amplifier, and a receive band pass filter on the top surface. module. 12. The RF module of claim 11 further comprising a cover attached to an upper surface of the substrate and covering at least the duplexer, the receive band pass filter, the receive low pass filter, and the low noise amplifier.

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