KR20090026616A - Method of fabricating for wafer level chip scale package - Google Patents

Abstract

A method of fabricating for wafer level chip scale package is provided to realize a simple manufacturing and reduce a cost by attaching a wring pattern through the adhesive tape on the wafer. A method of fabricating for wafer level chip scale package is comprised of the steps: forming a bump on the bonding pad of the semiconductor chip(110); Attaching a tape and connecting on one-side end of the wiring to the bump; Adhering the adhesive tape on metallic film(102) upper side and lower side and etching mask; forming the wiring by etching the tape for the etching mask and metallic film lower-part; removing the tape for the etching mask.

Description

METHODS OF FABRICATING FOR WAFER LEVEL CHIP SCALE PACKAGE}

The present invention relates to a method for manufacturing a wafer level chip scale package, and more particularly, to a method for manufacturing a wafer level chip scale package constructed by using an adhesive tape having a wiring pattern.

The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the key technologies that enables these product design goals is package assembly technology.

This package assembly technique is a technique for securing the operation reliability of the semiconductor chip by protecting the semiconductor chip on which the integrated circuit is formed through the wafer assembly process from the external environment and easily mounted on the substrate.

Existing packages are manufactured by cutting a wafer into separate semiconductor chips and then packaging the semiconductor chips. However, the above packaging process itself includes many unit processes, that is, chip attaching, wire bonding, molding, trim / forming, etc., and thus a conventional package in which each packaging process must be performed for each semiconductor chip. The manufacturing method has a problem that the packaging time for all the semiconductor chips is too large, considering the number of semiconductor chips obtained from one wafer.

Therefore, in recent years, assembling does not proceed in the state of being separated into individual semiconductor chips, and wafer level chip scale packages manufactured through a rewiring operation in the wafer state, the formation of ball-type external connection terminals, and the operation of separating individual semiconductor chips ( A technology called Wafer Level Chip Scale Package has been proposed.

Meanwhile, referring to a method of manufacturing a wafer-level chip scale package, first, an insulating layer is formed on the entire upper surface of the semiconductor chip having a circuit pattern formed thereon, the bonding pad is exposed through a photo process, and a portion of the upper surface of the semiconductor chip formed of the insulating layer. A metal layer is deposited for electrical signal connection.

Next, after plating the metal layer and the borland deposited on the semiconductor chip using a photo process again, the metal layer is etched to expose the region where the solder bumps are to be formed, and the bonding pads and the region where the solder bumps are to be formed. The redistribution layer is formed so that the liver is electrically connected.

Then, a solder mask is formed over the entire area except the region where the solder bumps are to be formed, and the solder is attached to the exposed solder bumps to mount, and sawed into each package to wafer-level packages. To prepare.

However, although not shown and described in detail, a conventional wafer level chip scale package is manufactured by performing a complex and multi-step manufacturing process as is well known in the manufacture of a package. There is a problem that the cost of the large.

In addition, there is a problem that the reliability of the package due to the limit that the thickness between the insulating layer on the semiconductor chip and the solder mask is increased.

In addition, after the reflow process in the wafer-level chip scale package, there is a problem that the reliability of the package due to the occurrence of cracks between the insulating layer and the solder mask and the semiconductor chip due to the difference in thermal expansion coefficient.

The present invention provides a method of manufacturing a wafer level chip scale package that can simplify the manufacturing process and reduce the cost of manufacturing equipment and manufacturing equipment.

In addition, the present invention provides a method of manufacturing a wafer level chip scale package that can prevent cracks between the insulating layer and the solder mark and the semiconductor chip and improve the reliability of the package.

A method of manufacturing a wafer level chip scale package according to the present invention comprises the steps of: forming a bump on the bonding pad of a semiconductor chip having a plurality of bonding pads; And attaching a tape having a plurality of wires formed on one surface of the semiconductor chip including the bumps so that one end of the wires is connected to the bumps.

The method of forming the tape on which the wiring is formed may include attaching an adhesive tape and an etching mask tape to upper and lower surfaces of the metal film, respectively; Etching the bottom surface of the etching mask tape and the metal film to form a wire; And removing the tape for the etch mask.

Removing the tape for the etching mask, the high temperature or UV (Ultra Violet) treatment is performed on the tape for the etching mask.

The high temperature treatment is performed at a temperature of 50 to 210 ° C.

The step of attaching the tape is characterized in that the thermal compression using a punch (Punch) process.

The punching process is carried out at a temperature of 250 ~ 300 ℃.

Removing the tape except the wires connected to the bump after attaching the bump to be connected; Attaching a connection terminal to the other end of the wire connected to the bump; And sawing the wafer at the semiconductor chip level.

The connecting terminal is formed of a stud bump made of copper or gold.

Accordingly, the present invention simplifies the manufacturing process of the wafer level chip scale package by forming a wafer level chip scale package by attaching only a wiring pattern on the wafer through the adhesive tape as described above, without performing a multi-step process. And thus, the cost of manufacturing equipment and manufacturing equipment can be reduced.

In addition, the present invention, by attaching only the wiring pattern without using a solder mask, the limit between the insulating layer on the semiconductor chip and the solder mask increases and after the reflow process, the insulating layer and the solder mask according to the difference in thermal expansion coefficient and The generation of cracks between the semiconductor chips can be blocked at the source, thereby preventing the reliability of the package from being lowered.

First, the technical principle of the present invention will be briefly described. In the present invention, a wafer-level chip scale package is formed by attaching a wiring pattern made of a metal including a ball land on a wafer via a tape.

In this case, a conventional method of forming a photoresist film pattern for plating, a seed metal deposition process, a plating process, and a strip process of the photoresist pattern directly on a wafer is performed. Unlike a wafer level chip scale package, a wafer level chip scale package is formed by attaching a wiring pattern on the wafer through an adhesive tape as described above to form a wafer level chip scale package without performing various steps. It is possible to simplify the manufacturing process and thus reduce the cost of manufacturing equipment and manufacturing equipment.

In addition, without using a solder mask, a wafer-level chip scale package is formed by attaching only a wiring pattern on the wafer via an adhesive tape as described above, thereby increasing the thickness and thickness between the insulating layer on the semiconductor chip and the solder mask. After the process, the generation of cracks between the insulating layer and the solder mask and the semiconductor chip due to the difference in thermal expansion coefficient can be prevented at the source, thereby preventing the reliability of the package from being lowered.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A through 1F are cross-sectional views illustrating processes for manufacturing a wafer level chip scale package according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, an adhesive tape 104 and an etching mask tape 106 are attached to upper and lower surfaces of the metal film 102 for forming a wiring pattern, respectively. Here, the metal film 102 is preferably formed of a material such as copper.

Referring to FIG. 1B, the lower surface of the etching mask tape 106 and the metal film 102 are etched to form a wiring pattern formed of the metal film 102.

Referring to FIG. 1C, the etching mask tape 106 attached to the lower surface of the metal film 102 is formed and a wiring pattern is removed.

At this time, the removal of the etching mask tape 106 is performed by a high temperature or UV (Ultra Violet) treatment, wherein the high temperature treatment is preferably performed at a temperature of about 50 ~ 210 ℃.

In this case, the adhesive force of the etching mask tape 106 attached to the lower surface of the metal film 102 is weakened by high temperature or UV treatment as described above, thereby facilitating its removal.

Referring to FIG. 1D, a passivation layer 112 having a bonding pad 116 and exposing the bonding pad 116 is formed, a solder bump 118 is formed on the bonding pad 116, and a semiconductor chip. A wafer made of 110 is attached to the bottom surface of the metal film 102 via an adhesive 114. Attachment between the wafer and the metal film 102 may be performed so that the wiring pattern of the metal film 102 and the solder bumps 118 formed on the bonding pad 116 of the semiconductor chip 110 correspond to each other.

At this time, the adhesion of the metal film 102 and the adhesive 102 formed on the wafer is performed by thermocompression using a punch process, and the punch process is performed at a high temperature of about 250 to 300 ° C. desirable.

Here, when the metal film 102 is thermally compressed and adhered to the wafer at a high temperature of about 250 ° C. or more, the exposed metal is melted while the solder bumps 118 formed on the bonding pads 116 are melted. It is possible to electrically bond with the wiring pattern of the film 102, and also to reduce the adhesion of the adhesive tape 104 attached to the upper surface of the metal film 102 to facilitate its removal.

Referring to FIG. 1E, the adhesive tape 104 attached to the metal film 102 is removed, and an external connection terminal such as solder ball is mounted on the exposed surface of the wiring pattern of the metal film 102 as soldering means ( 120) or form a stud bump made of copper or gold.

Referring to FIG. 1F, a wafer having a connection terminal 120 attached thereto is sawed at each semiconductor chip level to complete a wafer level chip scale package 100 according to an embodiment of the present invention.

Herein, the present invention simplifies the manufacturing process of the wafer level chip scale package by forming a wafer level chip scale package by attaching only a wiring pattern on the wafer through the adhesive tape as described above, and thus, the manufacturing equipment and The cost of manufacturing equipment can be reduced.

In addition, since the solder mask is not used, a crack between the insulating layer and the solder mask and the semiconductor chip due to a difference in thermal expansion coefficient after the reflow process and a limit that the thickness between the insulating layer and the solder mask on the semiconductor chip increases. Can be prevented from occurring at the source, thereby reducing the reliability of the package.

Although not shown, the wafer is sawed at the level of a semiconductor chip, and a substrate is disposed on a lower surface of the semiconductor chip, the substrate and the semiconductor chip are electrically connected by a bonding wire, and the bonding wire and the semiconductor chip are connected. Sealing one surface of the substrate including an encapsulant, it is possible to apply the present invention by attaching an external connection terminal such as a solder ball on the lower surface of the substrate.

In addition, after the wafer is sawed at the semiconductor chip level, the semiconductor chip is disposed below the face-down or face-up type, and the semiconductor chip having the same structure on the top is disposed. A stack package may be formed by attaching an adhesive, and the face-down may be attached to the semiconductor chip on a substrate having a cavity, and the bonding wire may be electrically connected through the cavity. You can rearrange them again to form a stack package.

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1A to 1F are cross-sectional views illustrating a method of manufacturing a wafer level chip scale package according to an exemplary embodiment of the present invention.

Claims (8)

Forming bumps on the bonding pads of the semiconductor chip having a plurality of bonding pads; And Attaching a tape having a plurality of wires formed on one surface of the semiconductor chip including the bumps so that one end of the wires is connected to the bumps; Method of manufacturing a wafer level chip scale package comprising a. The method of claim 1, The method of forming the tape on which the wiring is formed, Attaching an adhesive tape and an etching mask tape to upper and lower surfaces of the metal film, respectively; Etching the bottom surface of the etching mask tape and the metal film to form a wire; And Removing the tape for the etching mask; Method for producing a wafer-level chip scale package, characterized in that by performing. The method of claim 2, Removing the tape for the etching mask, The high-temperature or UV (Ultra Violet) treatment is performed on the tape for the etching mask. The method of claim 3, wherein The high temperature treatment is carried out at a temperature of 50 ~ 210 ℃ method of manufacturing a wafer level chip scale package. The method of claim 1, Attaching the tape is A method of manufacturing a wafer level chip scale package, characterized in that it is thermally compressed using a punch process. The method of claim 5, wherein The punch process is a manufacturing method of a wafer level chip scale package, characterized in that performed at a temperature of 250 ~ 300 ℃. The method of claim 1, After attaching to connect with the bump, Removing the tape except the wires connected to the bumps; Attaching a connection terminal to the other end of the wire connected to the bump; And Sawing the wafer at the semiconductor chip level; Method of manufacturing a wafer level chip scale package further comprising. The method of claim 7, wherein And the connection terminal is formed of a stud bump made of copper or gold.

Images