KR20090026033A - Method for manufacturing image sensor - Google Patents

Abstract

A manufacturing method of the image sensor is provided to fully dump the photo charge by designing the device to make the potential difference to exist between the source and the drain. A manufacturing method of the image sensor includes the step for forming a readout circuit(120) in the first substrate(100); the step for forming an electricity bonding domain(140) which is electrically connected with the readout circuit on the first substrate; the step for forming a wiring(150) on the electricity bonding domain; the step for forming image sensing parts(210) on the wiring.

Description

Method for Manufacturing Image Sensor

An embodiment relates to a method of manufacturing an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is divided into a charge coupled device (CCD) and a CMOS image sensor (CIS). do.

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. And photodiodes are formed on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and lead-out circuit are connected via a metal line.

On the other hand, according to the related art, since both the source and the drain of the both ends of the transfer transistor are doped with a high concentration N-type, there is a problem that charge sharing occurs. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur.

In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

Embodiments provide a method of manufacturing an image sensor in which charge sharing may not occur while increasing the fill factor.

In addition, the embodiment of the present invention manufactures an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by making a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a method.

In another embodiment, a method of manufacturing an image sensor includes: forming a readout circuitry on a first substrate; Forming an electrical junction region on the first substrate, the electrical junction region being electrically connected to the lead-out circuit; Forming a wire on the electrical junction region; And forming an image sensing device on the wiring.

In addition, a method of manufacturing an image sensor according to an embodiment may include forming a readout circuitry including a first transistor and a second transistor on a first substrate; Forming an electrical junction region on the first substrate between the first transistor and the second transistor, the electrical junction region being electrically connected to the readout circuit; And forming a wire on the electrical junction region; And forming an image sensing device on the wiring.

According to the method of manufacturing the image sensor according to the embodiment, the device is designed such that there is a voltage difference between the source and the drain across the transistor Tx to allow full dumping of the photo charge. Can be.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. It can prevent.

Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

The present invention is not limited to the CMOS image sensor, and may be applied to an image sensor requiring a photodiode.

(First embodiment)

1 is a cross-sectional view of an image sensor according to a first embodiment.

The image sensor according to the first embodiment includes a readout circuitry 120 formed on the first substrate 100; An electrical junction region 140 formed on the first substrate 100 to be electrically connected to the lead-out circuit 120; And a wiring 150 formed on the electrical junction region 140. And an image sensing unit 210 formed on the wiring 150.

The image sensing unit 210 may be a photodiode, but is not limited thereto and may be a photogate, a combination of a photodiode and a photogate, and the like. On the other hand, the embodiment is an example in which the photodiode is formed in the crystalline semiconductor layer, but is not limited thereto, and includes the one formed in the amorphous semiconductor layer.

Unexplained reference numerals among the reference numerals of FIG. 1 will be described in the following manufacturing method.

Hereinafter, a manufacturing method of an image sensor according to an exemplary embodiment will be described with reference to FIGS. 2 to 7.

First, as shown in FIG. 2, the first substrate 100 having the wiring 150 and the readout circuit 120 is prepared. For example, the isolation layer 110 is formed on the second conductive first substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. In addition, according to the embodiment, the noise can be improved by adding a noise removing circuit (not shown).

The forming of the lead-out circuit 120 on the first substrate 100 may include forming an electrical junction region 140 on the first substrate 100 and the wiring on the electrical junction region 140. And forming a first conductivity type connection region 147 connected to 150.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. The first substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transistor Tx to enable full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, in the embodiment, as shown in FIG. 2, the voltage difference between the source / drain across the transistor Tx 121 is formed by forming the electrical junction region 140 on the first substrate 100 on which the readout circuit 120 is formed. This allows full dumping of the photocharge.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 210 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on to be converted into a voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the FD (131) node becomes Vdd-Rx Vth, the charge sharing is performed due to the potential difference between both ends of the Tx (131). Electrons generated from the photodiode 210 above the chip may be fully dumped to the FD 131 node.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub, which is the first substrate 100, is P0 / N- / during the 4-Tr APS Reset operation. In Pwell Junction, + voltage is applied to N- (143) and Ground voltage is applied to P0 (145) and Pwell 141. Therefore, P0 / N- / Pwell Double Junction is Pinch-Off as in BJT structure. Will occur. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, thereby preventing the charge sharing phenomenon during the Tx On / Off operation.

Therefore, unlike the case where the photodiode is simply connected by N + junction as in the prior art, the embodiment can avoid problems such as degradation of saturation and degradation of sensitivity.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit to make a smooth movement path of the photo charge, thereby minimizing the dark current source and saturation ( Saturation) can be prevented and degradation of sensitivity.

To this end, the first embodiment may form a first conductivity type connection region 147 for ohmic contact on the surface of the P0 / N- / P- cushion 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, the width of the first conductive connection region 147 may be minimized in order to minimize the first conductive connection region 147 from becoming a leakage source. To this end, the embodiment may proceed with a plug implant after etching the first metal contact 151a, but is not limited thereto. For example, as another example, an ion implantation pattern (not shown) may be formed and the first conductive connection region 147 may be formed using the ion implantation mask as an ion implantation mask.

That is, as in the first embodiment, the reason for locally N + doping only to the contact forming part is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

Next, the interlayer insulating layer 160 may be formed on the first substrate 100, and the wiring 150 may be formed. The wiring 150 may include a first metal contact 151a, a first metal 151, a second metal 152, and a third metal 153, but is not limited thereto.

Next, as shown in FIG. 3, a crystalline semiconductor layer 210a is formed on the second substrate 200. In the first embodiment, the photodiode 210 is formed on a crystalline semiconductor layer. Thus, according to the first embodiment, the image sensing unit adopts a three-dimensional image sensor positioned above the readout circuit to increase the fill factor while forming the image sensing unit in the crystalline semiconductor layer to prevent defects in the image sensing unit. Can be.

For example, the crystalline semiconductor layer 210a is formed on the second substrate 200 by epitaxial. Thereafter, hydrogen ions are implanted at the boundary between the second substrate 200 and the crystalline semiconductor layer 210a to form the hydrogen ion implanted layer 207a. The implantation of hydrogen ions may be performed after ion implantation to form the photodiode 210.

Next, as shown in FIG. 4, the photodiode 210 is formed by ion implantation into the crystalline semiconductor layer 210a. For example, a second conductivity type conductive layer 216 is formed under the crystalline semiconductor layer 210a. For example, a high concentration P-type conductive layer 216 may be formed by implanting ions into the entire surface of the second substrate 200 with a blanket under the crystalline semiconductor layer 210a without a mask. For example, the second conductivity type conductive layer 216 may be formed with a junction depth within about 0.5 μm.

Thereafter, a first conductivity type conductive layer 214 is formed on the second conductivity type conductive layer 216. For example, the low concentration N-type conductive layer 214 may be formed by implanting ions onto the entire surface of the second substrate 200 without a mask on the second conductive conductive layer 216. For example, the low concentration first conductivity type conductive layer 214 may be formed with a junction depth of about 1.0-2.0 μm.

According to the embodiment, the thickness of the first conductivity type conductive layer 214 is formed to be thicker than the thickness of the second conductivity type conductive layer 216, thereby increasing the charge storage capacity. That is, by forming the N-layer 214 thicker to expand the area, it is possible to improve the capacity (capacity) that may contain the optoelectronic.

Thereafter, the first embodiment may further include forming a high concentration of the first conductivity type conductive layer 212 on the first conductivity type conductive layer 214. For example, the high concentration first conductive type layer 212 may be formed with a junction depth of about 0.05 to 0.2 μm. For example, an ion implantation may be performed on the entire surface of the second substrate 200 without a mask on the first conductive type conductive layer 214 to form a high concentration N + type conductive layer 212, thereby contributing to ohmic contact.

Next, as illustrated in FIG. 5, the first substrate 100 and the second substrate 200 are bonded to each other so that the photodiode 210 and the wiring 150 contact each other. In this case, the bonding may be performed by increasing the surface energy of the surface bonded by activation by plasma before bonding the first substrate 100 and the second substrate 200. Meanwhile, in order to improve the bonding force, bonding may be performed through an insulating layer, a metal layer, or the like on the bonding interface.

Thereafter, as illustrated in FIG. 6, the hydrogen ion injection layer 207a may be changed into a hydrogen gas layer (not shown) through heat treatment on the second substrate 200. Thereafter, the photodiode 210 may be exposed by leaving a photodiode 210 based on the hydrogen gas layer and removing a portion of the second substrate 200 using a blade or the like.

Thereafter, etching may be performed to separate the photodiode 210 for each pixel. Thereafter, the etched portion may be filled with an inter-pixel insulating layer (not shown).

Next, as shown in FIG. 7, a process such as an upper electrode 240 and a color filter (not shown) may be performed.

(2nd Example)

8 is a cross-sectional view of the image sensor according to the second embodiment, which is a detailed view of the first substrate on which the wiring 150 is formed.

The image sensor according to the second embodiment includes a readout circuitry 120 formed on the first substrate 100; An electrical junction region 140 formed on the first substrate 100 to be electrically connected to the lead-out circuit 120; And a wiring 150 formed on the electrical bonding region 140. And an image sensing unit 210 formed on the wiring 150.

The second embodiment can employ the technical features of the first embodiment.

For example, according to the second embodiment, a device may be designed such that there is a voltage difference between a source / drain across the transistor Tx, thereby enabling full dumping of photo charge. have.

In addition, according to the embodiment, a charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path for the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. It can prevent.

Meanwhile, unlike the first embodiment, the second embodiment is an example in which the first conductive connection region 148 is formed on one side of the electrical bonding region 140.

According to an embodiment, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, in which the process of forming the N + connection region 148 and the M1C contact 151a may be performed. It can be a Leakage Source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. The crystal defects generated during the contact forming process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-field by the N + / P0 junction 148/145 is added, which may also be a leakage source. .

Accordingly, in the second embodiment, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with a P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is provided. present.

According to the second embodiment, the E-Field of the Si surface does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

(Third Embodiment)

9 is a cross-sectional view of the image sensor according to the third embodiment, which is a detailed view of the first substrate on which the wiring 150 is formed.

The image sensor according to the third embodiment includes a readout circuitry 120 formed on the first substrate 100 including a first transistor 121a and a second transistor 121b; An electrical junction region 140 electrically connected to the readout circuit 120 to the first substrate 100 and formed between the first transistor 121a and the second transistor 121b; And a wiring 150 formed on the electrical bonding region 140. And an image sensing unit 210 formed on the wiring 150.

The third embodiment can employ the technical features of the first embodiment.

For example, according to the third embodiment, the device can be designed such that there is a potential difference between the source and the drain across the transistor Tx, so that a full dumping of the photo charge can be performed. have.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. It can prevent.

Meanwhile, in the third embodiment, the step of forming the readout circuit 120 on the first substrate 100 will be described in more detail.

First, a first transistor 121a and a second transistor 121b are formed on the first substrate 100. For example, the first transistor 121a and the second transistor 121b may be the first transfer transistor 121 and the second transfer transistor 121b, respectively, but are not limited thereto. The first transistor 121a and the second transistor 121b may be formed simultaneously or sequentially.

Thereafter, an electrical junction region 140 is formed between the first transistor 121a and the second transistor 121b. For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto.

For example, the PN junction 140 of the embodiment may include a first conductivity type ion implantation layer 143 and a first conductivity type ion implantation layer (143) formed on a second conductivity type epi (or well) 141. 143 may include a second conductivity type ion implantation layer 145.

For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto.

Thereafter, a high concentration first conductivity type connection region 131b is formed on one side of the second transistor 121b to be connected to the wiring 150. The high concentration first conductivity type connection region 131b may serve as a second concentration diffusion region FD 2 131b as a high concentration N + ion implantation region N + junction, but is not limited thereto.

In the embodiment, the readout circuit part includes a portion for moving electrons generated from a photodiode on a chip to an N + junction 131b of a substrate on which a circuit is formed, and N +. 4Tr operation may be possible by moving electrons of the junction 131b back to the N-junction 143.

In the third embodiment, as illustrated in FIG. 9, the reason why the P0 / N− / P− junction 140 and the N + junction 131b are formed separately is as follows.

For example, if N + Doping and Contact are formed in P / N / P Junction 140 of P0 / N- / P-Epi 140, N + Layer 131b and Contact Etch damage ( Dark current is generated due to damage), so the contact forming portion N + junction (131b) is separated from the P / N / P junction (140) portion.

That is, when N + Doping and Contact Etch is performed on the surface of the P / N / P junction 140, it becomes a leakage source, so to contact N + / P-Epi Junction 131b to prevent it. ) Is formed.

During signal readout, the gates of the second transistors Tx 2 and 121b are turned on so that electrons generated in the photodiode 210 on the chip are P0 / N- / P-. Since it is moved to the first floating diffusion region (FD 1) 131a node through the epi junction 140, correlated double sampling (CDS) is possible.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a sectional view of an image sensor according to a first embodiment;

2 to 7 are process cross-sectional views of a method of manufacturing the image sensor according to the first embodiment.

8 is a sectional view of an image sensor according to a second embodiment;

9 is a sectional view of an image sensor according to a third embodiment;

Claims (17)

Forming a readout circuitry on the first substrate; Forming an electrical junction region on the first substrate, the electrical junction region being electrically connected to the lead-out circuit; Forming a wire on the electrical junction region; And Forming an image sensing device on the wiring; and manufacturing an image sensor. According to claim 1, Forming the electrical junction region is Forming a first conductivity type ion implantation region in the first substrate; And And forming a second conductivity type ion implantation region on the first conductivity type ion implantation region. According to claim 1, The lead out circuit is A method of manufacturing an image sensor, characterized in that there is a voltage difference between a source and a drain on both sides of a transistor. The method of claim 3, wherein The transistor is a transfer transistor, And an ion implantation concentration of the transistor source is lower than that of the floating diffusion region. According to claim 1, The electrical junction region is Method of manufacturing an image sensor, characterized in that the PN junction (junction). The method of claim 5, The electrical junction region is Manufacturing method of an image sensor characterized in that the PNP junction (junction) According to claim 1, And forming a first conductive connection region between the electrical junction region and the wiring. The method of claim 7, wherein The first conductivity type connection region And an electrical connection with the wirings formed on the electrical junction region. The method of claim 8, The first conductivity type connection region The method of manufacturing an image sensor, characterized in that formed on the one side of the electrical junction region is electrically connected to the wiring. According to claim 1, Forming the image detection unit Forming an image sensing unit on the wiring including a first conductive conductive layer and a second conductive conductive layer formed on the first conductive conductive layer; The thickness of the first conductivity type conductive layer is thicker than the thickness of the second conductivity type conductive layer manufacturing method of the image sensor. Forming a readout circuitry including a first transistor and a second transistor on a first substrate; Forming an electrical junction region on the first substrate between the first transistor and the second transistor, the electrical junction region being electrically connected to the readout circuit; And Forming a wire on the electrical junction region; And Forming an image sensing unit on the wiring; and manufacturing an image sensor. The method of claim 11, wherein And forming a first conductive type second connection region on one side of the second transistor to be connected to the wiring. The method of claim 11, wherein Forming the electrical junction region is Forming a first conductivity type ion implantation region in the first substrate; And And forming a second conductivity type ion implantation region on the first conductivity type ion implantation region. The method of claim 11, wherein The lead out circuit is A method of manufacturing an image sensor, characterized in that there is a voltage difference between a source and a drain on both sides of a transistor. The method of claim 14, The first transistor and the second transistor are a first transfer transistor, a second transfer transistor, The ion implantation concentration of the first transfer transistor source is lower than the ion implantation concentration of the floating diffusion region manufacturing method of the image sensor. The method of claim 11, wherein The electrical junction region is Method of manufacturing an image sensor, characterized in that the PN junction (junction). The method of claim 11, wherein Forming the image detection unit Forming an image sensing unit on the wiring including a first conductive conductive layer and a second conductive conductive layer formed on the first conductive conductive layer; The thickness of the first conductivity type conductive layer is thicker than the thickness of the second conductivity type conductive layer manufacturing method of the image sensor.

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