KR20090024945A - Startup circuit and bandgap reference voltage generator including the same - Google Patents

Abstract

A start up circuit and a band gap reference voltage generator including the same are provided to prevent the increase of a reference voltage and power consumption due to an unnecessary start up operation and to secure the reference voltage of the whole system stably by controlling a bias voltage of the reference voltage generator to a stable level. A start up circuit(100) includes a charging/discharging unit(110) and a bias output unit(150). The charging/discharging unit supplies a current of a constant level to a charging/discharging node and discharges the current corresponding to the level of the power voltage among the supplied currents. The bias output unit generates a bias voltage based on the voltage of the charging/discharging node. The current supplied to the charging/discharging node is not affected by the power voltage.

Description

STARTUP CIRCUIT AND BANDGAP REFERENCE VOLTAGE GENERATOR INCLUDING THE SAME}

The present invention relates to a bandgap reference voltage generator, and more particularly to a start-up circuit applied to the bandgap reference voltage generator.

As electronic circuit systems become more and more integrated, various circuits are integrated on one chip. Among them, analog circuits require various DC biases due to their characteristics. In general, the DC bias applied to the analog circuit has a circuit that generates a DC bias inside the chip instead of being supplied separately from the outside of the chip. There are many circuits that generate DC bias, but among them, the band gap reference voltage generator is preferred by circuit designers because of its ability to supply relatively stable bias even if the supply voltage or temperature changes. Doing.

Bias generating circuits, such as bandgap reference voltage generators, especially those using transistors, quickly enter a steady state to enable the circuit designer to perform the desired operation when the semiconductor chip or system is powered up. Be prepared to bias the analog or other circuits beforehand. However, when the power supply starts, the bias circuits do not quickly finish preparing the bias supply, or sometimes the operation of the bias circuit itself becomes opaque. In order to prevent such a problem, a so-called start up circuit is used, which allows the bias generation circuit to safely and quickly enter a steady state when power is started. However, currently used start-up circuits have a large area occupied by Bipolar Junction Transistors (BJTs) in the circuit and are sensitive to variations in the analog supply voltage (VDD). Therefore, a power-up failure often occurs while the power supply voltage VDD increases during the power-up operation. As such, if the start-up operation is not normally performed during the initial operation, a normal reference voltage cannot be generated, thereby causing a problem that the circuit cannot guarantee a stable operation.

The start-up circuit only helps the initial operation of the bandgap reference voltage generator, as the word implies, and once the circuit is in steady state, the start-up circuit should be operatively separated from the bias circuit so that it does not affect the circuit. However, if the start-up circuit is operated again even after the circuit enters the normal operation state, there is a problem that the current is consumed by the unnecessary start-up operation and the problem that the reference voltage is increased. Increasing the reference voltage will result in instability of the system.

An object of the present invention is to provide a start-up circuit of a bandgap reference voltage generator that can prevent a power-up failure caused by an increase in the power supply voltage VDD.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a start-up circuit of a bandgap reference voltage generator capable of preventing an increase in a reference voltage and an increase in current consumption due to an unnecessary startup operation.

An object of the present invention is to provide a start-up circuit of a bandgap reference voltage generator capable of stably securing the reference voltage of the entire system.

In order to achieve the above object, a start-up circuit according to the present invention includes a charge / discharge unit for providing a current of a predetermined level to a charge / discharge node and discharging a current corresponding to a level of a power supply voltage among the provided currents; And a bias output unit for generating a bias voltage based on the voltage of the charge / discharge node, wherein the current provided to the charge / discharge node is not affected by the power supply voltage.

The charging / discharging unit may include: a charging transistor configured to provide the predetermined level of current to the charging / discharging node; A voltage difference determiner configured to determine an amount of current flowing through the charging transistor; A discharge transistor for discharging a current corresponding to the power supply voltage from the charge / discharge node; And a current supply unit generating a current corresponding to the power supply voltage and copying the generated current to a discharge transistor.

In this embodiment, the voltage difference determination unit includes a plurality of transistors for generating a control voltage of a predetermined level by dropping the power supply voltage, the control voltage is provided to the control terminal of the charging transistor.

In this embodiment, the current supply unit includes a load transistor for generating a current corresponding to the power supply voltage; And a current mirror transistor configured to copy current generated from the load transistor to the discharge transistor, wherein the current mirror transistor and the discharge transistor form a current mirror.

In this embodiment, the load transistor is characterized by consisting of a single transistor.

In this embodiment, the load transistor is characterized in that the cascode form.

In this embodiment, the charge / discharge unit is characterized in that it further comprises a capacitor for controlling the timing of the current flowing through the current mirror.

In this embodiment, the charge / discharge unit further comprises a switch for activating the charge / discharge unit in response to the level of the power supply voltage.

In this embodiment, the bias output unit comprises: one or more first discharge transistors for discharging the voltage of one or more output nodes in response to the voltage of the charge / discharge node; And a second discharge transistor configured to discharge the discharge result of the first discharge transistor to a ground level.

In this embodiment, the second discharge transistor is characterized in that the first discharge transistor is suppressed from re-operation after the first discharge transistor is turned off.

According to the present invention as described above, it is possible to prevent the power-up failure caused by increasing the power supply voltage (VDD), and to adjust the bias voltage of the bandgap reference voltage generator to a stable level. As a result, the reference voltage of the entire system is stably secured.

In addition, according to the present invention as described above, since the possibility that the startup operation occurs after the circuit enters the normal state is effectively blocked, it is possible to prevent the increase of the reference voltage and the increase of current consumption due to unnecessary startup operation. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The novel start-up circuit of the present invention provides a charge / discharge unit for providing a constant level of current to a charge / discharge node and discharging a current corresponding to a level of a power supply voltage among the provided currents, and the voltage of the charge / discharge node. It includes a bias output unit for generating a bias voltage based on. The current provided to the charge / discharge node is not affected by the power supply voltage. Accordingly, the bandgap reference voltage generator including the start-up circuit of the present invention can generate a stable level reference voltage without being affected by the power supply voltage during the start-up operation.

1 is a diagram illustrating a configuration of a bandgap reference voltage generator 1000 to which a start-up circuit 100 is applied according to an exemplary embodiment of the present invention. The configuration of the bandgap reference voltage generator 1000 shown in FIG. 1 is an embodiment to which the start-up circuit 100 according to the present invention may be applied, and may be changed and modified in various forms by those skilled in the art.

Referring to FIG. 1, the bandgap reference voltage generator 1000 includes a start-up circuit 100, a differential amplifier unit 10, and a reference voltage generator 50. As will be described in detail below, the bandgap reference voltage generator 1000 shown in FIG. 1 is insensitive to changes in PVT (Process Voltage Temperature).

The differential amplifier 10 is a bias generation circuit that receives two differential inputs Va and Vb configured as differential pairs and generates a bias voltage Vbias. The differential amplifier 10 operates in a saturation region, and although not shown in the drawing, the differential amplifier 10 uses two low voltage transistors having a low threshold voltage. Va, Vb).

When the initial power is applied during the power-up operation, the power supply voltage VDD gradually increases from 0V to the target level. The start-up circuit 100 is used to safely and quickly enter the steady state when the power supply voltage VDD starts to be supplied to the differential amplifier 10. That is, the start-up circuit 100 is activated to generate the bias voltage Vbias during the period after the initial power is applied and before the circuit enters the normal state. This is called a start up operation. After the circuit enters the normal state, the start-up circuit 100 is deactivated and the bias voltage Vbias generated by the differential amplifier 10 is provided to the reference voltage generator 50. The reference voltage generator 50 may generate a reference voltage Vref having a constant level in response to the bias voltage Vbias generated by the start-up circuit 100 or the differential amplifier 10 depending on whether the circuit enters a normal state. Will occur).

The reference voltage generator 50 includes a plurality of PMOS transistors constituting a current mirror. The channel widths of the PMOS transistors have the same value Wp, and first to third resistors R1 to R3 are connected to the PMOS transistors. The voltages Va and Vb input to the differential amplifier 10 are determined using the resistance values R1-R3. Here, the values of the first and third resistors R1 and R3 are equal to each other, and the voltages of Va and Vb are adjusted to have the same value.

The gates of the PMOS transistors constituting the current mirror are commonly connected to the output node of the differential amplifier 10. Therefore, the currents I1, I2, and Iref flowing through the current mirror are all the same. Here, since I1a = I2a and I1b = I2b, the difference (ΔV _EB ) between the emitter-base voltages of the two bipolar junction transistors Q1 and Q2 is defined as shown in [Equation 1].

Here, V _EB1 and V _EB2 denote emitter-base voltages of two bipolar junction transistors Q1 and Q2, respectively, and V _T denotes a thermal voltage. V _EB1 and V _EB2 decrease as the temperature increases, while V _T increases as the temperature increases.

The current I2a flowing to the third resistor R3 has a characteristic proportional to V _T as shown in [Equation 2]. Therefore, the current I2a flowing to the third resistor R3 has a characteristic that increases with increasing temperature.

The current I2b flowing to the second resistor R2 is V _EB1 as shown in [Equation 3]. Has a property proportional to Therefore, the current I2b flowing to the second resistor R2 has a characteristic of decreasing with increasing temperature.

 Here, I2 is the sum of I2a and I2b, and I2 and Iref have the same value. Therefore, the reference current Iref is defined as shown in [Equation 4].

Iref = I2a + I2b

As can be seen from Equation 4, the reference current Iref includes a thermal voltage V _T that increases with temperature and a base-emitter voltage V _EB1 of a bipolar junction transistor that decreases with temperature. Are made by combining Therefore, the reference current Iref always has a constant value without being affected by the change in temperature.

In this case, the output reference voltage Vref is calculated as shown in [Equation 5].

 In Equation 5, it can be seen that the output reference voltage Vref is obtained by multiplying the reference current Iref by the fourth resistor R4 connected to the output node. Since the output reference voltage Vref is determined by the reference current Iref which is not affected by the change in temperature, the output reference voltage Vref also has a constant value at all times without being affected by the change in temperature. Therefore, the bandgap reference voltage generator 1000 shown in FIG. 1 can always generate a constant level of the reference voltage Vref without being affected by a change in temperature (that is, a change in PVT).

The start-up circuit 100 helps only the initial operation of the bandgap reference voltage generator 1000, and stops the operation once the bandgap reference voltage generator 1000 reaches a normal operating state so as not to affect the circuit. If the start-up circuit is operated again after the circuit enters the normal operating state, a problem arises in that the reference voltage is increased and current is consumed by the unnecessary start-up operation. In order to prevent such a problem, the start-up circuit 100 according to the present invention is a start-up circuit so that the start-up circuit 100 is not re-operated after the bandgap reference voltage generator 1000 has reached a normal operating state. The operation of the 100 is effectively suppressed. In order to prevent the failure of the startup operation, the bias voltage Vbias is not increased even when the level of the power supply voltage VDD is increased during the startup operation. That is, the bias voltage Vbias caused by the increase in the power supply voltage VDD is suppressed during the startup operation. Detailed configuration of the start-up circuit 100 according to the present invention will be described in detail below with reference to FIG.

2 is a diagram illustrating a configuration of the bandgap reference voltage generator 2000 to which the start-up circuit 200 is applied according to an exemplary embodiment of the present invention. The bandgap reference voltage generator 2000 shown in FIG. 2 is the bandgap reference voltage shown in FIG. 1 in that the current mirror included in the mood voltage generator 60 is formed as a cascode current mirror. It is different from the generator 1000, and the other circuit configurations are substantially the same. In particular, the start-up circuit 200 shown in FIG. 2 includes two bias voltages Vbiasu and Vbiasd in relation to the cascode current mirror since the bandgap reference voltage generator 2000 includes a cascode current mirror. Transistors (MN6, MP6, MP7) for processing the more was added compared to FIG. However, operations performed by the start-up circuit 200 and the bandgap reference voltage generator 2000 are basically the same as the start-up circuit 100 and the bandgap reference voltage generator 1000 shown in FIG. 1. Therefore, hereinafter, a description of blocks that perform the same function will be omitted to avoid overlapping descriptions. The configuration of the bandgap reference voltage generator 2000 shown in FIG. 2 is an embodiment to which the start-up circuit 200 according to the present invention may be applied, and may be changed and modified in various forms by those skilled in the art.

Referring to FIG. 2, the bandgap reference voltage generator 2000 includes a start-up circuit 200, a differential amplifier 20, and a reference voltage generator 60.

The reference voltage generator 60 uses the bias voltages Vbiasu and Vbiasd generated by the start-up circuit 200 or the differential amplifier 20 depending on whether the circuit enters a normal state and has a constant reference voltage. Generates (Vref). The reference voltage generator 60 is configured to generate a reference level Iref of a constant level required to generate the reference voltage Vref, and includes a cascode current mirror. The cascode current mirror may be configured to have a wide swing, and the ratio of the current mirror may be 1: 2. The current mirror may also be configured in the start-up circuit 200 to correspond to the configuration of the current mirror provided in the reference voltage generator 60. According to the current mirror configuration, the ratio of the area occupied by the bipolar junction transistor (BJT) in the circuit is reduced, and the sensitivity of the output reference voltage Vref due to the variation of the analog supply voltage VDD is reduced. Therefore, a more stable level of reference voltage Vref can be generated.

If the bias voltages Vbiasu and Vbiasd rise along the power supply voltage VDD in the bandgap reference voltage generator during power-up operation, there is a possibility of a power-up failure in which the start-up circuit does not operate normally. In order to prevent such a problem, the start-up circuit 200 according to the present invention drops the bias voltage (Vbiasu, Vbiasd) to a constant voltage, respectively, to prevent the power-up failure. In addition, by suppressing the operation of the start-up circuit 200 so that the start-up circuit 200 does not operate again after the circuit enters the normal operating state, an increase in the reference voltage and current consumption according to the unnecessary start-up operation are performed. To prevent. Detailed configuration of the start-up circuit 200 according to the present invention will be described in detail with reference to FIG.

3 is a circuit diagram of a start-up circuit 100 according to an embodiment of the present invention. 3 shows the structure of the start-up circuit 100 using a single current mirror. The start-up circuit 100 shown in FIG. 3 is an embodiment to which the present invention is applied and can be changed and modified in various forms by those skilled in the art without departing from the spirit of the present invention.

Referring to FIG. 3, the start-up circuit 100 of the present invention includes a charge / discharge unit 110 and a bias output unit 150. The charging / discharging unit 110 is activated during the start-up operation to perform an operation of charging / discharging the first node N1. The first node N1 is used as a charge / discharge node charged / discharged by the charge / discharge unit 110. The bias output unit 150 adjusts the level of the bias voltage Vbias based on the voltage of the first node N1 during the startup operation, and outputs the adjusted bias voltage Vbias. . The bias output unit 150 is turned off in response to the voltage level of the first node N1 when the system enters a normal state. As a result, the electrical connection between the start-up circuit 100 and the bandgap reference voltage generator 1000 is interrupted. As will be described in detail below, the start-up circuit 100 according to the present invention is suppressed so that the start-up operation is not performed once the system enters the normal state.

First, look at the detailed configuration of the charge / discharge unit 110 as follows.

The charge / discharge unit 110 includes a first PMOS transistor MP1 in which a current path is connected between the power supply voltage VDD and the first node N1 to charge the first node N1. The voltage difference determiner 120 and the first NMOS transistor MN1 are common to the second node N2 connected to the gate terminal of the first PMOS transistor MP1 (that is, the control terminal of the first PMOS transistor MP1). Is connected. The voltage difference determiner 120 includes second and third PMOS transistors MP2 and MP3 having a current path connected in series between the power supply voltage VDD and the second node N2. Gate terminals of the second and third PMOS transistors MP2 and MP3 are connected to drain terminals, respectively. The voltage difference determiner 120 determines a source-gate voltage difference ΔV of the first PMOS transistor MP1, and the number of series-connected transistors constituting the voltage difference determiner 120 varies. Can be changed. The voltage difference determination unit 120 maintains the source-gate voltage difference ΔV of the first PMOS transistor MP1 at a predetermined voltage. Therefore, even when the power supply voltage VDD gradually increases during the initial operation, the source-gate voltage difference ΔV of the first PMOS transistor MP1 is not affected by the change in the power supply voltage VDD. Therefore, the voltage provided from the first PMOS transistor MP1 to the first node N1 is not affected by the change in the power supply voltage VDD. This not only prevents the bias voltage Vbias from increasing with the level of the power supply voltage VDD, but also prevents current consumption due to an increase in current.

The current path of the first NMOS transistor MN1 is connected between the second node N2 and ground. The activation signal Vref_en is input to the gate terminal of the first NMOS transistor MN1. The first NMOS transistor MN1 functions as an activation switch for activating the operation of the startup circuit 100 in response to the activation signal Vref_en. The activation signal Vref_en may use a separate voltage applied from the outside or use a power supply voltage VDD. In the present invention, the case where the power supply voltage VDD is used as the activation signal Vref_en is described as an example.

The current mirror 130 including the second and third NMOS transistors MN2 and MN3 is connected to the first node N1. As will be described in detail below, the third NMOS transistor MN3 constituting the current mirror 130 serves to flow a current provided to the first node N1 by the first PMOS transistor MP1 toward the ground. In other words, the voltage of the first node is determined according to the amount of current flowing through the third NMOS transistor MN3. The current mirror 130 is connected to the capacitor 140 through the third node N3. The capacitor 140 adjusts the timing at which the current radiated by the current mirror 130 flows. The fourth PMOS transistor MP4 is connected to the third node N3. The source terminal of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and the drain terminal is connected to the third node N3. The gate terminal of the fourth PMOS transistor MP4 is connected to the fifth node N5, which is an output node. The fourth PMOS transistor MP4 is a load transistor connected to the power supply voltage VDD and provides a current corresponding to the power supply voltage VDD to the third node N3.

Subsequently, a detailed configuration of the bias output unit 150 will be described.

The bias output unit 150 includes a fourth NMOS transistor MN4 having a gate terminal connected to the first node N1 and a drain terminal connected to the output node N5. The fourth node N4 is connected to the source terminal of the fourth NMOS transistor MN4. The gate terminal and the drain terminal of the fifth NMOS transistor MN5 are connected to the fourth node N4 in common. The source terminal of the fifth NMOS transistor MN5 is connected to ground. The current flowing through the fourth NMOS transistor MN4 is adjusted according to the voltage level of the first node N1. When the voltage of the first node N1 falls below a certain level, the fourth NMOS transistor MN4 is turned off. do.

The operation of the start-up circuit 1000 according to the present invention is as follows.

When the activation signal Vref_en and the power supply voltage VDD are applied during the initial operation, the first NMOS transistor MN1 is turned on in response to the activation signal Vref_en, and the second and third PMOS transistors MP2, MP3) is turned on. As a result, the voltage of the second node N2 (that is, the voltage applied to the gate of the first PMOS transistor MP1) has a predetermined level. At this time, the voltage applied to the gate of the first PMOS transistor MP1 has a level of VDD-ΔV, and ΔV is a source-gate voltage difference of the first PMOS transistor MP1, and the magnitude of ΔV is a voltage difference. Determined by the decision unit 120.

Meanwhile, while the second to fourth NMOS transistors MN2, MN3 and MN4 and the fourth and fifth PMOS transistors MP4 and MP5 are turned off, the first PMOS transistor MP1 is connected to the second node N2. Turns on in response to voltage. At this time, since the third NMOS transistor MN3 is in an off state, charges are accumulated by the current flowing into the first node N1. As a result, the voltage of the first node N1 increases. When the voltage of the first node N1 increases, the fourth NMOS transistor MN4 of the bias output unit 150 is turned on, and the charge of the fifth node N5 passes to the ground via the fourth node N4. Get out. That is, when the current flows to the ground through the fifth node N5 and the fourth node N4, the voltage of the fifth node N5 drops, and the fourth receiving the voltage of the fifth node N5 as the gate terminal. And a voltage difference between the source and gate of the fifth PMOS transistors MP4 and MP5 is generated, and the transistors MP4 and MP5 are turned on. As a result, the second and third NMOS transistors MN2 and MN3 constituting the current mirror 130 are turned on.

The current flowing through the fourth PMOS transistor MP4 flows to the ground through the second NMOS transistor MN2, and the current flowing through the second NMOS transistor MN2 is radiated to the third NMOS transistor MN3. In this case, since the second and third NMOS transistors MN2 and MN3 form the current mirror 130, the current flowing through the second NMOS transistor MN2 is equal to the current flowing through the third NMOS transistor MN3. Indicates. The current flowing through the third NMOS transistor MN3 uses the current provided from the first PMOS transistor MP1, and the voltage of the first node N1 is determined according to the amount of current flowing through the third NMOS transistor MN3. do.

Since the current provided from the first PMOS transistor MP1 is a current generated by a constant source-gate voltage difference ΔV, it has a constant value. The constant current of the first PMOS transistor MP1 not only prevents the bias voltage Vbias from increasing with the level of the power supply voltage VDD, but also prevents current consumption due to an increase in the current. On the other hand, the current flowing through the third NMOS transistor MN3 is determined by the level of the analog power supply voltage VDD provided to the fourth PMOS transistor MP4. Therefore, when the power supply voltage VDD gradually increases from 0V during the start-up operation, the current flowing to the third NMOS transistor MN3 will gradually increase. The voltage at the first node N1 determined by the current supplied from the first PMOS transistor MP1 and the current flowing through the third NMOS transistor MN3 is used to control the operation of the bias output unit 150.

When the analog power supply voltage VDD gradually increases from 0 V, the amount of current flowing through the fourth PMOS transistor MP4 increases, and eventually, the current flowing from the first node N1 to the third NMOS transistor MN3. Will increase gradually. In this case, since the current provided from the first PMOS transistor MP1 to the first node N1 is constant, the voltage of the first node N1 will gradually decrease as the level of the power supply voltage VDD increases. . The reduced voltage of the first node N1 will reduce the amount of current flowing in the fourth NMOS transistor MN4. For example, when the level of the power supply voltage VDD increases by a predetermined level or more and the voltage of the first node N1 falls below a predetermined level, the fourth NMOS transistor MN4 is turned off and the start-up circuit ( Start-up operation of 100) is stopped. Turning off the fourth NMOS transistor MN4 means that the start-up circuit 100 no longer affects the reference voltage generator 1000.

On the other hand, when the level of the power supply voltage VDD does not reach a predetermined level and the voltage of the first node N1 is kept above a predetermined level, the fourth NMOS transistor MN4 is the fifth node N5 which is an output node. Start to discharge the voltage (i.e., Vbias). At this time, the amount of current flowing through the fourth NMOS transistor MN4 (that is, the voltage of the fifth node N5 to be discharged) is controlled by the voltage of the first node N1. The voltage of the fifth node N5 determined according to the discharge operation of the fourth NMOS transistor MN4 is output as the bias voltage Vbias.

The fifth NMOS transistor MN5 serves as a diode for bringing down the voltage of the fourth node N4 to the ground level. The operating characteristic of the diode of the fifth NMOS transistor MN5 controls the fourth NMOS transistor MN4 to be turned off correctly when the level of the power supply voltage VDD increases by a predetermined level or more and no start-up operation is required. In this case, once turned off, the fourth NMOS transistor MN4 is not operated again, so that the startup circuit 100 does not perform an abnormal startup operation. Therefore, power consumption and an increase of the reference voltage due to abnormal start-up operation are prevented. In addition, the start-up circuit 100 according to the present invention generates a bias voltage Vbias, so that the current provided to the first node N1 (ie, the current provided by the first PMOS transistor MP1). Is configured to exhibit a constant value regardless of the level of the power supply voltage VDD. As a result, the bias voltage Vbias output from the startup circuit 100 of the present invention can be generated at a stable level without receiving nutrition from the increase in the power supply voltage VDD. As a result, not only the bias voltage Vbias increases with the level of the power supply voltage VDD, but also the current consumption due to the increase of the current can be prevented. Such voltage generation characteristics of the present invention will be described in detail with reference to FIGS. 5 to 8.

4 is a circuit diagram of a start-up circuit 200 according to another embodiment of the present invention. The start-up circuit 200 shown in FIG. 4 is associated with the cascode current mirror structure of the bandgap reference voltage generator (see FIG. 2) to process two bias voltages Vbiasu and Vbiasd. It is different from FIG. 3 in that MP6 and MP7) are further added. However, the operation performed in the startup circuit 200 is basically the same as the startup circuit 100 shown in FIG. 3. Therefore, in FIG. 4, the same reference numerals are added to the same functional blocks, and a description of blocks performing the same functions will be omitted below to avoid overlapping descriptions. The configuration of the start-up circuit 200 shown in FIG. 4 is an embodiment to which the present invention can be applied, and can be changed and modified in various forms by those skilled in the art.

Referring to FIG. 4, the start-up circuit 200 of the present invention includes a charge / discharge unit 210 and a bias output unit 250. The charging / discharging unit 210 is activated during the start-up operation to perform an operation of charging / discharging the first node N1. The bias output unit 250 adjusts the levels of the bias voltages Vbiasu and Vbiasd based on the voltage of the first node N1 during the startup operation, and outputs the bias voltages Vbiasu and Vbiasd of the adjusted levels. Perform the action. The bias output unit 250 is turned off in response to the voltage level of the first node N1 after the system enters a normal state. The turned-off bias output unit 250 is suppressed so that it is not operated again. As a result, the electrical connection between the start-up circuit 200 and the band gap reference voltage generator 2000 is effectively cut off, and unnecessary start-up operation is prevented.

The configuration of the charge / discharge unit 210 includes the charge / discharge unit 110 illustrated in FIG. 3 except that the sixth PMOS transistor MP6 is further connected to the current path of the fourth PMOS transistor MP4. It is virtually identical to the configuration. For example, due to the configuration of the voltage difference determination unit 120 which maintains the source-gate voltage difference ΔV of the first PMOS transistor MP1 at a predetermined voltage, and because of such a configuration, one PMOS transistor The lighting is the same that the current supplied from MP1 to the first node N1 is not affected by the change in the power supply voltage VDD. According to such a configuration, the bias voltages Vbiasd and Vbiasu output from the startup circuit 200 of the present invention can be generated at a stable level without receiving nutrition from the increase in the power supply voltage VDD. As a result, not only the bias voltages Vbiasd and Vbiasu rise in accordance with the level of the power supply voltage VDD, but also the current consumption due to the increase of the current can be prevented.

Referring to the configuration of the bias output unit 250, the gate terminal of the fourth NMOS transistor MN4 and the gate terminal of the sixth NMOS transistor MN6 are commonly connected to the first node N1. The current path of the fourth NMOS transistor MN4 is connected to the fifth node N5 and the fourth node N4 which are output nodes, and the current path of the sixth NMOS transistor MN6 is the sixth node N6 which is an output node. ) And the fourth node N4. In addition, a source terminal of the fourth NMOS transistor MN4, a source terminal of the sixth NMOS transistor MN6, and a gate terminal and a drain terminal of the fifth NMOS transistor MN5 are commonly connected to the fourth node N4. do. The source terminal of the fifth NMOS transistor MN5 is connected to ground.

When the voltage of the first node N1 increases during the power-up operation, the fourth NMOS transistor MN4 discharges the voltage of the fifth node N5 based on the voltage of the first node N1. As a result, the level of the first bias voltage Vbiasd is adjusted. The sixth NMOS transistor MN6 discharges the voltage of the sixth node N6 based on the voltage of the first node N1. As a result, the level of the first bias voltage Vbiasu is adjusted. At this time, the levels of the first and second bias voltages Vbiasd and Vbiasu are determined according to the amount of current flowing through the fourth and sixth NMOS transistors MN4 and MN6. The amount of current flowing through the fourth and sixth NMOS transistors MN4 and MN6 is determined according to the voltage of the first node N1. The fifth NMOS transistor MN5 serves as a diode for bringing down the voltages of the fourth node N4 (that is, the discharge results of the fourth and sixth NMOS transistors MN4 and MN6) to the ground level.

When the level of the power supply voltage VDD is increased by more than a predetermined level and no startup operation is required, the voltage of the first node N1 falls below a certain level. The fourth and sixth NMOS transistors MN4 and MN6 are turned off in response to the voltage of the first node N1 having a value less than a predetermined level. In this case, the fourth and sixth NMOS transistors MN4 and MN6 that are once turned off are controlled not to operate again by the fifth PMOS transistor MP5 having diode characteristics. As a result, the start-up circuit 200 does not perform the abnormal start-up operation, the problem of increase of the reference voltage due to the abnormal start-up operation is prevented and thus power consumption is prevented. Such voltage generation characteristics of the present invention will be described in detail with reference to FIGS. 5 to 8.

5 is a graph showing a result of generating a reference voltage Vref of a bandgap reference voltage generator according to a supply voltage of the start-up circuits 100 and 200 according to the present invention during the start-up operation. The start-up circuits 100 and 200 used in the simulations shown in FIG. 5 were designed using a 0.18 μm CMOS process and the measured reference voltage Vref was 732 ± 29.88 mV. The simulation was performed using spice.

5, 3, and 4, the reference voltage Vref_VDC generated from the bandgap reference voltage generator of the present invention during the start-up operation is generated constantly regardless of the level change of the supplied power supply voltage VDD. Able to know.

As described with reference to FIGS. 3 and 4, the source-gate voltage difference (ΔV) that is constantly generated during the start-up operation may have a bias voltage Vbias or Vbiasd or Vbiasu depending on the level of the power supply voltage VDD. Prevent rising problems. Low-level bias voltages (Vbias or Vbiasd, Vbiasu) make bias circuits, such as bandgap reference generators, fully operational.

Therefore, the bandgap reference voltage generator having the start-up circuits 100 and 200 of the present invention as described above can generate the reference voltage Vref_VDC of a constant level which is not affected by the level change of the power supply voltage VDD. Will be. The generation of a stable reference voltage Vref can ensure stable operation of the system.

6 is a graph showing the operating characteristics of the conventional start-up circuit during the start-up operation, Figure 7 is a graph showing the operating characteristics of the start-up circuit 200 of the present invention shown in Figure 4 during the start-up operation.

FIG. 7 illustrates a bias voltage generated by using a source-gate voltage difference ΔV that is constantly generated regardless of the level change of the power supply voltage VDD in the start-up circuit 200 of FIG. 4. Vbiasd and Vbiasu and reference voltage Vref waveforms generated using the bias voltages Vbiasd and Vbiasu are illustrated. The operating characteristics of the start-up circuit 200 shown in FIG. 7 differ only in that the bias voltages are two, and are the same as the operation characteristics of the start-up circuit 100 of the present invention shown in FIG. 3. Meanwhile, FIG. 6 includes the voltage difference determination unit 120 of the present invention when the source-gate voltage difference ΔV is affected by the level change of the power supply voltage VDD. The operating characteristics of a conventional start-up circuit that is not shown are shown.

6 and 7, the voltage V _n1 (see FIG. 7) of the first node N1 generated in the start-up circuit according to the present invention is a first node (generated in a conventional start-up circuit). It can be seen that it has a voltage level lower than the voltage V _n1 (see FIG. 6) of N1), and the voltage level is generated more stably than in the related art. The voltage V _n1 characteristic of the first node N1 having a stable and low level allows the bias voltage to be generated at a stable level regardless of the change in the power supply voltage VDD.

The voltage V _n1 characteristic of the first node N1 of the start-up circuits 100 and 200 of the present invention is due to the configuration of the voltage difference determining unit 120 shown in FIGS. 3 and 4. The voltage difference determiner 120 has a configuration such that the current provided from the first PMOS transistor MP1 connected to the first node N1 is constant regardless of the change in the power supply voltage VDD. Due to this configuration, the bias voltage generated in the start-up circuits 100 and 200 of the present invention has a more stable level than the bias voltage generated in the conventional start-up circuit. The stable bias voltage generation characteristic makes it possible to generate a stable level of reference voltage.

8 is a view showing a change in the current consumed in the start-up circuit (100, 200) and the current consumed in the conventional start-up circuit according to the present invention. Here, in the conventional start-up circuit, as shown in FIG. 6, when the source-gate voltage difference ΔV is affected by the level change of the power supply voltage VDD, that is, the voltage difference of the present invention shown in FIGS. 3 and 4. Means a conventional start-up circuit that does not have a determination unit 120.

Referring to FIG. 8, it can be seen that the start-up circuits 100 and 200 of the present invention have a significantly smaller amount of current consumed compared to a conventional start-up circuit when the simulation is performed under the same conditions. In particular, the start-up circuits 100 and 200 according to the present invention generate a low level bias voltage regardless of the change in the power supply voltage VDD, so that current consumption due to the increase in the power supply voltage VDD does not increase. do. In addition, since the start-up circuits 100 and 200 are suppressed to no longer operate after the system enters the normal state, the increase of the reference voltage and the current consumption due to unnecessary start-up operation do not occur.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a diagram illustrating a configuration of a bandgap reference voltage generator to which a start-up circuit according to an exemplary embodiment of the present invention is applied.

2 is a diagram illustrating a configuration of a bandgap reference voltage generator to which a start-up circuit according to an exemplary embodiment of the present invention is applied.

3 is a circuit diagram of a start-up circuit according to an embodiment of the present invention.

4 is a circuit diagram of a start-up circuit according to another embodiment of the present invention.

5 is a graph showing a result of generating a reference voltage Vref of a bandgap reference voltage generator according to a supply voltage of a start-up circuit according to the present invention during a start-up operation.

6 is a graph showing the operating characteristics of a conventional start-up circuit in the start-up operation.

7 is a graph showing an operating characteristic of the start-up circuit of the present invention shown in FIG. 4 during the start-up operation.

8 is a view showing a change in the current consumed in the start-up circuit according to the present invention, and the current consumed in the conventional start-up circuit.

* Description of the symbols for the main parts of the drawings *

100, 200: Start-up circuit 110, 210: Charge / discharge part

120: voltage difference determination unit 130: current mirror

150, 250: bias output unit 1000, 2000: bandgap reference voltage generator

Claims (11)

A charge / discharge unit configured to provide a current of a predetermined level to the charge / discharge node and discharge a current corresponding to a level of a power supply voltage among the provided currents; And It includes a bias output unit for generating a bias voltage based on the voltage of the charge / discharge node, The current supplied to the charge / discharge node is not affected by the power supply voltage. The method of claim 1, The charge / discharge unit, A charging transistor providing the constant level of current to the charge / discharge node; A voltage difference determiner configured to determine an amount of current flowing through the charging transistor; A discharge transistor for discharging a current corresponding to the power supply voltage from the charge / discharge node; And And a current supply unit generating a current corresponding to the power supply voltage and copying the generated current to a discharge transistor. The method of claim 2, The voltage difference determination unit includes a plurality of transistors for generating a predetermined level of control voltage by dropping the power supply voltage. The control voltage is provided to a control terminal of the charging transistor. The method of claim 2, The current supply unit, A load transistor for generating a current corresponding to the power supply voltage; And And a current mirror transistor for copying current generated from the load transistor to the discharge transistor, wherein the current mirror transistor and the discharge transistor form a current mirror. The method of claim 4, wherein The load transistor comprises a single transistor. The method of claim 4, wherein The load transistor is a start-up circuit, characterized in that configured in the form of a cascode. The method of claim 4, wherein The charge / discharge unit further comprises a capacitor for adjusting the timing of the current flowing through the current mirror. The method of claim 1, The charge / discharge unit further includes a switch for activating the charge / discharge unit in response to the level of the power supply voltage. The method of claim 1, The bias output unit, One or more first discharge transistors for discharging a voltage of one or more output nodes in response to the voltage of the charge / discharge node; And And a second discharge transistor for discharging the discharge result of the first discharge transistor to a ground level. The method of claim 9, And said second discharge transistor suppresses reactivation of said first discharge transistor after said first discharge transistor is turned off. A start-up circuit for generating a bias voltage in the start-up operation; A bias generator which generates the bias voltage in response to a differential input during normal operation; And A reference voltage generator configured to generate a reference voltage in response to the bias voltage generated from any one of the differential amplifier and the start-up circuit, And said start-up circuit comprises the one as claimed in claim 1.

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