KR20090024528A - Thin film transistor using nano structure and method for manufacturing the same - Google Patents

Abstract

A thin film transistor using the nanostructures and a method of manufacture thereof are provided to fill up the air gap between the nanostructures and to reduce the contact resistance of electrode. The source and drain electrodes(110,120) are formed in upper part the substrate(100). The channel(210) including nanostructures is formed between the source and drain electrode. The contact resistance reduction layer(251) surrounds the channel including the nanostructures and is formed in the upper part of substrate. The gate insulating layer(150) surrounds the source electrode, and the drain electrode and contact resistance reduction layer and is formed in the upper par of substrate. The gate electrode(170) is formed in the upper part of the gate insulating layer.

Description

 Thin film transistor using nano structure and manufacturing method thereof {Thin film transistor using nano structure and method for manufacturing the same}

The present invention relates to a thin film transistor using a nanostructure and a method for manufacturing the same that can reduce the contact resistance of the electrode to drive the device stably.

Recently, as satellite and digital broadcasting are promoted in earnest, demand and interest for a large-screen display having high resolution have increased, and expectations and roles for a flat panel display are very important.

At the same time, the demand for high brightness and high definition image information has become stronger, and research and investment on large screen liquid crystal displays and plasma displays have been actively conducted.

In particular, with the growing interest in organic light emitting displays, which are considered to be ideal displays, research and investment in AMOLED (Active Matrix OLED) for realizing large screens have been actively conducted.

As the display price competition intensifies with the development of these technologies, the demand for a printing process for producing a low-cost, large-area display is increasing.

Ultimately, the printing process, which pursues the "roll-to-roll" process, has recently been increasingly being introduced into the existing flat panel display manufacturing process centering on inkjet and contact printing methods.

In addition, with the development of nanomaterials, interest in the implementation of electronic devices using nanomaterials is increasing, and research and development on fabrication of printing devices using nanomaterial dispersion inks are being actively conducted.

In particular, in order to implement an active matrix display, securing a process technology for an active backplane in addition to a display mode is an important factor.

At present, there are many limitations in applying the printing processor, but in particular, there are many limitations in the printing method for high-resolution patterning.

This is expected to be improved through the complementary development of materials and equipment.

In addition, when the TFT is implemented as a print, research and development has been conducted based on the organic material mainly in solution until now, but recently, research based on the inorganic material has been conducted due to the problem of the reliability of the organic material.

In particular, in the case of the active material, all layers such as dispersion ink of nanowire and nano powder materials such as Si, ZnO and GaAs, which are conventional semiconductor materials, inorganic insulating film formation using a liquid precursor, and metal wiring formation using a metal nano ink are printed. Research is underway to implement this.

However, since the contact surface is small and the roughness at the interface compared with the conventional thin film device, it is necessary to properly adjust the interface.

The present invention is to solve the problem that the contact characteristics of the printed interface is reduced.

According to a first preferred embodiment of the present invention,

A substrate;

Source and drain electrodes formed on the substrate;

A channel including a nanostructure formed between the source and drain electrodes;

A contact resistance reduction layer surrounding the channel including the nanostructure and formed on the substrate;

A gate insulating layer surrounding the source electrode, the drain electrode, and the contact resistance reduction layer and formed on the substrate;

A thin film transistor using a nanostructure composed of a gate electrode formed on the gate insulating layer is provided.

According to a second preferred embodiment of the present invention,

A substrate;

A gate insulating film formed on the substrate;

A channel including a nanostructure formed on the gate insulating layer;

A contact resistance reduction layer surrounding a portion of the channel including the nanostructure and formed on the gate insulating layer;

A thin film transistor using nanostructures each connected to the contact resistance reduction layer and formed of a source and a drain electrode formed on the gate insulating layer is provided.

According to a third preferred embodiment of the present invention,

Forming a source and a drain electrode over the substrate;

Forming a channel including a nanostructure between the source and drain electrodes;

Applying a liquid precursor having the same composition as the nanostructures to the entire surface of the substrate and curing the liquid precursor;

Patterning the cured liquid precursor to form a contact resistance reduction layer surrounding the channel including the nanostructures;

Surrounding the source electrode, the drain electrode, and the contact resistance reducing layer, forming a gate insulating layer on the substrate;

Provided is a method of manufacturing a thin film transistor using a nanostructure configured to form a gate electrode on the gate insulating layer.

According to a fourth preferred embodiment of the present invention,

Forming a gate over the substrate;

Surrounding the gate and forming a gate insulating film on the substrate;

Forming a channel including a nanostructure on the gate insulating layer;

Applying a liquid precursor having the same composition as the nanostructures on the gate insulating film, and curing the liquid precursor;

Patterning the cured liquid precursor to form a contact resistance reduction layer surrounding the channel including the nanostructures;

A method of manufacturing a thin film transistor using a nanostructure is provided to surround a portion of the contact resistance reduction layer and to form a source and a drain electrode on the gate insulating layer.

According to the present invention, since the thin film transistor using the nanostructures surrounds the channel including the contact resistance reducing layer or the nanostructure, the gaps between the nanostructures can be filled, thereby reducing the contact resistance of the electrode, thereby stably driving the device. It can be, and there is an effect that can improve the uniformity of the device.

In addition, the present invention has the effect of realizing a thin film transistor having excellent performance by a dual printing method such as a primary printing process for forming a channel containing a nanostructure and a secondary printing process for forming a contact resistance reduction layer. have.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic cross-sectional view of a thin film transistor using a nanostructure according to a first embodiment of the present invention, including a substrate 100; Source and drain electrodes 110 and 120 formed on the substrate 100; A channel 210 including nanostructures formed between the source and drain electrodes 110 and 120; A contact resistance reduction layer 251 surrounding the channel 210 including the nanostructures and formed on the substrate 100; A gate insulating layer 150 formed on the substrate 100 to surround the source electrode 110, the drain electrode 120, and the contact resistance reduction layer 251; The gate electrode 170 is formed on the gate insulating layer 150.

Here, in the channel 210 including the nanostructures, the nanostructures are preferably nanopowders or nanowires.

In addition, the channel 210 including the nanostructures is preferably made of a film containing nanowires made of one of Si, ZnO and GaAs.

In addition, the channel 210 including the nanostructures may be formed of a film in which the ink in which the nanostructures are dispersed is cured.

In addition, the contact resistance reduction layer 251 is preferably formed by curing a liquid precursor having the same composition as the nanostructures.

For example, when the nanostructures are made of Si, the liquid precursor is silane cyclopenta, and when the nanostructures are made of ZnO, the liquid precursor is Znic acetate.

In addition, when the nanostructure is a nanowire made of ZnO, the content thereof is preferably 10 mg / ml to 100 mg / ml.

Therefore, the thin film transistor using the nanostructures of the present invention, since the contact resistance reducing layer surrounds the channel including the nanostructures, can fill gaps between the nanostructures, thereby reducing the contact resistance of the electrode, thereby stably providing a device. It can be driven, there is an advantage that can improve the uniformity of the device.

2A to 2F are schematic cross-sectional views illustrating a method of manufacturing a thin film transistor using a nanostructure according to a first embodiment of the present invention, and form source and drain electrodes 110 and 120 on an upper portion of the substrate 100. Figure 2a)

The source and drain electrodes 110 and 120 may be formed by photolithography or printing.

Next, an ink film 200 having nanostructures dispersed therebetween is formed between the source and drain electrodes 110 and 120 (FIG. 2B).

Here, the ink layer 200 in which the nanostructures are dispersed may be formed by coating and patterning ink in which the nanostructures are dispersed by an ink-jet printing method or a spin coating method.

In this case, the substrate 100 is preferably a glass or plastic substrate on which a barrier layer is formed.

The barrier layer is for preventing the coated ink from flowing out of the substrate.

Subsequently, the ink layer 200 in which the nanostructures are dispersed is cured to form a channel 210 including the nanostructures between the source and drain electrodes 110 and 120.

At this time, to cure the ink film 200 in which the coated nanostructures are dispersed, it is preferable to perform heat treatment for about 1 hour on a hot plate of about 200 degrees.

Next, a liquid precursor 250 having the same composition as the nanostructures is applied to the entire surface of the substrate 100, and the liquid precursor 250 is cured (FIG. 2C).

The liquid precursor 250 is preferably cured by heat treatment for about 1 hour on a hot plate of approximately 200 degrees.

Subsequently, the cured liquid precursor 250 is patterned to form a contact resistance reducing layer 251 surrounding the channel 210 including the nanostructures (FIG. 2D).

In this case, the nanostructure is dispersed in the ink film 200, the liquid precursor 250 is applied and cured, and then the cured ink film 200 and the liquid precursor 250 is patterned, nanostructure The included channel 210 and the contact resistance reduction layer 251 may be patterned at the same time. Such patterning may be variously modified within the technical scope of the present invention.

Thereafter, the source electrode 110, the drain electrode 120, and the contact resistance reduction layer 251 are wrapped to form a gate insulating layer 150 on the substrate 100 (FIG. 2E).

Subsequently, a gate electrode 170 is formed on the gate insulating layer 150 (FIG. 2F).

By performing the above-described processes of FIGS. 2A to 2F, it is possible to form a thin film transistor using the unit nanostructures according to the first embodiment of the present invention.

Therefore, the present invention can realize a thin film transistor having excellent performance by a dual printing method such as a primary printing process for forming a channel including a nanostructure and a secondary printing process for forming a contact resistance reducing layer.

In addition, the present invention has the advantage of improving the step coverage of the electrode because the nano-dispersed ink is applied along the curved surfaces of the source and drain electrodes to form a channel.

3 is a schematic cross-sectional view of a thin film transistor using a nanostructure according to a second embodiment of the present invention, including a substrate 100; A gate insulating layer 150 formed on the substrate 100; A channel 210 including a nanostructure formed on the gate insulating layer 150; A contact resistance reduction layer 251 surrounding a portion of the channel 210 including the nanostructure and formed on the gate insulating layer 150; It is connected to the contact resistance reduction layer 251, respectively, and includes source and drain electrodes 110 and 120 formed on the gate insulating layer 150.

4A to 4D are schematic cross-sectional views illustrating a method of manufacturing a thin film transistor using a nanostructure according to a second exemplary embodiment of the present invention, and form a gate 170 on an upper portion of the substrate 100 (FIG. 4A).

Thereafter, the gate 170 is surrounded and a gate insulating layer 150 is formed on the substrate 100 (FIG. 4B).

Subsequently, an ink layer 200 in which nanostructures are dispersed is formed on the gate insulating layer 150 (FIG. 4C).

Next, the ink layer 200 in which the nanostructures are dispersed is cured to form a channel 210 including the nanostructures, and then the liquid precursor 250 having the same composition as the nanostructures is formed on the gate insulating layer 150. ) Is applied on top, and the liquid precursor 250 is cured (FIG. 4D).

Subsequently, the cured liquid precursor 250 is patterned to form a contact resistance reducing layer 251 surrounding the channel 210 including the nanostructures (FIG. 4E).

Thereafter, a portion of the contact resistance reduction layer 210 is wrapped to form source and drain electrodes 110 and 120 on the gate insulating layer 150 (FIG. 4F).

5 is a photographic view of a transmission electron microscopy (TEM) of ZnO nanowires applied according to the present invention. The nanowires 211 made of ZnO have a spherical nano-shape, as shown in TEM photographs, but generally have a diameter It is 6-10 nm, and 60-100 nm in length.

The ZnO nanowires 211 can adjust the density from several mg / ml to several hundred mg / ml by controlling the amount of the dispersion solvent.

Further, by treating the surface of the ZnO nanowires with amines of alkyl chains, a stable dispersion state for a long time of about 3 months or more can be maintained.

FIG. 6 is an AFM photograph of the surface of a ZnO nanowire thin film applied according to the present invention. Looking at the surface image of a thin film formed by spin coating using ink in which ZnO nanowires are dispersed, as shown in FIG. 6, It can be seen that the ZnO nanowires are densely formed.

FIG. 7 is a TEM photograph showing a cross-sectional state in which a metal thin film is formed on a ZnO nanowire thin film applied according to the present invention, which is a thin film (ie, ZnO formed by spin coating ZnO nanowire dispersed ink) A metal thin film is formed on the top of the nanowire thin film 212 and the cross section is photographed.

Here, referring to the photograph of FIG. 7, even when the metal thin film 230 is formed on the ZnO nanowire thin film 212, the possibility of controlling the thickness and forming a dense film is shown.

In addition, regardless of the surface roughness of the interface between the ZnO nanowire thin film 212 and the metal thin film 230, it can be seen that an overall uniform film is coated.

Although the invention has been described in detail only with respect to specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the spirit of the invention, and such modifications and variations belong to the appended claims.

1 is a schematic cross-sectional view of a thin film transistor using a nanostructure according to a first embodiment of the present invention

2A to 2F are schematic cross-sectional views illustrating a method of manufacturing a thin film transistor using a nanostructure according to a first embodiment of the present invention.

3 is a schematic cross-sectional view of a thin film transistor using a nanostructure according to a second embodiment of the present invention.

4A to 4D are schematic cross-sectional views illustrating a method of manufacturing a thin film transistor using a nanostructure according to a second embodiment of the present invention.

5 is a photograph of transmission electron microscopy (TEM) of ZnO nanowires applied according to the present invention.

6 is an AFM photograph of the surface of a ZnO nanowire thin film applied according to the present invention.

7 is a TEM photograph taken a cross-sectional state in which a metal thin film is formed on the ZnO nanowire thin film applied according to the present invention

Claims (9)

A substrate; Source and drain electrodes formed on the substrate; A channel including a nanostructure formed between the source and drain electrodes; A contact resistance reduction layer surrounding the channel including the nanostructure and formed on the substrate; A gate insulating layer surrounding the source electrode, the drain electrode, and the contact resistance reduction layer and formed on the substrate; A thin film transistor using a nanostructure consisting of a gate electrode formed on the gate insulating film. A substrate; A gate insulating film formed on the substrate; A channel including a nanostructure formed on the gate insulating layer; A contact resistance reduction layer surrounding a portion of the channel including the nanostructure and formed on the gate insulating layer; A thin film transistor using nanostructures each connected to the contact resistance reducing layer and formed of a source and a drain electrode formed on the gate insulating layer. The method according to claim 1 or 2, The nanostructures, Thin film transistor using a nanostructure, characterized in that the nanopowder or nanowire. The method according to claim 1 or 2, The channel containing the nanostructures, A thin film transistor using a nanostructure, comprising a film containing a nanowire made of one of Si, ZnO and GaAs. The method according to claim 1 or 2, The channel containing the nanostructures, The thin film transistor using a nanostructure, characterized in that the ink is dispersed in the nanostructure is formed of a cured film. The method according to claim 1 or 2, The contact resistance reduction layer, A thin film transistor using a nanostructure, characterized in that the liquid precursor having the same composition as the nanostructure is cured and formed. Forming a source and a drain electrode over the substrate; Forming a channel including a nanostructure between the source and drain electrodes; Applying a liquid precursor having the same composition as the nanostructures to the entire surface of the substrate and curing the liquid precursor; Patterning the cured liquid precursor to form a contact resistance reduction layer surrounding the channel including the nanostructures; Surrounding the source electrode, the drain electrode, and the contact resistance reducing layer, forming a gate insulating layer on the substrate; A method of manufacturing a thin film transistor using a nanostructure consisting of forming a gate electrode on the gate insulating film. Forming a gate over the substrate; Surrounding the gate and forming a gate insulating film on the substrate; Forming a channel including a nanostructure on the gate insulating layer; Applying a liquid precursor having the same composition as the nanostructures on the gate insulating film, and curing the liquid precursor; Patterning the cured liquid precursor to form a contact resistance reduction layer surrounding the channel including the nanostructures; A method of manufacturing a thin film transistor using a nanostructure surrounding a portion of the contact resistance reducing layer and forming a source and a drain electrode on the gate insulating layer. The method according to claim 7 or 8, Forming a channel containing the nanostructures, Forming an ink film in which the nanostructures are dispersed; And curing the ink layer in which the nanostructures are dispersed to form a channel including the nanostructures.

Images