KR20090017856A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and manufacturing method thereof are provided to increase the contact area between the storage of the DRAM device and the embedded plug and to decrease the constant resistance. The bit line pattern comprises the bit line(410) laminated on the substrate(110), the capping line(420) and the bit line spacer(430) that surrounds the side wall of the bit line and the capping line. The protruded embedded plug(510) is positioned between the bit line patterns. The storage node(700) contacts the upper side of the bit line pattern and the protrusion of the protruded embedded plug. The bit line, the protruded embedded plug and storage node include the conductive material.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same, which increase an area of a contact region between a storage node and a buried plug.

As semiconductor devices, particularly semiconductor devices such as DRAMs, have been highly integrated and large in capacity, it is necessary to secure a process for minimizing semiconductor chip size. As a result of such high integration and large capacity, bit lines, which are one of the elements constituting the DRAM, are formed by a fine process technology. That is, the distance between the bit lines is reduced and the size of the bit lines is reduced to achieve scale down of the DRAM.

In addition, in response to high integration, DRAMs are manufactured by gradually reducing the area of active regions in a cell array region based on a capacitor over bit-line (COB) structure. However, because of the continued shrinking of design rules, DRAMs have the potential for electrical shorts between storage and bitlines in COB structures. This is because storage is electrically connected to landing pads, buried plugs, and storage nodes that are stacked one after the other so that they horizontally correspond to gates and bit lines, respectively. As the high integration of the DRAM increases, the contact resistance that connects the storage and the individual elements increases, causing a decrease in the speed and refresh characteristics of the DRAM.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems and to provide a semiconductor device which prevents electrical short and reduction of contact resistance. In particular, there is provided a semiconductor device in which the contact area between the storage and the contact plug is increased. In addition, another technical problem of the present invention is to provide a method of manufacturing the semiconductor device.

In order to achieve the above technical problem, the present invention provides a semiconductor device as follows.

According to an exemplary embodiment of the present invention, a semiconductor device includes a bit line pattern including a bit line and a capping line sequentially stacked on a substrate, and a bit line spacer surrounding sidewalls of the bit line and the capping line. A ridge buried plug separated in a pattern and having a raised portion protruding above the top of the capping line, a storage node in contact with the top of the bitline pattern and the raised portion of the raised buried plug.

Preferably, the bit line, the raised buried plug and the storage node comprise a conductive material. In addition, the insulating pattern preferably includes a silicon oxide film. The capping line and the bit line spacer may include a silicon nitride layer.

In addition, in order to achieve the above another technical problem, the present invention provides a method for manufacturing a semiconductor device as follows.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a bit line pattern including bit lines and capping lines sequentially stacked on a substrate, and bit line spacers surrounding sidewalls of the bit lines and capping lines, Forming a ridge buried plug between the bit line patterns, the ridge buried plug having a ridge separated by an insulating pattern and protruding from an upper surface of the capping line, and a storage node contacting the upper surface of the capping line and the ridge portion of the ridge buried plug; Forming a step.

The forming of the raised buried plug may include forming a buried plug separated by an insulating pattern between the bit line patterns, sequentially forming a buffer layer and an etch stop layer on the buried plug formed substrate, and the buried plug. Removing a portion of the etch stop layer formed on the upper portion of the substrate, forming the hole by anisotropically etching the buffer layer to expose the buried plug, using the etch stop layer as an etch mask, and forming the hole as an etch mask. Isotropically etching the buffer layer to form extension holes, and filling the extension holes with a conductive material.

In the forming of the hole, it is preferable that the etch stop layer is an etch mask and a portion of the buried plug is also removed. In the forming of the expansion hole, the buried plug may be isotropically etched together with the buffer layer.

The forming of the buried plug may include forming an insulating layer on the substrate having the bit line pattern, planarizing the insulating layer to expose the top surface of the bit line pattern, and forming the insulating layer on the bit line pattern and the insulating layer. Forming a photoresist pattern orthogonal to the bit line pattern, forming a buried contact hole by partially removing the insulating layer using the photoresist pattern and the bit line pattern as an etch mask, and the buried contact The method may include filling the hole with a conductive material.

Filling the conductive contact hole in the buried contact hole may include removing the photoresist pattern, forming a conductive material layer on the substrate on which the buried contact hole is formed, and etching the exposed back surface of the bit line patterns. and removing the conductive material layer by a chemical mechanical polishing process after an etchback process, a chemical mechanical polishing process, or an etchback process.

In addition, according to another embodiment of the present invention, a method of fabricating a semiconductor device may include forming a bit line pattern including bit lines and capping lines sequentially stacked on a substrate, and bit line spacers surrounding sidewalls of the bit lines and capping lines. Forming a buried plug separated by an insulating pattern between the bit line patterns, partially removing an upper portion of the capping line such that an upper surface of the capping line is lower than an upper surface of the buried plug, and the lower capping line Forming a storage node in contact with the top surface and the buried plug.

The forming of the buried plug may include forming an insulating layer on the substrate having the bit line pattern, planarizing the insulating layer to expose the top surface of the bit line pattern, and forming the insulating layer on the bit line pattern and the insulating layer. Forming a photoresist pattern orthogonal to the bit line pattern, forming a buried contact hole by partially removing the insulating layer using the photoresist pattern and the bit line pattern as an etching mask, and forming the buried contact hole The method may include filling a contact hole with a conductive material.

Filling the conductive contact hole in the buried contact hole may include forming a conductive material layer on the substrate on which the buried contact hole is formed, and an etchback process and a chemical mechanical polishing process to expose the top surface of the bit line patterns. Or removing the conductive material layer by a chemical mechanical polishing process after the etch back process.

The semiconductor device according to the present invention can increase the contact area between the storage of the DRAM device and the buried plug. In particular, the contact area is increased, so that the contact resistance can be reduced and the operation speed can be improved, whereby a high performance semiconductor device can be manufactured.

In the method of manufacturing a semiconductor device according to the present invention, a contact area between a storage of a DRAM device and a buried plug is secured, and thus contact failure can be prevented. This can reduce the defective rate of the semiconductor device, it is possible to improve the productivity.

Also, during storage manufacturing, the capping portion of the bit line pattern is not etched, thereby preventing unintended contact between the storage and the bit line pattern. Therefore, the planarization process can be sufficiently performed in the separation step of the buried plug. Through this, the defect rate of the semiconductor device due to the separation failure between the buried plug can be reduced, thereby improving productivity. Alternatively, the height of the capping portion of the bit line pattern may be reduced. Through this, it is possible to reduce the thickness of the semiconductor device and to improve performance by shortening the charge transfer path.

Hereinafter will be described in detail to enable those skilled in the art to easily understand and reproduce the present invention through the preferred embodiments. However, embodiments of the present invention illustrated in the following may be modified in many different forms within the scope of the same invention and the scope of the present invention is not limited to those shown in the following embodiments and the accompanying drawings.

1 is a schematic layout view of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 to 12 are views of a semiconductor device according to an exemplary embodiment of the present invention, cut along lines II and II-II of FIG. 1, respectively. Sectional drawing for showing the formation method.

1 and 2, the semiconductor device 100 may include a device isolation layer 130 disposed on the semiconductor substrate 110. The device isolation layer 130 generally includes silicon oxide. The active region 120 is formed on the substrate 110 by the device isolation layer 130. The gate pattern 200 is formed on the active region 120 as shown in FIG. 1. The gate pattern 200 is disposed to pass across the active zone 120. The gate pattern 200 is not limited to the method as illustrated in FIG. 1, and as long as the gate pattern 200 maintains a connection relationship between a transistor, a gate, a bit line, and a storage device, which is a basic component of a DRAM, Can be arranged in various ways.

The gate pattern 200 is formed using the gate 210 and the gate capping pattern 220 that are sequentially stacked, and gate spacers 230 are formed on both sides of the gate 210 and the gate capping pattern 220. The gate 210 may be formed of a doped polysilicon, tungsten (W), tungsten silicide, or a stacked structure thereof, and may be stacked with titanium (Ti), titanium nitride (TiN), and the like. . The gate capping pattern 220 and the gate spacer 230 may be formed using a silicon nitride layer. The pad insulating layer 250 is formed to cover all of the gate patterns 200 on the substrate 110 on which the gate patterns 200 are formed, and to fill all of the gate patterns 200. The pad insulating layer 250 may be formed using a silicon oxide film.

1 and 3, a pad hole 255 is formed through the pad insulating layer 250 to expose the substrate 110. The pad holes 255 are disposed on the active region 120 between the gate patterns 200. The landing pad 260 is filled in the pad hole 255. Landing pad 260 includes a conductive material. Landing pad 48 may be formed using laminated doped polysilicon and metal, or may be formed using alone doped polysilicon.

The bit line interlayer insulating layer 310 is formed on the pad insulating layer 250 to cover the landing pad 260. The bit line interlayer insulating layer 310 may be formed using an insulating layer having an etching rate similar to that of the pad insulating layer 250. The bit line contact hole 315 is formed in the bit line interlayer insulating film 50. The bit line contact hole 315 is disposed to expose the landing pad 260 positioned on the bit line pattern 400 in FIG. 1.

1 and 4, bit lines 410 are formed on the bit line interlayer insulating layer 310 to fill the bit line contact hole 315. The bit lines 410 are disposed to contact the selected landing pads 260 through the bit line contact holes 315. The capping line 420 having a thickness of the first height T ₁ is stacked on the bit line 410. The bit line 410 may be formed using doped polysilicon, or may be formed by laminating using at least two materials selected from doped polysilicon, titanium, titanium nitride, and tungsten. The capping line 420 may be formed using a silicon nitride film. The stacked patterns of the bit line 410 and the capping line 420 are disposed to be orthogonal to the gate patterns 200. Through this, the bit lines 410 may be disposed to intersect the active regions 120.

1 and 5, bit line spacers 430 are formed on sidewalls of the bit line 410 and the capping line 420 to complete the bit line pattern 400. The bit line spacer 430 may be formed using a silicon nitride film. An insulating layer 500 covering the bit line pattern 400 is formed on the substrate 110 on which the bit line pattern 400 is formed. The insulating layer 500 may be formed using a silicon oxide film. Referring to FIG. 6, the insulating layer 500 is partially removed through planarization so that the top surface of the bit line pattern 400 is exposed. The planarization of the insulating layer 500 may be performed using a chemical mechanical polishing (CMP) process.

1 and 7, the buried contact hole 505 is formed by removing the insulating layer 500 on the space between the gate patterns 200. The buried contact hole 505 may be formed by forming a photoresist pattern parallel to the gate pattern 200, that is, orthogonal to the bit line pattern, and then etching the insulating layer 500 using the photoresist pattern. Can be. In the II ′ plane of FIG. 1, the width of the buried contact hole 505 is not limited to the width of the space between the gate patterns 200. In order to increase the exposed area of the landing pad 260, the width of the buried contact hole 505 may be wider. It may be.

The buried contact hole 505 is filled with a buried plug 510. The buried plug 510 includes a conductive material. The buried plug 510 may be formed using, for example, doped polysilicon, or may be formed using a stacked structure of doped polysilicon and metal.

The buried plug 510 forms a conductive material layer (not shown) on the substrate 110 on which the buried contact hole 505 is formed, and then the conductive material is exposed until the top surfaces of the bit line patterns 400 are exposed. The layer (not shown) may be partially removed through a planarization process. The planarization process may be performed by an etchback process or a chemical mechanical polishing (CMP) process. Alternatively, the planarization process may be performed by an additional chemical mechanical polishing (CMP) process after the etchback process. Through this, each buried plug 510 may be electrically separated.

Although the buried plug 510 is not illustrated in the drawing, a dishing phenomenon may occur in which the buried plug 510 is partially lower than the top surfaces of the bit line patterns 400.

Referring to FIG. 8, an interlayer insulating layer 600 including a buffer layer 610 and an etch stop layer 620 is formed on the bit line pattern 400 and the buried plug 510. The buffer layer 610 may be formed using, for example, a silicon oxide film. In addition, the etch stop layer 620 may be formed using, for example, a silicon nitride layer. The etch stop layer 620 is partially removed on the buried plug 510 such that the buffer layer 610 is exposed to a narrower area of the buried plug 510.

9, the hole 605 is formed by performing an anisotropic etching process on the buffer layer 610 to expose the buried plug 510 using the etch stop layer 620 as an etch mask. In the anisotropic etching process, the buried plug 510 may be partially removed to form the hole 605.

Referring to FIG. 10, an expansion hole 607 is formed by performing an isotropic etching process on the buffer layer 610 using the etch stop layer 620 as an etch mask. In the isotropic etching process, the buried plug 510 may also be isotropically etched together to form the expansion hole 607. Although the expansion hole 607 is not shown, when dishing occurs in the buried plug 510, all of the buffer layers 610 formed in the dishing space formed at a position lower than the upper surface of the bit line pattern 400 are removed. It is preferable to form by isotropic etching.

Referring to FIG. 11, a raised buried plug 510a is formed by filling a conductive material in the expansion hole 607. As the conductive material filled in the expansion hole 607, a material having the same or similar conductivity as that used in the buried plug 510 of FIG. 7 is used. The conductive material filled in the expansion holes 607 may be formed using, for example, doped polysilicon, or may be formed using a stacked structure of doped polysilicon and metal.

The raised buried plug 510a forms a conductive material layer (not shown) on the substrate 110 on which the extension holes 607 are formed, and then the conductive material layer is exposed until the top surface of the etch stop layer 620 is exposed. (Not shown) may be partially removed through a planarization process. The planarization process may be performed by an etchback process or a chemical mechanical polishing (CMP) process. Alternatively, the planarization process may be performed by an additional chemical mechanical polishing (CMP) process after the etchback process. Through this, each raised buried plug 510a may be electrically separated.

Referring to FIG. 12, after the upper surface of the bit line pattern 400 is exposed, a portion of the interlayer insulating layer 600, that is, the etching insulating layer 620 and the buffer layer 610, and the raised buried plug 510a are removed. The storage node 700 is formed in the removed space. A mold layer (not shown) may be formed on the etch stop layer 620 and the raised buried plug 510a before the storage node 700 is formed. The mold layer (not shown) is removed together in some removal steps of the interlayer insulating layer 600 and the raised buried plug 510a to form the storage node 700, so that the storage node 700 is removed in the removed space. Can be formed.

In the cross-sectional view taken along the line II-II ', the lower surface of the storage node 700 is formed so that a portion of the upper surface of the bit line pattern 400 and the raised buried plug 510a are partially removed to cover the exposed surface. At this time, only a portion of the ridge buried plug 510a that is higher than the upper surface of the bit line pattern 400 is removed so that a portion of the ridge buried plug 510a that is higher than the upper surface of the bitline pattern 400 that is not removed is located. Make contact with the side of the storage node 700. As a result, contact between the raised buried plug 510a is made at a portion of the lower surface and the side of the storage node 700, so that the contact area between the storage node 700 and the raised buried plug 510a may be widened. In the cross-sectional view taken along the line II ′, both surfaces of the storage node 700 are in contact with the top surface of the insulating layer, so that the contact surface of the raised buried plug 510a is maximized.

FIG. 13 is a cross-sectional view illustrating a method of forming a semiconductor device in accordance with another embodiment of the present disclosure, taken along lines I-I and II-II of FIG. 1.

Referring to FIG. 13, after proceeding in the same manner to FIG. 7, the capping line (420 of FIG. 7) having the first thickness (T1 of FIG. 7) is partially removed to settle the capping line having the second thickness (T2). 420a is formed. In this case, although not illustrated, the bit line spacer 430 may also be partially removed. The settling capping line 420a may be formed by, for example, performing a wet etching process using an etchant containing sulfuric acid.

As a result, the upper surface of the settling capping line 420a, that is, the upper surface of the bit line pattern 400 may be lower than the upper surface of the buried plug 510. Subsequently, when a storage node (not shown) is formed over a portion of the upper surface of the bit line pattern 400 and the buried plug 510, the portion of the lower surface and the side of the storage node (not shown) is buried similarly to that shown in FIG. 12. The contact with the plug 510 is made, such that the contact area between the storage node (not shown) and the buried plug 510 may be widened.

1 is a schematic layout view of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 to 12 are views of a semiconductor device according to an exemplary embodiment of the present invention, cut along lines II and II-II of FIG. 1, respectively. Sectional drawing for showing the formation method.

FIG. 13 is a cross-sectional view illustrating a method of forming a semiconductor device in accordance with another embodiment of the present disclosure, taken along lines I-I and II-II of FIG. 1.

<Description of Symbols for Main Parts of Drawings>

100 semiconductor device 110 substrate

120: active region 130: device separator

200: gate pattern 210: gate

220: gate capping pattern 230: gate spacer

250: pat insulating film 255: pad hole

260: landing pad 310: bit line interlayer insulating film

315: bit line contact hole 400: bit line pattern

410: bit line 420: capping line

430: bit line spacer 500: insulating layer

505: buried contact hole 510: buried plug

600: interlayer insulating layer 605: hole

607: expansion hole 610: buffer layer

620: etching insulating film 700: storage node

Claims (13)

A bit line pattern including bit lines and capping lines sequentially stacked on a substrate, and bit line spacers surrounding sidewalls of the bit lines and capping lines; A ridge buried plug disposed between the bit line patterns, the ridge buried plug having a ridge portion separated by an insulating pattern and protruding from an upper surface of the capping line; And a storage node in contact with an upper surface of the bit line pattern and a raised portion of the raised buried plug. According to claim 1, And the bit line, the raised buried plug, and the storage node comprise a conductive material. According to claim 1, The insulating pattern comprises a silicon oxide film. According to claim 1, And the capping line and the bit line spacer include a silicon nitride layer. Forming a bit line pattern including bit lines and capping lines sequentially stacked on a substrate, and bit line spacers surrounding sidewalls of the bit lines and capping lines; Forming a ridge buried plug between the bit line patterns, the ridge buried plug having a ridge separated from an insulating pattern and protruding from an upper surface of the capping line; And Forming a storage node in contact with an upper surface of the capping line and a raised portion of the raised buried plug. The method of claim 5, Forming the raised buried plug, Forming a buried plug separated by an insulating pattern between the bit line patterns; Sequentially forming a buffer layer and an etch stop layer on the substrate on which the buried plug is formed; Removing a portion of the etch stop layer on an upper portion of the buried plug; Forming an hole by anisotropically etching the buffer layer using the etch stop layer as an etch mask to expose the buried plug; Forming an expansion hole by isotropically etching the buffer layer using the etch stop layer as an etch mask; And And filling a conductive material in the expansion hole. The method of claim 6, wherein forming the hole comprises: And partially removing the buried plug using the etch stop layer as an etch mask. The method of claim 6, wherein the forming of the expansion hole comprises: The buried plug isotropically etched together with the buffer layer. The method of claim 6, Forming the buried plug, Forming an insulating layer on the substrate having the bit line pattern; Planarizing the insulating layer to expose an upper surface of the bit line pattern; Forming a photoresist pattern orthogonal to the bit line pattern on the bit line pattern and the insulating layer; Forming a buried contact hole by partially removing the insulating layer using the photoresist pattern and the bit line pattern as an etching mask; And And filling a conductive material in the buried contact hole. The method of claim 9, Filling the conductive contact hole in the buried contact hole, Removing the photoresist pattern; Forming a conductive material layer on the substrate on which the buried contact hole is formed; And Removing a portion of the conductive material layer by an etchback process, a chemical mechanical polishing process, or a chemical mechanical polishing process after the etchback process so that the top surfaces of the bit line patterns are exposed. Method of manufacturing the device. Forming a bit line pattern including bit lines and capping lines sequentially stacked on a substrate, and bit line spacers surrounding sidewalls of the bit lines and capping lines; Forming a buried plug separated by an insulating pattern between the bit line patterns; Removing a portion of an upper portion of the capping line such that an upper surface of the capping line is lower than an upper surface of the buried plug; And Forming a storage node in contact with the lower capping line upper surface and the buried plug. The method of claim 11, wherein Forming the buried plug, Forming an insulating layer on the substrate having the bit line pattern; Planarizing the insulating layer to expose an upper surface of the bit line pattern; Forming a photoresist pattern orthogonal to the bit line pattern on the bit line pattern and the insulating layer; Forming a buried contact hole by partially removing the insulating layer using the photoresist pattern and the bit line pattern as an etching mask; And And filling a conductive material in the buried contact hole. The method of claim 12, Filling the conductive contact hole in the buried contact hole, Forming a conductive material layer on the substrate on which the buried contact hole is formed; And Removing a portion of the conductive material layer by an etchback process, a chemical mechanical polishing process, or a chemical mechanical polishing process after the etchback process so that the top surfaces of the bit line patterns are exposed. Method of manufacturing the device.

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