KR20090017104A - Circuit for entering test mode and semiconductor memory apparatus using the same - Google Patents

Circuit for entering test mode and semiconductor memory apparatus using the same Download PDF

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KR20090017104A
KR20090017104A KR1020070081590A KR20070081590A KR20090017104A KR 20090017104 A KR20090017104 A KR 20090017104A KR 1020070081590 A KR1020070081590 A KR 1020070081590A KR 20070081590 A KR20070081590 A KR 20070081590A KR 20090017104 A KR20090017104 A KR 20090017104A
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South Korea
Prior art keywords
signal
pulse
enabled
test
test mode
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KR1020070081590A
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Korean (ko)
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문형욱
이정우
최원준
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주식회사 하이닉스반도체
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Publication of KR20090017104A publication Critical patent/KR20090017104A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

The present invention provides a test pulse generator for generating a first test pulse in response to a remaining specific address combination when one of a plurality of specific addresses transitions to low, and an enabled first test when the first test pulse is enabled. And a test mode signal generator for generating a mode signal and disabling the first test mode signal when the reset signal is enabled.

Description

Circuit for Entering Test Mode and Semiconductor Memory Apparatus Using the Same}

The present invention relates to a semiconductor memory device, and more particularly, to a test mode entry circuit capable of performing a test during a wafer test and a semiconductor memory device using the same.

A general semiconductor memory device is configured to select and enter a test mode by using four externally input addresses during wafer testing.

A typical semiconductor memory device during a wafer test, for example, briefly describes an operation of selecting a test mode with the four addresses and entering a test. When one of the four addresses transitions high, the test mode is selected with the remaining three address combinations and enters the selected test mode. In addition, the reset signal is generated by the combination of the four addresses to end the selected test mode.

As a result, there are a total of eight types of test modes that a general semiconductor memory device can test during a wafer test. This is because the second to third address combinations have a total of eight types.

The semiconductor memory device is divided into a wafer level test (wafer test) and a package level test (package test) at the mass production stage to ensure the stability of the finished product.

The package test performs a test that cannot be tested in the wafer test to confirm the failure of the semiconductor memory device. Among these package tests, there is a test that repeats an active-light-precharge operation to a semiconductor memory device. When performing a package test that repeats the active-write precharge operation, the test time is long because the word lines of the semiconductor memory device must be activated one by one. In addition, as the semiconductor memory device becomes higher in capacity, the time required for the package test for repeating the active-light-precharge operation is further increased, and by using expensive test equipment for repeating the active-light-precharge operation in the package state Increasing price of memory devices.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a test mode entry circuit of a semiconductor memory device capable of increasing the types of test modes that can be performed during wafer testing.

Another object of the present invention is to provide a semiconductor memory device that can replace a package test that repeats an active-light-precharge operation during a wafer test.

According to an embodiment of the present invention, a test mode entry circuit may include a test pulse generator configured to generate a first test pulse in response to a remaining specific address combination when one of a plurality of specific addresses transitions low, And a test mode signal generator configured to generate an enabled first test mode signal when enabled, and to disable the first test mode signal when a reset signal is enabled.

The semiconductor memory device using the test mode entry circuit according to an exemplary embodiment of the present invention generates an enabled test mode signal in response to the remaining specific address combinations when one of a plurality of specific addresses transitions, and when the reset signal is enabled, A test mode entry circuit for disabling a test mode signal, a signal combination unit configured to generate an enabled refresh operation signal when the test mode signal is enabled or a refresh signal is enabled, and a refresh operation when the refresh operation signal is enabled It includes a refresh circuit for performing the.

The test mode entry circuit according to an embodiment of the present invention can reduce the type of package test by increasing the type of test mode that can be performed during wafer testing.

In addition, by reducing the type of package test, the time required for the test and the type of equipment used in the package test can be reduced, thereby reducing the cost.

The test mode entry circuit of the semiconductor memory device according to the exemplary embodiment of the present invention includes a test pulse generator 100 and a test mode signal generator 200 as illustrated in FIG. 1.

The test pulse generation unit 100 responds to the combination of the second to fourth addresses add <2>, add <3>, and add <4> when the first address add <1> transitions. A test pulse pulse1_test or a second test pulse pulse2_test is generated.

The test pulse generator 100 includes a polling pulse generator 110 and a rising pulse generator 120.

When the first address add <1> transitions low, the polling pulse generator 110 may combine a combination of the second to fourth addresses add <2>, add <3>, and add <4>. If it matches the predetermined code, the first test pulse pulse1_test is generated.

The polling pulse generator 110 includes a polling pulse generator 111 and a first output controller 112.

The polling pulse generator 111 generates a first pulse pulse1 that is enabled when the first address add <1> transitions low.

The first output controller 112 may generate the first pulse pulse1 when the combination of the second to fourth addresses add <2>, add <3>, and add <4> matches the preset code. It outputs as the said 1st test pulse pulse1_test.

When the first address add <1> transitions high, the rising pulse generator 120 may combine a combination of the second to fourth addresses add <2>, add <3>, and add <4>. If it matches the predetermined code, the second test pulse pulse2_test is generated.

The rising pulse generator 120 includes a rising pulse generator 121 and a second output controller 122.

The rising pulse generator 121 generates a second pulse pulse2 that is enabled when the first address add <1> transitions high.

The second output controller 122 may generate the second pulse pulse2 when the combination of the second address to the fourth address add <2>, add <3>, and add <4> matches the predetermined code. It outputs as said 2nd test pulse pulse2_test.

The test mode signal generator 200 generates the enabled first test mode signal Test1_mode when the first test pulse pulse1_test is enabled, and activates the second test pulse pulse2_test when the first test pulse pulse1_test is enabled. The enabled second test mode signal Test2_mode is generated, and when the reset signal reset is enabled, the first and second test mode signals Test1_mode and Test2_mode are disabled. At this time, when the power-up signal pwrup or the reset signal reset is enabled, the test mode signal generator 200 is initialized.

The test mode signal generator 200 includes a first level signal generator 210 and a second level signal generator 220.

The first level signal generator 210 enables the first test mode signal Test1_mode when the first test pulse pulse1_test is enabled and the first test when the reset signal reset is enabled. The mode signal Test1_mode is disabled and initialized.

The second level signal generator 220 enables the second test mode signal Test2_mode when the second test pulse pulse2_test is enabled and the second test when the reset signal reset is enabled. The mode signal Test2_mode is disabled and initialized.

The first and second level signal generators 210 and 220 are initialized when the power up signal pwrup is enabled.

In this case, in describing the test mode entry circuit of the semiconductor memory device according to the exemplary embodiment of the present invention, for convenience of description, four address signals input from the outside of the semiconductor memory device will be described, but the number of address signals is not limited. The reset signal is also generated by a combination of address signals.

As shown in FIG. 2, the rising pulse generator 121 includes a first delay unit delay1, first and second inverters IV1 and IV2, and a first NAND gate ND1. The first delay delay1 receives the first address add <1>. The first inverter IV1 receives the output signal of the first delayer delay1. The first NAND gate ND1 receives the first inverter IV1 and the first address add <1>. The second inverter IV2 inverts the output signal of the first NAND gate ND1 to generate the second pulse pulse2.

As illustrated in FIG. 3, the falling pulse generator 111 includes third to fifth inverters IV3, IV4, and IV5, a second delay unit delay2, and a second NAND gate ND2. The third inverter IV3 receives the first address add <1>. The second delay delay2 receives an output signal of the third inverter IV3. The fourth inverter IV4 receives the output signal of the second delayer delay2. The second NAND gate ND2 receives the output signals of the third inverter IV3 and the fourth inverter IV4. The fifth inverter IV5 inverts the output signal of the second NAND gate ND2 to generate the first pulse pulse1.

As illustrated in FIG. 4, the first output control unit 112 includes a first determination unit 112-1 and a first output unit 112-2.

The first determination unit 112-1 receives the second to fourth addresses add <2: 4> and generates a first determination signal dis1 when it matches the predetermined code.

The first output unit 112-2 outputs the first pulse pulse1 as the first test pulse pulse1_test when the first discrimination signal dis1 is enabled high, and outputs the first discrimination signal ( When dis1 is disabled low, only the low level signal is output regardless of the first pulse pulse1. The first output unit 112-2 includes a third NAND gate ND3 and a sixth inverter IV6. The third NAND gate ND3 receives the first determination signal dis1 and the first pulse pulse1. The sixth inverter IV6 inverts the output signal of the third NAND gate ND3 to generate the first test pulse pulse1_test.

As illustrated in FIG. 5, the second output control unit 122 includes a second determination unit 122-1 and a second output unit 122-2.

The second determination unit 122-1 receives the second to fourth addresses add <2: 4> and generates a second determination signal dis2 when it matches the predetermined code.

The second output unit 122-2 outputs the second pulse pulse2 as the second test pulse pulse2_test when the second discrimination signal dis2 is enabled high, and the second discrimination signal ( When dis2) is disabled low, only the low level signal is output regardless of the second pulse pulse2. The second output unit 122-2 includes a fourth NAND gate ND4 and a seventh inverter IV7. The fourth NAND gate ND4 receives the second discrimination signal dis2 and the second pulse pulse2. The seventh inverter IV7 inverts the output signal of the fourth NAND gate ND4 to generate the second test pulse pulse2_test.

As illustrated in FIG. 6, the first level signal generator 210 includes a first initializer 211, a first pulse inverter 212, and a first flip-flop 213.

The first initialization unit 211 generates an enabled first initialization signal initial1 when the power-up signal pwrup or the reset signal is enabled. In this case, the power up signal pwrup, the reset signal reset, and the first initialization signal initial1 are all low enable signals.

The first initialization unit 211 includes a fifth NAND gate ND5 and an eighth inverter IV8. The fifth NAND gate ND5 receives the power up signal pwrup and the reset signal reset. The eighth inverter IV8 inverts the output signal of the fifth NAND gate ND5 to generate the first initialization signal initial1.

When the power-up signal pwrup is enabled low, the first pulse inverting unit 212 outputs only a high level signal regardless of the first test pulse pulse1_test and the power-up signal pwrup is high. When the signal is disabled, the first test pulse pulse1_test is inverted to generate a first inverted pulse pulse1.

The first pulse inverting unit 212 includes a sixth NAND gate ND6. The sixth NAND gate ND6 receives the first test pulse pulse1_test and the power up signal pwrup to generate the first inverted pulse pulse1.

The first flip-flop 213 enables the first test mode signal Test1_mode to low when the first inverted pulse pulseb1 is enabled low, and the first initialization signal initial1 to low. When enabled, the first test mode signal Test1_mode is disabled high and initialized.

The first flip-flop 213 includes seventh and eighth NAND gates ND7 and ND8, and a ninth inverter IV9. The seventh NAND gate ND7 receives the output signals of the first initialization signal initial1 and the eighth NAND gate ND8. The eighth NAND gate ND8 receives the output signal of the seventh NAND gate ND7 and the first inverted pulse pulseb1. The ninth inverter IV9 inverts the output signal of the eighth NAND gate ND8 to generate the first test mode signal Test1_mode.

As illustrated in FIG. 7, the second level signal generator 220 includes a second initializer 221, a second pulse inverter 222, and a second flip-flop 223.

The second initialization unit 221 generates the enabled second initialization signal initialize2 when the power-up signal pwrup or the reset signal reset is enabled. In this case, the power up signal pwrup, the reset signal reset, and the second initialization signal initialize2 are all low enable signals.

The second initialization unit 221 includes a ninth NAND gate ND9 and a tenth inverter IV10. The ninth NAND gate ND9 receives the power up signal pwrup and the reset signal reset. The tenth inverter IV10 inverts the output signal of the ninth NAND gate ND9 to generate the second initialization signal initial2.

When the power up signal pwrup is enabled low, the second pulse inverting unit 222 outputs only a high level signal regardless of the second test pulse pulse2_test, and the power up signal pwrup is high. When disabled, the second test pulse pulse2_test is inverted to generate a second inverted pulse pulseb2.

The second pulse inverting unit 222 includes a tenth NAND gate ND10. The tenth NAND gate ND10 receives the second test pulse pulse2_test and the power up signal pwrup to generate the second inverted pulse pulse2.

The second flip-flop 223 enables the second test mode signal Test2_mode to high when the second inverted pulse pulseb2 is enabled low and the second initialization signal initial2 to low. When enabled, the second test mode signal Test2_mode is disabled high and initialized.

The second flip-flop 223 includes eleventh and twelfth NAND gates ND11 and ND12, and an eleventh inverter IV9. The eleventh NAND gate ND11 receives the output signal of the second initialization signal initial2 and the twelfth NAND gate ND12. The twelfth NAND gate ND12 receives the output signal of the eleventh NAND gate ND11 and the second inverted pulse pulseb2. The eleventh inverter IV11 inverts the output signal of the twelfth NAND gate ND12 to generate the second test mode signal Test2_mode.

The operation of the test mode entry circuit of the semiconductor memory device configured as described above will be described with reference to FIG. 8. In this case, the predetermined code of the first determination unit 112-1 of FIG. 4 is (0, 0, 0) and the predetermined code of the second determination unit 122-1 of FIG. 5 is (1, 1, 1). Suppose). In this case, the first determination unit 112-1 preset to (0, 0, 0) may be implemented as a NOR gate having three input terminals, and the second determination unit preset to (1, 1, 1). Reference numeral 122-1 may be implemented as a NAND gate and an inverter having three input stages.

If the second to fourth addresses add <2>, add <3>, and add <4> are (1, 1, 1) when the first address add <1> is transitioned high, the second When the test mode signal Test2_mode is enabled low and the reset signal reset is enabled low, the second test mode signal Test2_mode is disabled high.

Referring to Figures 2, 5, 7 in more detail the operation description as follows.

In FIG. 2, when the first address add <1> transitions high, the second pulse pulse2 is enabled high and is disabled low after a predetermined time.

In FIG. 5, for example, a preset code having the level of the second to fourth addresses add <2>, add <3>, and add <4>, which the second determination unit 122-1 has (1, If it matches 1, 1, the second discrimination signal dis2 is enabled high. The second determination signal dis2 enabled to be high is input to the second output unit 122-2 to output the second pulse pulse2 as the second test pulse pulse2_test.

In FIG. 7, the power up signal pwrup is disabled in a high state. The second pulse inverting unit 222 receives the power-up signal pwrup having a high level and inverts the second test pulse pulse2_test to generate a second inverting pulse pulse2. In this case, the second inversion pulse pulseb2 is a low enable pulse. The second flip-flop 223 outputs the second test mode signal Test2_mode enabled at the low level when the second inversion pulse pulseb2 is enabled at the low level. In addition, the second flip-flop 223 may enable the second test mode signal Test2_mode to a low level until the reset signal is enabled and the second initialization signal initial2 is enabled low. Maintain state. The power up signal pwrup is a signal that is enabled low when the power is applied to the semiconductor memory device to initialize a circuit in the semiconductor memory device and is disabled high after a predetermined time.

Meanwhile, when the second to fourth addresses add <2>, add <3>, and add <4> are (0, 0, 0) when the first address (add <1>) is transitioned low When the first test mode signal Test1_mode is enabled low and the reset signal reset is low, the first test mode signal Test1_mode is disabled high.

Referring to Figures 2, 4, 6 in more detail the operation description as follows.

In FIG. 2, when the first address add <1> transitions low, the first pulse pulse1 is enabled high and is disabled low after a predetermined time.

In FIG. 4, for example, a preset code having the level of the second to fourth addresses add <2>, add <3>, and add <4>, which the first determination unit 112-1 has (0, If it matches 0, 0, the first determination signal dis1 is enabled high. The first determination signal dis1, which is enabled high, is input to the first output unit 112-2 to output the first pulse pulse1 as the first test pulse pulse1_test.

In FIG. 6, the power up signal pwrup is disabled in a high state. The first pulse inverting unit 212 receives the power-up signal pwrup having a high level and inverts the first test pulse pulse1_test to generate a first inversion pulse pulse1. In this case, the first inversion pulse pulseb1 is a low enable pulse. The first flip-flop 213 outputs the first test mode signal Test1_mode enabled at the low level when the first inversion pulse pulseb1 is enabled at the low level. Also, the first flip-flop 213 may set the first test mode signal Test1_mode to a low level until a reset signal reset is enabled low and the first initialization signal initial1 is enabled low. Keep enabled. The power up signal pwrup is enabled when the power is applied to the semiconductor memory device to initialize the circuit in the semiconductor memory device and is disabled after a predetermined time.

The present invention supports more types of test modes than those used in conventional wafer testing. For example, in the related art, a test is performed by selecting a test mode using a second to fourth address combination when the first address transitions to high. However, in the present invention, the second to fourth operations also occur when the first address transitions to low. Since the test mode can be selected by the address combination, the test mode can be selected twice as much as before.

9 is a diagram configured to perform a refresh test that was not performed in the conventional wafer test. The test mode entry circuit according to the present invention enables the test mode signal Test1_mode enabled to be low when the second to fourth address combinations coincide with a predetermined code when the first address add <1> transitions to low. ) The signal combination unit 300 generates a refresh operation signal refresh_act enabled when the test mode signal Test1_mode is enabled low or when the refresh signal refresh is enabled low. The signal combination unit 300 includes a thirteenth NAND gate ND13, and the thirteenth NAND gate ND13 receives the test mode signal Test1_mode and the refresh signal and receives the refresh operation signal ( refresh_act). The refresh operation signal refresh_act enabled to be high is input to the refresh circuit 10 to perform a refresh operation. By performing the refresh test during the wafer test, it is possible to replace the test that repeats the active-light-precharge operation performed in the package test. This is because the refresh operation includes an operation of storing and precharging data of the semiconductor memory device back to the cell.

Accordingly, the present invention can reduce the type of test performed in the package test by making more types of test modes that can be selected during wafer testing than in the related art. In addition, the refresh operation can be tested by selecting one of the increased test modes. This can replace testing that repeats the active-light-precharge operation performed by package testing, eliminating the need for expensive equipment used in package testing. Therefore, it is effective to reduce the cost of the semiconductor memory device.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a test mode entry circuit of a semiconductor memory device according to an embodiment of the present invention;

2 is a circuit diagram of the rising pulse generator of FIG.

3 is a circuit diagram of the falling pulse generator of FIG.

4 is a detailed configuration diagram of the first output control unit of FIG. 1;

5 is a detailed configuration diagram of the second output control unit of FIG. 1;

6 is a detailed configuration diagram of the first level signal generator of FIG. 1;

7 is a detailed configuration diagram of a second level signal generator of FIG. 1;

8 is a timing diagram of a test mode entry circuit of a semiconductor memory device according to an embodiment of the present invention;

9 is a detailed configuration diagram of a semiconductor memory device to which a test entry circuit according to an exemplary embodiment of the present invention is applied.

Claims (25)

A test pulse generator configured to generate a first test pulse in response to the remaining specific address combinations when one of the plurality of specific addresses transitions low; And And a test mode signal generator configured to generate an enabled first test mode signal when the first test pulse is enabled, and to disable the first test mode signal when a reset signal is enabled. Test mode entry circuit. The method of claim 1, The test pulse generator is And generate a second test pulse in response to the remaining specific address combination when the one specific address transitions high. The method of claim 2, The test pulse generator is A polling pulse generator for outputting the first test pulse in response to the remaining specific address combinations when the one specific address transitions low; and And a rising pulse generator configured to output the second test pulse in response to the remaining specific address combinations when the one specific address transitions high. The method of claim 3, wherein The polling pulse generator A polling pulse generator that generates the pulses that are enabled when the one specific address transitions low, and And an output controller configured to output the pulse as the first test pulse when the remaining specific address combination matches the predetermined code. The method of claim 4, wherein The output control unit A discriminator configured to generate an enabled discrimination signal when the remaining specific address is input and coincides with the predetermined code; And an output unit configured to output the pulse as the first test pulse when the determination signal is enabled. The method of claim 3, wherein The rising pulse generator A rising pulse generator that generates the pulses that are enabled when the one particular address transitions high, and And an output controller configured to output the pulse as the second test pulse when the remaining specific address combination matches the predetermined code. The method of claim 6, The output control unit A discriminator configured to generate an enabled discrimination signal when the remaining specific address is input and coincides with the predetermined code; And an output unit configured to output the pulse as the second test pulse when the determination signal is enabled. The method of claim 2, The test mode signal generation unit A first level signal generator configured to generate the first test mode signal when the first test pulse is enabled, and to disable the first test mode signal when the reset signal is enabled, and And a second level signal generator configured to generate the second test mode signal when the second test pulse is enabled and to disable the second test mode signal when the reset signal is enabled. Test mode entry circuit. The method of claim 8, The first level signal generator An initialization unit generating an initialization signal in response to a power-up signal or the reset signal; A pulse inversion unit inverting the first test pulse in response to the power up signal to generate an inversion pulse; and And a flip-flop configured to generate the first test mode signal in response to the inversion pulse when initialized in response to the initialization signal. The method of claim 9, The initialization unit And generate the enabled initialization signal when the power up signal is enabled or the reset signal is enabled. The method of claim 9, The pulse inversion unit Output the signal of a specific level irrespective of the first test pulse when the power up signal is enabled, and generate the inverted pulse by inverting the first test pulse when the power up signal is disabled. The test mode entry circuit of the semiconductor memory device. The method of claim 9, The flip flop And the first test mode signal is enabled when the inverted pulse is enabled, and the first test mode signal is disabled and initialized when the initialization signal is enabled. The method of claim 8, The second level signal generator An initialization unit generating an initialization signal in response to a power-up signal or the reset signal; A pulse inversion unit inverting the second test pulse to generate an inversion pulse in response to the power up signal, and And a flip-flop configured to generate the second test mode signal in response to the inversion pulse when initialized in response to the initialization signal. The method of claim 13, The initialization unit And generate the enabled initialization signal when the power up signal is enabled or the reset signal is enabled. The method of claim 13, The pulse inversion unit Output the signal of a specific level irrespective of the second test pulse when the power up signal is enabled, and generate the inverted pulse by inverting the second test pulse when the power up signal is disabled. The test mode entry circuit of the semiconductor memory device. The method of claim 13, The flip flop And the second test mode signal is enabled when the inverted pulse is enabled, and the second test mode signal is disabled and initialized when the initialization signal is enabled. A test mode entry circuit for generating an enabled test mode signal in response to the remaining specific address combinations when one of a plurality of specific addresses transitions, and disabling the test mode signal when a reset signal is enabled; A signal combination unit configured to generate an enabled refresh operation signal when the test mode signal is enabled or the refresh signal is enabled; And And a refresh circuit configured to perform a refresh operation when the refresh operation signal is enabled. The method of claim 17, The test mode entry circuit And enable the test mode signal if the remaining specific address combination coincides with a predetermined code when the one specific address transitions. The method of claim 18, The test mode entry circuit A test pulse generation unit generating a test pulse enabled when the one specific address transitions and outputting the test pulse when the remaining specific address combination matches the predetermined code; and And a test mode signal generator configured to enable the test mode signal when the test pulse is enabled and disable the test mode signal when the reset signal is enabled. The method of claim 19, The test pulse generator is A pulse generator that generates the pulse that is enabled when the one specific address transitions, and And an output controller configured to output the pulse as the test pulse when the remaining specific address combination is the same as the predetermined code. The method of claim 20, The output control unit A discriminator configured to receive the remaining specific address and generate an enabled discrimination signal when the predetermined code is the same as the preset code; And an output unit configured to output the pulse as the test pulse when the determination signal is enabled. The method of claim 19, The test mode signal generation unit An initialization unit generating an initialization signal in response to a power-up signal or the reset signal; A pulse inversion unit inverting the test pulse in response to the power up signal to generate an inversion pulse, and And a flip-flop configured to generate the test mode signal in response to the inversion pulse when initialized in response to the initialization signal. The method of claim 22, The initialization unit And generate the initialization signal when the power up signal is enabled or the reset signal is enabled. The method of claim 23, The pulse inversion unit And when the power-up signal is enabled, output a signal having a specific level irrespective of the test pulse, and when the power-up signal is disabled, invert the test pulse to generate the inverted pulse. . The method of claim 23, The flip flop And enable the test mode signal when the inversion pulse is enabled, and disable and initialize the test mode signal when the initialization signal is enabled.
KR1020070081590A 2007-08-14 2007-08-14 Circuit for entering test mode and semiconductor memory apparatus using the same KR20090017104A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11881244B2 (en) 2021-07-27 2024-01-23 SK Hynix Inc. Semiconductor memory apparatus including address generation circuit, row hammer detection circuit and operation determination circuit operating to ensure a stable refresh operation against row hammering

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11881244B2 (en) 2021-07-27 2024-01-23 SK Hynix Inc. Semiconductor memory apparatus including address generation circuit, row hammer detection circuit and operation determination circuit operating to ensure a stable refresh operation against row hammering

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