KR20090016839A - Method for fabricating capacitor - Google Patents

Abstract

A capacitor manufacturing method is provided to remove a sacrificing layer which catches the frame of a bottom electrode by fixing the upper part of the bottom electrode of a cylinder type with a support pattern. An interlayer insulating film is formed on the substrate. A part of the interlayer insulating film is etched and a contact hole is formed. A storage node contact plug lice reclaiming a contact hole inside is formed. An etch stopping layer and a sacrificing layer(15) are laminated on the substrate including the storage node contact plug. An open pattern, which opens the storage node contact plug by successively etching the sacrificing layer and the etch stopping layer, is formed. A conductive film is formed on the overall structure including the open pattern. A bottom electrode(17) is formed by progressing a lower electrode separation process. A support film having bad step coverage is formed on the substrate. A hard mask film is formed on the substrate. A photoresist pattern is formed on the hard mask film. The hard mask film is etched by using the photoresist pattern as an etching barrier. A support film pattern(18A) is formed by etching the support film. The support film pattern is removed. By forming a dielectric layer and an upper electrode covering the bottom electrode, a capacitor is manufactured.

Description

Capacitor Manufacturing Method {METHOD FOR FABRICATING CAPACITOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device for fixing between cylindrical lower electrodes during a semiconductor device manufacturing process.

A DRAM (Dynamic Random Access Memory) device representing a semiconductor device is composed of one capacitor and one transistor. As the degree of integration of such DRAM devices increases, the area of the electrode of the capacitor needs to be increased to secure sufficient capacitance of the capacitor. The structure developed to satisfy this is a cylinder type.

The capacitor of the cylindrical structure forms a lower electrode of a cylindrical shape, and is formed to surround the dielectric film and the upper electrode to maximize the area of the capacitor electrode.

However, the lower electrode of the cylinder type has a problem in which the lower electrode collapses during full deep out. The lower electrode of the cylinder type has a small contact area with the bottom surface. On the other hand, it has a high height.

Therefore, there is a need for a technology that can solve the problem of falling of the lower electrode.

The present invention has been made to solve the above problems of the prior art, it is an object of the present invention to provide a method for manufacturing a capacitor that prevents the phenomenon that the lower electrode of the cylindrical shape falls.

Capacitor of the present invention for achieving the above object, forming a sacrificial film pattern having a plurality of open patterns, forming a lower electrode in each of the inside of the open pattern, fixing the upper portion of the adjacent lower electrode It provides a capacitor manufacturing method comprising the step of forming a support pattern, the step of removing the sacrificial film pattern and the support pattern.

The present invention based on the above-mentioned means for solving the problem is to remove the sacrificial film holding the frame of the lower electrode after fixing the upper portion of the lower electrode of the cylindrical form with a support pattern. At this time, the problem of falling down is prevented because the lower electrodes are fixed to each other.

Therefore, the reliability of a capacitor can be improved, and also the reliability and stability of the semiconductor element containing this capacitor can be improved.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

An embodiment to be described later prevents a phenomenon in which the cylindrical lower electrode falls over as a support pattern for fixing the lower electrode.

The support pattern fixes the upper part of the lower electrode. In detail, among the adjacent lower electrodes, the lower electrodes are fixed in the short distance direction, and the support pattern is removed in the long distance direction. This is to efficiently fix the lower electrodes, and to proceed with the sacrificial film removal (pull-dip out process).

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

2A to 2E are process plan views corresponding to process cross-sectional views of FIGS. 1A to 1E.

As shown in FIG. 1A, after forming the interlayer insulating film 12 on the substrate 11, planarization is performed to alleviate the step difference caused by the underlying structure.

Thereafter, the interlayer insulating layer 12 is partially etched to form a contact hole.

Subsequently, a storage node contact plug 13 filling the inside of the contact hole is formed.

The storage node contact plug 13 is made of polysilicon. The etch stop layer 14 and the sacrificial layer 15 are stacked on the entire surface of the substrate on which the storage node contact plug 13 is formed.

The etch stop layer 14 and the sacrificial layer 15 are thin films having a high etching selectivity. For example, the etch stop layer 14 is a silicon nitride layer Si ₃ N ₄ , and the sacrificial layer 15 is silicon. It is possible to form an oxide film (SiO _x , where x is a natural number exceeding zero). In addition, the sacrificial layer 15 is formed by a plasma deposition method, for example, a plasma enhanced chemical vapor deposition (PECVD) method. Or it can be formed by a CVD method.

Subsequently, the sacrificial layer 15 and the etch stop layer 14 are sequentially etched to form an open pattern 16 for opening the storage node contact plug 13.

The open pattern 16 is formed by etching the sacrificial layer 15 until the etching stops at the etch stop layer 14, and then etching the etch stop layer 14 to expose the storage node contact plug 13.

Etching of the sacrificial layer 15 may be performed in two steps. The first etching may be a dry etching process using a CF-based etching gas, for example, an etching process using a reactive ion etching (RIE) plasma source. For example, the CF gas may be CF ₄ gas. Secondary etching is performed by etching with O ₂ / Ar mixed gas to remove the polymer generated.

The open pattern 16 is a hole having a three-dimensional structure in which the lower electrode of the capacitor is to be formed.

Subsequently, after the conductive film is formed on the resultant product on which the open pattern 16 is formed, the lower electrode 17 is formed to form a lower electrode 17.

The conductive film for forming the lower electrode 17 is at least one selected from the group consisting of a titanium film (Ti), a titanium nitride film (TiN), tungsten (W), a ruthenium film (Ru), and an aluminum film (Al). It is formed by vapor deposition (CVD). For example, it may be a laminated film having a titanium nitride film / titanium (TiN / Ti) structure.

The lower electrode separation process is an etch back process, in which Cl ₂ or CF-based gas is singly or mixed and proceeds without a barrier. Here, the CF-based gas may be, for example, CF ₄ gas. In addition, since the etch back process is performed without the protective layer, the lower electrode 17 is positioned below the upper surface of the sacrificial layer 15.

Referring to FIG. 2A corresponding to FIG. 1A, it can be seen that a plurality of lower electrodes 17 having a circular cylinder shape and a sacrificial layer 15 surrounding the lower electrodes 17 are formed.

The plurality of lower electrodes 17 may be aligned horizontally and vertically or have a zigzag shape. For this reason, the short distance A and the long distance B exist between adjacent lower electrodes 17. In cross-section, short distance (A) corresponds to section I-I ', and long distance (B) corresponds to section II-II'.

As shown in FIG. 1B, a supporting layer 18 having poor step coverage is deposited on the substrate 11 on which the lower electrode 17 is formed.

The support film 18 with poor step coverage is a Si _x N _y film (x, y is a natural number exceeding zero). For example, it may be a silicon nitride film (Si ₃ N ₄ ). And, the thickness has a range of 105 ~ 500Å.

The support layer 18 is not formed on the bottom surface of the open pattern 16 having a high aspect ratio because of poor step coverage, and covers only a portion of the inner wall of the lower electrode 16.

Referring to FIG. 2B corresponding to FIG. 1B, it can be seen that the top surface of the lower electrode 17 is not exposed in plan view, and only the bottom surface is exposed. This is because the support film 18 covers a portion of the inner wall of the lower electrode 17.

In addition, the sacrificial layer 15 is not exposed due to the supporting layer 18.

As shown in FIG. 1C, after the hard mask film 19 is formed on the substrate 11 on which the support film 18 is formed, the photoresist pattern 20 is formed on the hard mask film 19.

The photoresist pattern 20 covers the hard mask film 19 in the short distance direction (I-I ') between the lower electrodes 17, and exposes the hard mask film 19 in the long distance direction (II-II'). Let's do it.

That is, the photoresist pattern 20 in the short distance direction covers the entire hard mask film 19, and the photoresist pattern 20 in the long distance direction may remove the support layer 18, and the lower electrode 17 may be removed. Form to protect the inside of the.

The hard mask film 19 is not formed inside the lower electrode 17 because of poor step coverage. To this end, the hard mask film 19 is formed of a Si _x O _y film (x, y is a natural number exceeding zero). For example, it may be a SiO ₂ film.

Referring to FIG. 2C, which corresponds to FIG. 1C, the photoresist pattern 20 exposes the hard mask layer 19 in the long distance B direction of the plurality of lower electrodes 17 represented by dotted lines, and the short distance A It is seen that the hard mask film 19 is covered in the direction of.

As shown in FIG. 1D, the hard mask layer 19 is etched using the photoresist pattern 20 as an etch barrier. The support layer 18 is etched using the etched hard mask layer 19 as an etch barrier to form the support layer pattern 18A.

Etching of the support layer 18 is performed by using a reactive ion etching (RIE) plasma source.

The photoresist pattern 20 covers the hard mask film 19 in the short distance direction (I-I ') between the lower electrodes 17, and exposes the hard mask film 19 in the long distance direction (II-II'). As a result, the support film pattern 18A remains only in the short distance direction.

The support layer pattern 18A has a form capable of fixing the upper part between the lower electrodes 17. For example, it has the form '∩'.

Referring to FIG. 2D corresponding to FIG. 1D, a supporting film pattern 18A is formed in the short distance direction (I-I ') between the lower electrodes 17, and a sacrificial film is formed in the long distance direction (II-II'). It can be seen that (15) is exposed.

In addition, it can be seen that the support layer pattern 18A fixes the upper portion between the lower electrodes 17.

As shown in FIG. 1E, the sacrificial layer 15 is removed by performing a full dip-out.

The pull-out process is oxide wet etching, using HF solution. At this time, the underlying structure is prevented from being attacked by the etch stop layer 14.

As a result, the inside and the outside of the lower electrode 17 are exposed.

Referring to FIG. 2E corresponding to FIG. 1E, a supporting film pattern 18A is formed in the short distance direction (I-I ') between the lower electrodes 17, and the etch stop is performed in the long distance direction (II-II'). It can be seen that the membrane 14 is exposed. Here, the sacrificial layer 15 under the support layer pattern 18A is also removed.

As shown in FIG. 1F, the support film pattern 18A is removed.

Subsequently, a dielectric film and an upper electrode are formed to cover the lower electrode 17 to fabricate a capacitor.

In the embodiment of the present invention as described above, the sacrificial layer 15 holding the frame of the lower electrode 17 is removed after fixing the upper portion of the lower electrode 17 in the form of a cylinder with the support pattern 18A. At this time, the problem of falling down is prevented because the lower electrodes 17 are fixed to each other.

Thereafter, the support pattern 18A is removed, a dielectric film and an upper electrode are formed to prevent a fall phenomenon, and a capacitor having high capacitance is manufactured.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

2A to 2E are process plan views corresponding to the process cross-sectional views of FIGS. 1A to 1E.

Explanation of symbols on the main parts of the drawings

15: sacrificial film 17: lower electrode

18A: Support Pattern

Claims (9)

Forming a sacrificial layer pattern having a plurality of open patterns; Forming lower electrodes in each of the open patterns; Forming a support pattern for fixing the upper portions of neighboring lower electrodes; Removing the sacrificial layer pattern; And Removing the support pattern Capacitor manufacturing method comprising a. The method of claim 1, Forming the support pattern, After forming a lower electrode in each of the open patterns, contacting an upper portion of an inner wall of the lower electrode and forming a support layer on the sacrificial layer pattern; Forming a hard mask pattern covering the support film in the short distance direction between the lower electrodes and exposing the support film in the long distance direction between the lower electrodes; And Etching the support layer using the hard mask pattern as an etch barrier to expose the sacrificial layer pattern, and forming a support pattern to fix an upper portion of neighboring lower electrodes. Capacitor manufacturing method comprising a. The method of claim 2, The support film is a capacitor manufacturing method of forming a Si _x N _y film (x, y is a natural number greater than zero). The method of claim 2, The supporting film is a silicon nitride film (Si ₃ N ₄ ) to form a capacitor manufacturing method. The method of claim 2, The etching of the support film is a capacitor manufacturing method proceeds using a RIE plasma source. The method of claim 1, The sacrificial film pattern is a capacitor manufacturing method of forming a SiOx (x is a natural number greater than zero). The method of claim 1, The sacrificial layer pattern is a silicon oxide film (SiO ₂ ) to form a capacitor manufacturing method. The method of claim 1, The sacrificial film pattern is a capacitor manufacturing method formed by PECVD or CVD. The method of claim 1, The lower electrode is a capacitor manufacturing method to form a cylinder.

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