CN219066823U

CN219066823U - Semiconductor device

Info

Publication number: CN219066823U
Application number: CN202120380570.3U
Authority: CN
Inventors: 张钦福; 冯立伟; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-08-20
Filing date: 2020-08-20
Publication date: 2023-05-23
Anticipated expiration: 2030-08-20
Also published as: CN212695137U

Abstract

The utility model discloses a semiconductor device, which comprises a substrate, wherein the substrate comprises a cell array region, a peripheral circuit region and a middle region positioned between the peripheral circuit regions of the cell array region, a laminated structure is formed on the substrate, the laminated structure comprises a plurality of capacitor structures and a protection ring structure, the capacitor structures are formed on the cell array region, a supporting structure is arranged between at least part of adjacent capacitor structures, and the supporting structure comprises a first supporting structure and a second supporting layer; a guard ring structure is formed on the intermediate region and surrounds the capacitor structure on the cell array region. The electrode structure of the cell array region can be supported and the toppling of the lower electrode can be avoided by arranging the guard ring structure in the middle region, so that the stability of the structure is improved, and meanwhile, the physical isolation effect on the cell array region and the peripheral circuit region can be realized, and the current leakage is avoided.

Description

Semiconductor device

The application is a divisional application with a patent name of 'a semiconductor device', the application number of the original application is CN202021749655.6, and the application date is 2020, 8 months and 20 days.

Technical Field

The present utility model relates to the field of semiconductors, and more particularly, to a semiconductor device.

Background

In the related art, in order to increase the degree of integration of a semiconductor device, the area occupied by each semiconductor element in the semiconductor device is reduced. In order not to affect the capacitance of the capacitor, the effective area of the bottom electrode in the capacitor structure is generally selected to be increased, for example, a three-dimensional bottom electrode is manufactured, and the three-dimensional bottom electrode may be formed with a cylindrical structure, wherein the sidewall of the bottom electrode of the cylindrical structure extends in the direction perpendicular to the surface of the substrate, so as to increase the height of the bottom electrode and expand the effective area, thereby ensuring the capacitance required by the semiconductor device.

However, increasing the height of the lower electrode may cause tilting of the lower electrode, which may be solved by providing a support structure between the lower electrodes, but the presence of the support structure may also introduce new problems, which may stress the lower electrode causing twisting of the lower electrode, and may also cause electrical connections between different circuit areas, causing current leakage, thereby affecting the performance of the semiconductor device.

Disclosure of Invention

The utility model aims to solve the technical problems that: and how to improve the stability of the lower electrode so as to reduce the generation of electric connection between different circuit areas and improve the performance of the semiconductor device.

In order to solve the above technical problems, the present utility model provides a semiconductor device, comprising:

a substrate including a cell array region, a peripheral circuit region, and an intermediate region between the cell array region and the peripheral circuit region, the substrate including a semiconductor substrate and an interlayer insulating layer on the semiconductor substrate;

a stacking structure is formed on the substrate, the stacking structure comprises a plurality of capacitor structures and a protection ring structure, wherein the capacitor structures are formed on the cell array region, a supporting structure is arranged between at least part of adjacent capacitor structures, and the supporting structure comprises a first supporting structure and a second supporting layer; the guard ring structure is formed on the intermediate region and surrounds the capacitor structure on the cell array region.

Optionally, the guard ring structure includes a plurality of guard rings, the plurality of guard rings extending in a direction perpendicular to the substrate, and extending to different depths.

Optionally, the plurality of guard rings extend along a direction perpendicular to the substrate, and the extending depths are different, including:

the plurality of guard rings extend in a direction perpendicular to the substrate, wherein a bottom surface of at least one of the guard rings is in contact with a substrate upper surface of the semiconductor device.

Optionally, a stacked structure is formed on the substrate, the stacked structure includes a plurality of capacitor structures and a guard ring structure, and the capacitor structures include:

a lower electrode;

the first support structure and the second support layer support at least part of the outer side wall of the lower electrode, and are arranged at different heights of the outer side wall of the lower electrode;

the capacitor dielectric layer covers the lower electrode, the second supporting layer and the upper surface of the cell array region substrate;

and the upper electrode covers the capacitance dielectric layer.

Optionally, the capacitor dielectric layer further covers the guard ring structure and at least a portion of an upper surface of the second support layer in the peripheral circuit region.

Optionally, the upper electrode covering the capacitive dielectric layer includes: the upper electrode partially or completely covers the capacitive dielectric layer.

Optionally, the first support structure includes a plurality of sub-support layers and an insulating dielectric layer between each of the sub-support layers.

Optionally, the semiconductor device further includes: and the ONONO structure is positioned on the substrate of the peripheral circuit region and consists of a first dielectric layer, the first supporting structure, a second dielectric layer, the second supporting layer and an oxide layer.

One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:

the semiconductor device applying the utility model comprises a substrate 10, wherein the substrate 10 comprises a cell array region, a peripheral circuit region and a middle region positioned between the peripheral circuit regions of the cell array region, a laminated structure is formed on the substrate 10, the laminated structure comprises a plurality of capacitor structures and a protection ring structure 17, the capacitor structures are formed on the cell array region, a supporting structure is arranged between at least part of adjacent capacitor structures, and the supporting structure comprises a first supporting structure 12 and a second supporting layer 18; the guard ring structure is formed on the middle region and surrounds the capacitor structure on the cell array region. The guard ring structure 17 is arranged in the middle area, so that the electrode structure of the cell array area can be supported, the toppling of the lower electrode 19 is avoided, the stability of the structure is improved, and meanwhile, the physical isolation effect on the cell array area and the peripheral circuit area can be achieved, the current leakage is avoided, and the performance of the semiconductor device is greatly improved.

Drawings

The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The drawings included herein are:

fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present utility model;

FIG. 2 is a schematic cross-sectional view illustrating a stacked structure formed on a substrate according to an embodiment of the present utility model;

FIG. 3 (1) is a schematic top view of a guard ring trench formed around the periphery of a cell array region in a middle region according to an embodiment of the present utility model; fig. 3 (2) is a schematic cross-sectional view showing a structure in which a guard ring trench surrounding the periphery of a cell array region is formed in a middle region according to an embodiment of the present utility model;

fig. 4 is a schematic cross-sectional view illustrating a structure of forming a guard ring in an intermediate region according to an embodiment of the present utility model;

fig. 5 is a schematic flow chart illustrating formation of a capacitor structure in a cell array region according to an embodiment of the present utility model;

fig. 6 to fig. 12 are schematic cross-sectional structures corresponding to each implementation step of forming a capacitor structure in a cell array region according to an embodiment of the present utility model;

fig. 13 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present utility model;

fig. 14 is a schematic cross-sectional structure of forming a second guard ring trench according to an embodiment of the present utility model.

Detailed Description

In order to make the objects, technical solutions and advantages of the present utility model more apparent, the following detailed description of the implementation method of the present utility model will be given with reference to the accompanying drawings and examples, by which the technical means are applied to solve the technical problems, and the implementation process for achieving the technical effects can be fully understood and implemented accordingly.

In view of this, the present utility model provides a semiconductor device, which includes a substrate 10, the substrate 10 including a cell array region, a peripheral circuit region, and an intermediate region between the peripheral circuit regions of the cell array region, a stacked structure formed on the substrate 10, the stacked structure including a plurality of capacitor structures formed on the cell array region with a support structure between at least part of adjacent capacitor structures, and a guard ring structure 17, the support structure including a first support structure 12 and a second support layer 18; guard ring structure 17 is formed on the middle region and surrounds the capacitor structure on the cell array region. The guard ring structure 17 is arranged in the middle area, so that the electrode structure of the cell array area can be supported, the toppling of the lower electrode 19 is avoided, the stability of the structure is improved, and meanwhile, the physical isolation effect on the cell array area and the peripheral circuit area can be achieved, the current leakage is avoided, and the performance of the semiconductor device is greatly improved.

Example 1

Referring to fig. 1, fig. 1 shows a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present utility model, which includes the following steps:

step S101: a stacked structure is formed on the substrate 10, wherein the stacked structure includes a first dielectric layer 11, a first support structure 12, and a second dielectric layer 13 sequentially formed on the substrate 10, and the substrate 10 includes a cell array region, a peripheral circuit region, and an intermediate region between the cell array region and the peripheral circuit region.

Step S102: a guard ring trench 16 is formed around the periphery of the cell array region in the middle region.

Step S103: a first insulating material is deposited on the upper surface of the second dielectric layer 13 to form a second support layer 18 and a second insulating material is deposited on the bottom surface and sidewalls of the guard ring trench to form a guard ring structure 17.

Step S104: a capacitor structure is formed in the cell array region.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view illustrating a stacked structure formed on a substrate 10 according to an embodiment of the present utility model. In the embodiment of the present utility model, step S101 may specifically be to sequentially deposit the first dielectric layer 11, the first support structure 12 and the second dielectric layer 13 on the substrate by using a chemical vapor deposition or a physical vapor deposition method.

Among them, as an example, the base 10 may include a semiconductor substrate 101 and an interlayer insulating layer 102 on the semiconductor substrate 101, and as an example, the semiconductor substrate 101 may include a Si substrate, a Ge substrate, a SiGe substrate, and the like, the interlayer insulating layer 102 may include borophosphosilicate glass, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, a carbon-containing low dielectric constant dielectric, and the like, a gate structure 14 of a transistor is provided in the interlayer insulating layer 102 of a peripheral circuit region, and source/drain regions 15 of the transistor are formed in the semiconductor substrate 101 on both sides of the gate structure 14.

In an embodiment of the present utility model, the first dielectric layer 11 or the second dielectric layer 13 may include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), plasma Enhanced (PE) -Tetraethylorthosilicate (TEOS), high Density Plasma (HDP) -oxide, etc., and the first dielectric layer 11 and the second dielectric layer 13 may be formed of the same material.

The first support structure 12 may be formed of a material that is different from the material of the first dielectric layer 11 and the second dielectric layer 13 and that is selectively etchable, and as an example, the first support structure 12 may include at least one of silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon oxide, silicon nitride, and silicon oxynitride. As another example, the first support structure 12 may also be provided to include a plurality of sub-support layers and an insulating dielectric layer between adjacent sub-support layers. The sub-supporting layers may include at least one of silicon carbonitride, silicon oxycarbide, silicon carbonitride oxide, silicon nitride and silicon oxynitride, each of the sub-supporting layers may be spaced apart in a direction perpendicular to the substrate 10, and the insulating dielectric layer may be selected from the same material as the first dielectric layer 11 or the second dielectric layer 13. By arranging a plurality of sub-supporting layers at intervals, the stability of the lower electrode can be improved.

Referring to fig. 3 (1) and 3 (2), fig. 3 (1) is a schematic top view illustrating that a guard ring trench 16 is formed around the periphery of the cell array region in the middle region according to an embodiment of the present utility model; fig. 3 (2) is a schematic cross-sectional view showing a structure of forming a guard ring trench 16 around the periphery of a cell array region in the middle region according to an embodiment of the present utility model. As an example, forming the guard ring trench 16 around the periphery of the cell array region in the middle region may include: depositing a photoresist layer on the second dielectric layer 13, patterning the photoresist layer to form at least one first etching window in the middle region; the first dielectric layer 11, the first support structure 12, and the second dielectric layer 13 of the middle region are etched based on the first etching window until the upper surface of the substrate 10 exposing the semiconductor device is stopped, at least one first guard ring groove 161 is formed around the periphery of the cell array region, and as a specific example, one first guard ring groove 161 is formed around the periphery of the cell array region, the width of the first guard ring groove being the same as the width of the middle region.

Referring to fig. 4, fig. 4 is a schematic cross-sectional view of a guard ring structure 17 formed in an intermediate region according to an embodiment of the present utility model. Specifically, in step S103, a first insulating material is synchronously deposited on the upper surface of the second dielectric layer 13 and the bottom surface and the side wall of the guard ring trench 16, where the first insulating material and the second insulating material are the same. After the first insulating material is simultaneously deposited on the bottom surface and the side wall of the guard ring trench 16, the guard ring structure 17 is formed, and it should be noted that the first insulating material may be used to fill the guard ring trench 16 when the guard ring structure 17 is formed; after depositing the first insulating material on the upper surface of the second dielectric layer 13, a second support layer 18 may be formed. The guard ring structure 17 at the periphery of the cell array region can perform a function of physically isolating the cell array region from the peripheral circuit region, so as to avoid current leakage, and in addition, the guard ring structure 17 and the second support layer 18 of the peripheral circuit region can protect the peripheral circuit region from being etched, specifically, can avoid affecting the device performance of the peripheral circuit region due to subsequent etching of the peripheral circuit region in the process of forming the capacitor structure in the cell array region.

Referring to fig. 5, fig. 5 illustrates a flow chart of forming a capacitor structure in a cell array region according to an embodiment of the utility model.

Specifically, step S104 may include:

step S1041: the second support layer 18 of the cell array region is patterned.

Step S1042: the first dielectric layer 11, the first support structure 12 and the second dielectric layer 13 of the cell array region are etched using the patterned second support layer 18 as a mask to form a lower electrode recess in the stacked structure of the first dielectric layer 11, the first support structure 12 and the second dielectric layer 13, and a conductive material is deposited in the lower electrode recess to form a lower electrode 19, as shown in fig. 6.

Step S1043: a mask layer 20 is deposited on the stacked structure formed with the lower electrode 19.

Step S1044: the mask layer 20 is patterned to expose an upper surface of at least a portion of the second support layer 18 in the cell array region.

Step S1045: the first dielectric layer 11, the second dielectric layer 13, the exposed second support layer 18 and the first support structure 12 under the exposed second support layer 18 are etched.

Step S1046: a capacitor dielectric layer 21 is deposited conformally covering the lower electrode 19, the second support layer 18 and the upper surface of the cell array region substrate.

Step S1047: a conductive material is deposited on the capacitive dielectric layer 21 to form an upper electrode 22.

The second support layer 18 may include at least one of silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon oxide, silicon nitride, and silicon oxynitride.

In the embodiment of the present utility model, step S1042 may specifically be to etch the first dielectric layer 11, the first supporting structure 12 and the second dielectric layer 13 of the cell array region by using a dry etching process or a wet etching process, so as to form a plurality of lower electrode grooves in the stacked structure formed by the first dielectric layer 11, the first supporting structure 12 and the second dielectric layer 13. And utilizes a deposition process with good step coverage, such as: a chemical vapor deposition process deposits a conductive material in the bottom electrode recess to form the bottom electrode 19. As an example, the lower electrode 19 may be formed using a metal or a metal nitride.

As an example, the steps S1043 to S1045 may be specifically:

referring to fig. 7, a mask layer 20 is deposited on the stacked structure formed with the lower electrode 19, and specifically, a deposition process having a poor step coverage may be selected to deposit the mask layer 20 on the stacked structure formed with the lower electrode, so that a void may be formed on the inner wall of the lower electrode.

Referring to fig. 8, the mask layer 20 is patterned to expose an upper surface of at least a portion of the second support layer 18 located in the cell array region. As an example, the patterned mask layer 20 may be specifically formed by depositing a photoresist layer with a target pattern on the mask layer 20, using the photoresist layer as a mask, and performing photolithography and development on the mask layer 20, thereby forming the patterned mask layer 20.

Referring to fig. 9, the first dielectric layer 11, the second dielectric layer 13, the exposed second support layer 18, and the first support structure 12 under the exposed second support layer 18 are etched, and the mask layer 20 is removed after the etching is completed. As an example, etching the first dielectric layer 11, the second dielectric layer 13, the exposed second support layer 18, and the first support structure 12 under the exposed second support layer 18 may include etching the exposed second support layer 18 with the patterned mask layer 20 as a mask; then selecting a proper etching solvent to selectively etch away the second dielectric layer 13 between the adjacent lower electrodes 19; etching the first support structure 12 between adjacent lower electrodes 19 from which the second support layer 18 has been etched; finally, the first dielectric layer 11 is etched away.

In the embodiment of the present utility model, step S1046 may specifically be to deposit the capacitor dielectric layer 21 by a deposition process with a better step coverage effect, as an example, as shown in fig. 10 (1), the capacitor dielectric layer 21 conformally covers the lower electrode 19, the second supporting layer 18 of the cell array region, and the upper surface of part of the guard ring structure 17; as another example, referring to fig. 10 (2), the capacitor dielectric layer 21 conformally covers the lower electrode 19, the second support layer 18 of the cell array region, the guard ring structure 17, and the second support layer 18 of a part of the peripheral array region, and in other embodiments of the present utility model, the capacitor dielectric layer 21 conformally covers the lower electrode 19, the guard ring structure 17, and the second support layer 18 of the cell array region and the whole peripheral circuit region, wherein in the cell array region, a contact window may be further disposed in the interlayer insulating layer 102 under the lower electrode 19. As an example, the capacitive dielectric layer 21 may include at least one of an oxide, a nitride, or a high dielectric layer constant material.

Further, a conductive material is deposited on the capacitor dielectric layer 21 to form the upper electrode 22, and as an example, a metal layer 23 may be further deposited on the upper electrode 22, and the metal layer 23 may be tungsten. The upper electrode 22 and the metal layer 23 may partially cover the capacitor dielectric layer 21, as shown in fig. 10 (1), or may completely cover the capacitor dielectric layer 21, as shown in fig. 10 (2).

The upper electrode 22 may fill the area between the adjacent lower electrodes 19 provided with the supporting structure in addition to the conformal covering capacitor dielectric layer 21, and it should be noted that the capacitor dielectric layer 21 may also be formed on the lower surface of the second supporting layer 18 located in the cell array area, and the upper electrode 22 is isolated from the lower electrode 19 and the supporting structure by the capacitor dielectric layer 21.

It should be noted that, in the embodiment of the present utility model, in order to reduce the step heights of the peripheral array region and the cell array region, the oxide layer 24 may be further deposited, and as an example, after depositing the first insulating material on the upper surface of the second dielectric layer 13 to form the second support layer 18, the method may further include: an oxide layer 24 is deposited on the upper surface of the second support layer 18 of the peripheral circuit region to form an ONONO structure, i.e., an oxide-nitride-oxide structure, consisting of the first dielectric layer 11, the first support structure 12, the second dielectric layer 13, the second support layer 18 and the oxide layer 24. Here, as shown in fig. 11, the oxide layer 24 may be deposited on the metal layer 23 located in the cell array region and the second support layer 18 located in the peripheral circuit region at the same time to equalize the structural heights of the peripheral circuit region and the cell array region.

In addition, referring to fig. 12, the oxide layer 24 may be further etched to form a contact hole exposing the metal layer 23 in the cell array region, and the oxide layer 24, the second support layer 18, the second dielectric layer 13, the first support structure 12, and the first dielectric layer 11 in the peripheral circuit region may be etched to form a contact hole exposing a conductive contact plug, which is not shown in the drawing, in the interlayer insulating layer 102.

The above is a method for manufacturing a semiconductor device according to an embodiment of the present utility model, by forming a stacked structure on a substrate 10, where the stacked structure includes a first dielectric layer 11, a first support structure 12, and a second dielectric layer 13 sequentially formed on the substrate, and the substrate 10 includes a cell array region, a peripheral circuit region, and an intermediate region between the cell array region and the peripheral circuit region; forming a guard ring trench 16 around the periphery of the cell array region in the middle region; depositing a first insulating material on the upper surface of the second dielectric layer 13 to form a second support layer 18, and depositing a second insulating material on the bottom surface and sidewalls of the guard ring trench 16 to form a guard ring structure 17; a capacitor structure is formed in the cell array region. The method can avoid the subsequent etching of the peripheral circuit region when the capacitor structure is formed in the cell array region by forming the guard ring structure 17 in the middle region between the cell array region and the peripheral circuit region, thereby playing a role in protecting the device performance of the peripheral circuit region. In addition, the electrode structure of the cell array region can be supported, the toppling of the lower electrode 19 is avoided, the stability of the structure is improved, and meanwhile, the physical isolation effect on the cell array region and the peripheral circuit region can be achieved, the current leakage is avoided, and therefore the performance of the semiconductor device is greatly improved.

In the above, a semiconductor device manufacturing method according to the present utility model may further form different guard ring structures 17, specifically, please refer to the second embodiment.

Example two

The second embodiment provided by the present utility model can be further implemented based on the semiconductor device manufacturing method shown in the first embodiment, and in this embodiment, a description will be focused on the steps performed differently from those in the first embodiment.

Referring to fig. 13, fig. 13 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present utility model, which includes:

step S201: a stacked structure is formed on the substrate 10, wherein the stacked structure includes a first dielectric layer 11, a first support structure 12, and a second dielectric layer 13 sequentially formed on the substrate, and the substrate 10 includes a cell array region, a peripheral circuit region, and an intermediate region between the cell array region and the peripheral circuit region.

Step S202: a photoresist layer is deposited over the second dielectric layer 13.

Step S203: the photoresist layer is patterned to form at least one first etch window in the intermediate region.

Step S204: the first dielectric layer 11, the first support structure 12 and the second dielectric layer 13 of the intermediate region are etched based on the first etching window until the upper surface of the substrate 10 exposing the semiconductor device is stopped, forming at least one first guard ring groove 161 surrounding the periphery of the cell array region.

Step S205: the photoresist layer is patterned to form a second etch window in the middle region.

Step S206: the intermediate region is etched based on the second etching window, and a second guard ring trench 162 is formed around the periphery of the cell array region, the second guard ring trench 162 having a different depth from the first guard ring trench 161.

Step S207: a first insulating material is deposited on the upper surface of the second dielectric layer 13 to form a second support layer 18 and a second insulating material is deposited on the bottom surface and sidewalls of the guard ring trench 16 to form a guard ring structure 17.

Step S208: a capacitor structure is formed in the cell array region.

The steps S201, S207 to S208 may be the same as the steps S101, S103 to S104 in the first embodiment, and will not be described herein for brevity.

In the embodiment of the present utility model, steps S203 to S204 may be performed first and then steps S205 to S206 may be performed, or steps S203 and S205 may be performed simultaneously and then steps S204 and S206 may be performed separately, or steps S205 to S206 may be performed first and then steps S203 to S204 may be performed, and the execution sequence of steps S203 to S204 and S205 to S206 is not particularly limited in the embodiment of the present utility model.

In step S204, a schematic top view of a structure of forming at least one first guard ring groove 161 surrounding the periphery of the cell array region may be shown in fig. 3 (1).

Referring to fig. 14, fig. 14 is a schematic cross-sectional structure of a second guard ring trench 162 formed around the periphery of the cell array region by etching the middle region based on the second etching window according to the embodiment of the present utility model. The second guard ring groove 162 and the first guard ring groove 161 have different depths, and it should be noted that the second guard ring groove 162 may be located at the periphery of the first guard ring groove 161, or the first guard ring groove 161 may be located at the periphery of the second guard ring groove 162. As another example, forming the second guard ring trench 162 around the periphery of the cell array region may include: a plurality of second guard ring trenches 162 are formed around the periphery of the cell array region, wherein the plurality of second guard ring trenches 162 extend to different depths in a direction perpendicular to the substrate. By providing at least one first guard ring groove 161 and a second guard ring groove 162 having a different depth from the first guard ring groove, it is possible to further improve the physical isolation effect between the cell array region and the peripheral circuit region on the basis of supporting the cell array region structure, and to avoid current leakage.

In the method for manufacturing a semiconductor device according to another embodiment of the present utility model, at least one first etching window may be formed in the middle region by patterning the photoresist layer, a first guard ring trench 161 surrounding the periphery of the cell array region may be formed based on the first etching window, and a second etching window may be formed in the middle region, and a second guard ring trench 162 surrounding the periphery of the cell array region may be formed based on the second etching window, wherein the second guard ring trench 162 has a different depth from the first guard ring trench 161. The method can achieve the same advantages as those of the first embodiment, and can further improve the physical isolation effect between the cell array region and the peripheral circuit region, avoid current leakage, and greatly improve the performance of the semiconductor device by forming at least one first guard ring trench 161 and a second guard ring trench 162 having different depths from the first guard ring trench in the middle region between the cell array region and the peripheral circuit region.

Based on the method for manufacturing a semiconductor device provided by the embodiment of the present utility model, on the other hand, the present utility model further provides a semiconductor device correspondingly, and please refer to embodiment three specifically.

Example III

Referring to fig. 12, fig. 12 is a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present utility model, which includes:

the substrate 10, the substrate 10 includes a cell array region, a peripheral circuit region, and an intermediate region between the cell array region and the peripheral circuit region.

A stacked structure is formed on the substrate 10, the stacked structure includes a plurality of capacitor structures and a guard ring structure 17, wherein the plurality of capacitor structures are formed on the cell array region, and a support structure is formed between at least part of adjacent capacitor structures, and the support structure includes a first support structure 12 and a second support layer 18; guard ring structure 17 is formed on the middle region and surrounds the capacitor structure on the cell array region.

The guard ring structure 17 may include a plurality of guard rings extending in a direction perpendicular to the substrate 10, and the extending depths are different. As an example, a plurality of guard rings extend in a direction perpendicular to the substrate 10, wherein a bottom surface of at least one guard ring is in contact with an upper surface of the substrate 10 of the semiconductor device.

As an example, in an embodiment of the present utility model, the capacitor structure may include:

a lower electrode 19;

a first support structure 12 and a second support layer 18, wherein the first support structure 12 and the second support layer 18 support at least a portion of the outer side wall of the lower electrode 19, the first support structure 12 and the second support layer 18 being disposed at different heights of the outer side wall of the lower electrode 19;

a capacitance dielectric layer 21, the capacitance dielectric layer 21 covering the lower electrode 19, the second support layer 18 and the upper surface of the cell array region substrate;

an upper electrode 22, the upper electrode 22 covering the capacitor dielectric layer 21.

In an embodiment of the present utility model, the first support structure 12 may include a plurality of sub-support layers and an insulating medium layer between the sub-support layers, and stability of the lower electrode may be improved by providing the plurality of sub-support layers.

As another example, the capacitive structure may further include: a metal layer 23 on the upper electrode 22. Specifically, the metal layer 23 may be tungsten.

As another example, the semiconductor device may further include: an ONONO structure consisting of a first dielectric layer 11, a first support structure 12, a second dielectric layer 13, a second support layer 18 and an oxide layer 24 is located on the substrate 10 in the peripheral circuit region. The ONONO structure can meet the height requirement of the peripheral circuit region and reduce the height difference between the cell array region and the peripheral circuit region.

In other embodiments of the present utility model, the capacitor dielectric layer 21 may also cover the guard ring structure 17 and at least part of the upper surface of the second support layer 18 in the peripheral circuit region.

The above is a semiconductor device provided in the embodiment of the utility model, which includes a substrate 10, the substrate 10 includes a cell array region, a peripheral circuit region and an intermediate region located between the peripheral circuit regions of the cell array region, a stacked structure is formed on the substrate 10, the stacked structure includes a plurality of capacitor structures and a guard ring structure 17, wherein the plurality of capacitor structures are formed on the cell array region, a support structure is provided between at least part of adjacent capacitor structures, and the support structure includes a first support structure 12 and a second support layer 18; guard ring structure 17 is formed on the middle region and surrounds the capacitor structure on the cell array region. The guard ring structure 17 is arranged in the middle area, so that the electrode structure of the cell array area can be supported, the toppling of the lower electrode 19 is avoided, the stability of the structure is improved, and meanwhile, the physical isolation effect on the cell array area and the peripheral circuit area can be achieved, the current leakage is avoided, and the performance of the semiconductor device is greatly improved.

Although the embodiments of the present utility model are disclosed above, the embodiments are only used for the convenience of understanding the present utility model, and are not intended to limit the present utility model. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device of claim 1, wherein the guard ring structure comprises a plurality of guard rings extending in a direction perpendicular to the substrate and having different depths of extension.

3. The semiconductor device according to claim 2, wherein the plurality of guard rings extend in a direction perpendicular to the substrate and have different depths of extension, comprising:

4. The semiconductor device of claim 1, wherein a stacked structure is formed on the substrate, the stacked structure comprising a plurality of capacitor structures and a guard ring structure, the capacitor structures comprising:

a lower electrode;

and the upper electrode covers the capacitance dielectric layer.

5. The semiconductor device of claim 4, wherein the capacitive dielectric layer further covers the guard ring structure and at least a portion of an upper surface of the second support layer in the peripheral circuit region.

6. The semiconductor device of claim 5, wherein the upper electrode covers the capacitive dielectric layer comprises: the upper electrode partially or completely covers the capacitive dielectric layer.

7. The semiconductor device of claim 1, wherein the first support structure comprises a plurality of sub-support layers and an insulating dielectric layer between each of the sub-support layers.

8. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: and the ONONO structure is positioned on the substrate of the peripheral circuit region and consists of a first dielectric layer, the first supporting structure, a second dielectric layer, the second supporting layer and an oxide layer.