KR20090014635A - Oscillator for self refresh - Google Patents

Oscillator for self refresh Download PDF

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Publication number
KR20090014635A
KR20090014635A KR1020070078715A KR20070078715A KR20090014635A KR 20090014635 A KR20090014635 A KR 20090014635A KR 1020070078715 A KR1020070078715 A KR 1020070078715A KR 20070078715 A KR20070078715 A KR 20070078715A KR 20090014635 A KR20090014635 A KR 20090014635A
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KR
South Korea
Prior art keywords
voltage
signal
oscillator
self refresh
output
Prior art date
Application number
KR1020070078715A
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Korean (ko)
Inventor
이인재
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070078715A priority Critical patent/KR20090014635A/en
Publication of KR20090014635A publication Critical patent/KR20090014635A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

The present invention includes a voltage level detector for detecting and outputting a voltage level of a core voltage, a controller for outputting a control signal in response to an output signal of the voltage level detector, and an oscillator for generating a pulse signal in response to the control signal. do.

Description

Self-Refreshing Oscillator {OSCILLATOR FOR SELF REFRESH}

The present invention relates to a semiconductor memory device, and more particularly, to a self refresh oscillator.

The self refresh oscillator determines the self refresh cycle accordingly to correspond to the low voltage characteristics in the DRAM. The operation according to the set period is to preserve the data of the cell.

1 is a block diagram of a self refresh oscillator according to the prior art, and FIG. 1 is a circuit diagram of a self refresh oscillator according to the prior art.

As shown in Fig. 1 and Fig. 2, the prior art self refresh oscillator includes a control unit 100 for outputting control signals CS1 and CS2 in response to the self refresh signal SREF, and the control signal CS1. , Oscillator 200 generating a pulse signal in response to CS2).

The control signals CS1 and CS2 output from the controller 100 act to apply the core voltage and the ground voltage as bias to the oscillator, respectively, so that the period can be changed by changing the voltage level when a periodic change is required.

That is, when the control signal CS2 output from the controller 100 is lowered and the control signal CS1 is increased, the period is set to be faster. This is the principle that the period is changed by changing the Vgs of the MOSs of the oscillator 200. In the case of the control signal CS1 voltage, when the core voltage is lowered by Va, the control signal CS1 voltage is also lowered by Va, and the Vgs applied to the NMOS0 to NMOSx are reduced by Va. In conjunction with this, the period also changes correspondingly.

The self-refreshing oscillator according to an embodiment of the present invention includes a voltage level detector for detecting and outputting a voltage level of a core voltage, a controller for outputting a control signal in response to an output signal of the voltage level detector, and a response to the control signal. Oscillator to generate a pulse signal.

In addition, the self refresh oscillator according to another embodiment of the present invention includes a voltage level detector for detecting and outputting a voltage level of the core voltage in response to the self refresh signal, and a first control signal in response to an output signal of the voltage level detector. A first control signal output unit for outputting a first control signal to be output, a second control signal output unit for outputting a second control signal in response to the self refresh signal, and in response to the first and second control signals An oscillator for generating a pulse signal.

3 is a block diagram of a self refresh oscillator according to the present invention, and FIG. 4 is a circuit diagram of a self refresh oscillator according to the present invention.

As illustrated in FIG. 3, the present invention provides a voltage level detector 10 for detecting and outputting a voltage level of the core voltage VCORE, and a control signal in response to an output signal of the voltage level detector 10. A control unit 20 for outputting (CS1, CS2), and an oscillator 30 for generating a pulse signal in response to the control signal.

As shown in FIG. 4, the voltage level detection unit 10 outputs a pull-up element P1 for driving pull-up in response to a self-refresh signal SREF and an output from the pull-up element P1. And a voltage divider configured by connecting the resistors R1 and R2 in series so as to divide the core voltage VCORE.

The control unit 20 may include a first control signal output unit 21 outputting a first control signal CS1 in response to the output signal V1 of the voltage level detection unit 10, and the voltage level detection unit 10. And a second control signal output unit 22 outputting a second control signal CS2 in response to an output signal of the control signal CS2.

Here, the first control signal CS1 is a control signal for applying a ground voltage signal to the oscillator 30, and the second control signal CS2 is a control for applying a core voltage to the oscillator 30. It is a signal.

The first control signal output unit 21 may include a pull-up driving unit P2 for pull-up driving in response to the self refresh signal SREF, and an output signal V1 of the voltage level detection unit 10. A pull-down driving unit N1 for pull-down driving and voltage distribution units R3 and R4 for voltage distribution of the core voltage output from the pull-up driving unit P2.

The second control signal output unit 22 divides the voltage between the pull-up driving unit P3 for pull-up driving in response to the self refresh signal SREF and the core voltage output from the pull-up driving unit P3. And voltage dividers R5, R6, and R7.

The oscillator 30 includes a bias applying unit 31 for applying a core voltage VCORE and a ground voltage VSS in response to the control signals CS1 and CS2 output from the controller 20, and the bias applying unit. The inverter chain 32 receives the core voltage VCORE and the ground voltage VSS from 31 and outputs a predetermined pulse signal having a predetermined period.

The oscillator 30 buffers a pulse signal output from the inverter chain 32 and a level fixing part 33 for controlling the signal OSC_OUT output in response to the self refresh signal SREF to be fixed at a predetermined level. A buffer unit 34 is included.

The operation of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

As shown in FIGS. 3 and 4, when the self refresh signal SREF becomes High to Low, the voltage level detector 10 responds to the self refresh signal SREF to provide a voltage level of the core voltage VCORE. Is detected and output (V1).

Then, the first control signal output unit 21 is a first for applying the ground voltage signal to the bias applying unit 31 of the oscillator 30 in response to the output signal V1 of the voltage level detector 10. The control signal CS1 is output.

The second control signal output unit 22 supplies a second control signal CS2 for applying a core voltage signal to the bias applying unit 31 of the oscillator 30 in response to the self refresh signal SREF. Output

In this way, when a bias is applied to the inverter chain 32 of the oscillator 30, the oscillator 30 starts operation and outputs a pulse signal OSC_OUT of a predetermined period.

Here, the voltage signal V1 that is divided by the core voltage voltage by the resistors R1 and R2 of the voltage level detector 10 is output in the linear region of the NMOS N1 of the first control scene output unit 21. To work. As a result, the first control signal CS1 has its potential set to a value changed by the current change of the NMOS N1.

The reason for this is that at low voltage, the voltage level of the signal V1 is low, so that the current of the NMOS N1 is relatively small, so that the first control signal CS1 is not lowered as the core voltage is lowered. On the contrary, since the current of the NMOS N1 increases as the core voltage increases, the first control signal CS1 does not increase as the core voltage increases. By using this, the following operation can be performed.

First, when the core voltage is lowered by Va, the signal V1 is lowered by Va. However, since the current of the NMOS N1 decreases, the first control signal CS1 does not decrease as much as Va, but relatively low, so that the current of NMOS0 to NMOSx applying the ground voltage to the oscillator changes little, and the second control signal ( The potential of CS2) also changes less. This means that even if the core voltage goes down a lot, the cycles change less because Vgs changes less.

When the core voltage is increased by Va, the signal V1 is increased by Va. However, since the current of the NMOS N1 increases because the current of the NMOS N1 increases, the first control signal CS1 does not increase as much as Va. Therefore, the current of the NMOS0 to NMOSx that applies the ground voltage to the oscillator changes little and the second control signal ( The potential of CS2) also changes less. This means that even if the core voltage increases a lot, the Vgs changes less so the period changes.

As described above, the present invention can reduce the current consumption by supplying a pulse signal having a constant period in spite of a high voltage displacement to prevent frequent self refresh by the pulse signal having a short period.

1 is a block diagram of a self refresh oscillator according to the prior art.

2 is a circuit diagram of a self refresh oscillator according to the prior art.

3 is a block diagram of a self refresh oscillator according to the present invention.

4 is a circuit diagram of a self refresh oscillator according to the present invention.

Claims (27)

A voltage level detector for detecting and outputting a voltage level of the core voltage; A controller for outputting a control signal in response to an output signal of the voltage level detector; An oscillator for generating a pulse signal in response to the control signal; Self refresh oscillator comprising a. The method of claim 1, The voltage level detector is configured to drive in response to a self refresh signal; A voltage divider configured to voltage divide the core voltage output from the driver; Self refresh oscillator comprising a. The method of claim 2, And the driving unit pull-up driving the pull-up in response to the self-refresh signal. The method of claim 2, And the voltage divider is configured by connecting a plurality of resistors in series so as to divide the core voltage output from the driver. The method of claim 1, The controller may include a first control signal output unit configured to output a first control signal in response to an output signal of the voltage level detector; A second control signal output unit outputting a second control signal in response to an output signal of the voltage level detection unit; Self refresh oscillator comprising a. The method of claim 5, wherein The first control signal is a control signal for applying a ground voltage signal to the oscillator, and the second control signal is a control signal for applying a core voltage to the oscillator. The method of claim 5, wherein A first pull-up driving unit configured to pull-up driving in response to a self refresh signal; A pull-down driving unit for pull-down driving in response to an output signal of the voltage level detection unit; A voltage divider configured to voltage divide the core voltage output from the pull-up driver; Self refresh oscillator comprising a. The method of claim 7, wherein And the voltage divider is configured by connecting a plurality of resistors in series so as to divide the core voltage output from the driver. The method of claim 5, wherein The second control signal output unit includes a pull-up driving unit for pull-up driving in response to a self refresh signal; A voltage divider configured to voltage divide the core voltage output from the pull-up driver; Self refresh oscillator comprising a. The method of claim 8, And the voltage divider is configured by connecting a plurality of resistors in series so as to divide the core voltage output from the driver. The method of claim 1, The oscillator may include a bias applying unit configured to apply a core voltage and a ground voltage in response to a control signal output from the controller; An inverter chain receiving a core voltage and a ground voltage from the bias applying unit and outputting a predetermined pulse signal having a predetermined period; Self refresh oscillator comprising. The method of claim 11, The oscillator may include a level fixing unit controlling the output signal in response to the self refresh signal to be fixed at a predetermined level; Self refresh oscillator further comprising. The method of claim 12, The level fixing unit may include a pull-down device configured to pull-down drive in response to a self refresh signal; Self refresh oscillator comprising a. The method of claim 11, The oscillator further comprises a buffer for buffering the output pulse signal; self refresh oscillator further comprising. A voltage level detector for detecting and outputting a voltage level of the core voltage in response to the self refresh signal; A first control signal output unit outputting a first control signal outputting a first control signal in response to an output signal of the voltage level detection unit; A second control signal output unit outputting a second control signal in response to the self refresh signal; An oscillator for generating a pulse signal in response to the first and second control signals; Self refresh oscillator comprising a. The method of claim 15, The voltage level detector is configured to drive in response to a self refresh signal; A voltage divider configured to voltage divide the core voltage output from the driver; Self refresh oscillator comprising a. The method of claim 16, And the driving unit pull-up driving the pull-up in response to the self-refresh signal. The method of claim 16, And the voltage divider is configured by connecting a plurality of resistors in series so as to divide the core voltage output from the driver. The method of claim 15, The first control signal is a control signal for applying a ground voltage signal to the oscillator, and the second control signal is a control signal for applying a core voltage to the oscillator. The method of claim 15, A first pull-up driving unit configured to pull-up driving in response to a self refresh signal; A pull-down driving unit for pull-down driving in response to an output signal of the voltage level detection unit; A voltage divider configured to voltage divide the core voltage output from the pull-up driver; Self refresh oscillator comprising a. The method of claim 20, And the voltage divider is configured by connecting a plurality of resistors in series so as to divide the core voltage output from the driver. The method of claim 15, The second control signal output unit includes a pull-up driving unit for pull-up driving in response to a self refresh signal; A voltage divider configured to voltage divide the core voltage output from the pull-up driver; Self refresh oscillator comprising a. The method of claim 22, And the voltage divider is configured by connecting a plurality of resistors in series so as to divide the core voltage output from the driver. The method of claim 15, The oscillator may include a bias applying unit configured to apply a core voltage and a ground voltage in response to a control signal output from the controller; An inverter chain receiving a core voltage and a ground voltage from the bias applying unit and outputting a predetermined pulse signal having a predetermined period; Self refresh oscillator comprising. The method of claim 24, The oscillator may include a level fixing unit controlling the output signal in response to the self refresh signal to be fixed at a predetermined level; Self refresh oscillator further comprising. The method of claim 25, The level fixing unit may include a pull-down device configured to pull-down drive in response to a self refresh signal; Self refresh oscillator comprising a. The method of claim 24, The oscillator further comprises a buffer for buffering the output pulse signal; self refresh oscillator further comprising.
KR1020070078715A 2007-08-06 2007-08-06 Oscillator for self refresh KR20090014635A (en)

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KR1020070078715A KR20090014635A (en) 2007-08-06 2007-08-06 Oscillator for self refresh

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Application Number Priority Date Filing Date Title
KR1020070078715A KR20090014635A (en) 2007-08-06 2007-08-06 Oscillator for self refresh

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