KR20090014011A - Phase change ram device and method of manufacturing the same - Google Patents

Abstract

A phase change ram device and method of manufacturing the same is provided to reduce parasitic capacitance while reducing dynamic contact resistance of the bit line by forming the bit line to be contacted on the phase change film directly. In a phase change ram device and method of manufacturing the same, an N+ bulk region(104) of the line type is formed within the surface of the semiconductor substrate. A plurality of PN diodes(106) is formed on the N+ bulk region apart from each other, and a phase change film(108) is formed on the PN diode. The bit line(BL) is contacted with the phase change film directly and it is extended to be perpendicular to the N+ bulk region. The word line(WL) is contacted with the N+ bulk region and it is extended to the parallel to direction with the N+ bulk region.

Description

Phase change memory device and its manufacturing method {PHASE CHANGE RAM DEVICE AND METHOD OF MANUFACTURING THE SAME}

1A to 1F are process plan views illustrating a method of manufacturing a phase change memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a phase change memory device according to an embodiment of the present invention, corresponding to line A-A 'in FIG. 1F; FIG.

3 is a plan view for explaining a phase change memory device according to another embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 active region

104: N ⁺ bulk region 106: PN diode

108: phase change film 110: contact plug

BL: bit line 112: insulating film

WL: word line

The present invention relates to a phase change memory device and a method of manufacturing the same, and more particularly, to a phase change memory device that can increase the sensing margin (Sensing Margin) by reducing the parasitic capacitance (Parasitic Capacitance) and a manufacturing method thereof. .

The memory device is a volatile random access memory (RAM) device that loses input information when the power is cut off, and a read only memory (ROM) device that maintains the storage state of the input information even when the power is cut off. It is largely divided. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM is a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration because the electrode surface area must be increased. In addition, the flash memory device requires an operation voltage higher than a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies have been conducted to develop a new memory device having the characteristics of the nonvolatile memory device and having a simple structure. For example, recently, a phase change RAM device has been developed. Was proposed. In particular, a method of applying a vertical PN diode has been proposed in the manufacture of a phase change memory device of 512 Mb or more. The vertical PN diode is formed on a line type N ⁺ bulk region formed through an ion implantation process on a surface of a bar type active region.

In the phase change memory device, a phase change film interposed between the electrodes through a current flow between the lower electrode and the upper electrode is changed from a crystal state to an amorphous state. It is a memory element for determining information stored in a cell by using a resistance difference.

In detail, the phase change memory device uses a chalcogenide film as a phase change film. The chalcogenide film is a compound film made of germanium (Ge), stevilium (Sb) and tellurium (Te), and is amorphous by heat generated by an applied current, that is, Joule heat. A phase change occurs between the state and the crystalline state. At this time, since the specific resistance of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state, the current flowing through the phase change film in the read mode is sensed so that the information stored in the phase change memory cell is logical '1' or It is determined whether the logic is '0'.

On the other hand, in such a phase-change memory device, the phase change film becomes crystalline from amorphous state to reset, and conversely, from amorphous state to crystalline state is called set, in terms of power consumption and operation speed The smaller the magnitude of the current for the reset / set (programming), the better. Therefore, by making the contact area between the phase change film and the electrode as small as possible, the current density at the contact surface between the two materials should be increased to lower the current required for the phase change.

However, in the above-described prior art, the phase change layer and the upper electrode formed on the lower electrode are formed through one etching process. As the design rule of the cell decreases, the edge portion of the phase change layer is reduced. This over-etching causes loss.

As a result, a volume change occurs at the contact interface between the phase change film and the lower electrode to electrically open between the phase change film and the lower electrode, thereby widening the current distribution necessary for the phase change. The parasitic capacitance increases, which reduces the sensing margin.

The present invention provides a phase change memory device capable of reducing parasitic capacitance and a method of manufacturing the same.

In addition, the present invention provides a phase change memory device and a method of manufacturing the same that can increase the sensing margin.

A phase change memory device according to an embodiment of the present invention includes a line type N ⁺ bulk region formed in a surface of a semiconductor substrate; A plurality of PN diodes spaced apart on the N ⁺ bulk region; A phase change film formed on the PN diode; A bit line formed in direct contact with the phase change layer and extending in a direction perpendicular to the N ⁺ bulk region; And word lines formed to extend in the upper bit line in a direction parallel to the bulk region and the N ⁺ contact, and also as well as the N ⁺ bulk region; includes.

Here, the phase change film is formed in a pillar shape.

The phase change film is formed on the PN diode to contact a portion of the PN diode.

The phase change film is formed to contact the central portion of the PN diode.

The bit line is formed such that the width at the top of the N ⁺ bulk region is smaller than the width at the other portion.

It formed on the N ⁺ bulk region, and further comprising a contact plug for the contact with the N ⁺ bulk region and the word line.

The phase change film is formed to be in direct contact with the PN diode.

In addition, a method of manufacturing a phase change memory device according to an embodiment of the present invention, forming a line type N ⁺ bulk region in the surface of the semiconductor substrate; Forming a plurality of PN diodes spaced apart on the N ⁺ bulk region; Forming a phase change film on the PN diode; Forming a bit line in direct contact with the phase change layer and extending in a direction perpendicular to the N ⁺ bulk region; And the addition and also the N ⁺ bulk region and the contact to the upper bit line forming a word line extending in a direction parallel to the N ⁺ bulk region; and a.

Here, the phase change film is formed in a pillar shape.

The phase change layer is formed on the PN diode to contact a portion of the PN diode.

The phase change layer is formed to contact the central portion of the PN diode.

The bit line is formed such that the width at the top of the N ⁺ bulk region is smaller than the width at the other portions.

Further includes; after forming the bit lines, and, before the forming of the word lines, on said N ⁺ bulk region to form a contact plug that contacts the N ⁺ bulk region and the word line .

The phase change film is formed to be in direct contact with the PN diode.

In addition, the phase change memory device according to the present invention comprises: a phase change memory cell formed in an active region of a semiconductor substrate; A bit line formed in contact with the phase change memory cell and extending in a direction perpendicular to the active area; And a word line formed on the bit line and extending in a direction parallel to the active region, wherein the bit line is formed such that a portion in contact with the phase change memory cell has a narrower width than the other portions. .

Here, the bit lines are laid out at right angles at boundaries where the widths of the bit lines vary.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to an embodiment of the present invention, a phase change film is directly formed on a vertical PN diode, and then the bit line is directly formed without forming an upper electrode and an upper electrode contact for electrical contact between the phase change film and the bit line. Is formed to form an electrical contact between the phase change film and the bit line.

In this case, the bit line and the phase change layer are in direct contact with each other, thereby reducing the dynamic contact resistance. In addition, the present invention can reduce the parasitic capacitance because no conductive pattern is formed other than the phase change layer under the bit line, thereby increasing the sensing margin.

1A to 1F are plan views of processes for explaining a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, after defining active regions 102 of a bar type spaced apart from each other in a semiconductor substrate 100, an ion implantation process is performed on the active regions 102 to determine the active regions 102. Form a line type N ⁺ bulk region 104 in the surface.

Referring to FIG. 1B, a plurality of vertical PN diodes 106 are formed on the N ⁺ bulk regions 104. The PN diode 106 is preferably formed in a cylindrical shape having a predetermined interval on the N + bulk region 104, wherein the PN diode 106 has a diameter that is equal to the interval between the PN diode 106 Form the same, or different.

Referring to FIG. 1C, a phase change layer 108 is formed on the PN diode 106 in contact with a portion of the PN diode 106, preferably a central portion of the PN diode 106. The phase change layer 108 is formed in a pillar shape having a diameter of about 100 nm or less, and is formed to be in direct contact with the PN diode 106.

In an embodiment, the phase change film 108 is formed to be in direct contact with the central portion of the PN diode 106 without a lower electrode so that a phase change occurs in the central portion of the PN diode 106. The conventional problem of electrically opening between the change film 108 and the lower electrode can be solved. Accordingly, the present invention can reduce the current distribution required for the phase change, thereby reducing the parasitic capacitance to ensure a sensing margin.

In addition, the present invention forms the phase change layer 108 by filling a phase change material in the contact hole, in which case, the programming current can be lowered relative to the conventional stack structure. In order to further reduce the programming current, it is preferable to form a smaller size of the contact hole.

Referring to FIG. 1D, a bit line BL is formed on the phase change layer 108 extending in a direction perpendicular to the active region 102. The bit line BL is formed to have a predetermined width on the semiconductor substrate 100 including the active region 102 and is in direct contact with the phase change layer 108.

In this case, the width of the bit line BL is formed to be the same as or different from the interval between the bit lines BL, and the bit line BL is formed to overlap the phase change layer 108 to about 100 nm or less. It is preferable.

The present invention can reduce the dynamic contact resistance between the phase change layer 108 and the bit line BL by forming the bit line BL in direct contact with the phase change layer 108. have. In addition, since an upper electrode, a contact, etc. are not formed below the bit line BL, the parasitic capacitance of the bit line BL may be reduced, thereby increasing the sensing margin of the phase change memory device. In addition, the present invention has an advantage that the bit line BL is directly formed on the phase change layer 110, so that the height of the chip can be lowered, which is advantageous even when packaged.

Referring to FIG. 1E, after forming an insulating film (not shown) on the semiconductor substrate 100 on which the bit line BL is formed, a contact hole for etching the insulating film to expose the N ⁺ bulk region 104 is formed. Form. Then, the contact hole is filled with a conductive film to form a contact plug 110 on the N ⁺ bulk region 104.

The contact plug 110 electrically connects the vertical PN diode 106 and a word line to be subsequently formed, and the plurality of vertical PN diodes 106 formed on the N ⁺ bulk region 104. It is preferable to form between.

In this case, the contact plug 110 may have the same size as the vertical PN diode 106 or may have a different size. In addition, the contact plug 110 may have a spacing between the contact plug 110 and the closest vertical PN diode 106 equal to or different from that of the vertical PN diode 106.

Referring to FIG. 1F, a word line WL contacting the N ⁺ bulk region 104 and extending in a direction parallel to the N ⁺ bulk region 104 on the insulating layer on which the contact plug 110 is formed. To form. The N ⁺ bulk region 104 and the word line WL are contacted through the contact plug 110, and the width between the width of the word line WL and the word line WL is equal to or different from each other. It may be formed.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the phase change memory device according to the exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a phase change memory device according to an exemplary embodiment of the present invention, corresponding to line A-A 'of FIG. 1F.

As shown in FIG. 2, a line type N ⁺ bulk region 104 is formed in the surface of the active region of the semiconductor substrate 100, and a plurality of vertical PN diodes are spaced apart on the N ⁺ bulk region 104. 106 are formed. A pillar type phase change layer 108 is formed on the vertical PN diode 106 to contact a portion of the PN diode 106, preferably a central portion of the PN diode 106. .

Since the phase change layer 108 is formed to be in direct contact with the central portion of the vertical PN diode 106 without a lower electrode, it is possible to prevent the phase change layer 108 and the lower electrode from being electrically opened. And, through this, the present invention can reduce the parasitic capacitance to secure the sensing margin.

Subsequently, the phase-change film 108 onto N ⁺ bulk region (104) the bit line (BL) extending in a direction perpendicular to this is formed, and the bit line (BL) above the upper N ⁺ bulk region ( In addition to contacting 104, a word line WL is formed extending in a direction parallel to the N ⁺ bulk region 104. It said bit line (BL) is formed to have a predetermined width, the contact plug 110 for contact with the N ⁺ bulk region (104) formed on the word line (WL) and the N ⁺ bulk region (104) is formed.

Since the bit line BL is formed to be in direct contact with the phase change layer 108 without an upper electrode, the present invention provides a dynamic contact resistance between the phase change layer 108 and the bit line BL. Can be reduced. Therefore, the present invention can reduce the parasitic capacitance, thereby increasing the sensing margin of the phase change memory device.

Meanwhile, the above-described embodiment of the present invention reduces the parasitic capacitance and increases the sensing margin by forming a bit line having a constant width on the semiconductor substrate including the active region. The parasitic capacitance can be further reduced by forming a bit line having a narrower width than in other regions.

3 is a plan view illustrating a phase change memory device according to another exemplary embodiment of the present invention.

As shown in FIG. 3, a line type N ⁺ bulk region 104 is formed in the surface of the active region 102 of the semiconductor substrate 100 and a plurality of vertical spaced apart on the N ⁺ bulk region 104. Type PN diodes 106 are formed. A pillar type phase change layer 108 is formed on the vertical PN diode 106 to contact a portion of the PN diode 106, preferably a central portion of the PN diode 106.

Subsequently, a bit line BL extending in a direction perpendicular to the N ⁺ bulk region 104 is formed on the phase change layer 108. The bit line BL is formed to have a narrower width on the active region 102 than in the other regions. In this case, the bit line BL may be laid out in an acute angle or an obtuse shape at a boundary portion where the width of the bit line BL varies, but it is preferable that the bit line BL is laid out in a right angle shape.

In this case, a portion where the bit line BL overlaps with a subsequent word line may be reduced to further reduce the parasitic capacitance of the bit line BL, thereby further increasing the sensing margin of the phase change memory device. It can increase effectively.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, according to the present invention, the bit line may be directly contacted on the phase change layer, thereby reducing the dynamic contact resistance of the bit line and reducing the parasitic capacitance. Therefore, the present invention can increase the sensing margin of the phase change memory device.

Claims (18)

A line type N ⁺ bulk region formed in the surface of the semiconductor substrate; A plurality of PN diodes spaced apart on the N ⁺ bulk region; A phase change film formed on the PN diode; A bit line formed in direct contact with the phase change layer and extending in a direction perpendicular to the N ⁺ bulk region; And The bit line also the N ⁺ bulk region and in contact with the upper as well as the word lines are formed so as to extend in a direction parallel to the N ⁺ bulk region; Phase change memory device comprising a. The method of claim 1, And the phase change layer is formed in a pillar shape. The method of claim 1, And the phase change film is formed to contact a portion of the PN diode on the PN diode. The method of claim 3, wherein And the phase change film is formed to contact the central portion of the PN diode. The method of claim 1, And the bit line has a width at an upper portion of the N ⁺ bulk region narrower than a width at the other portion. The method of claim 5, wherein And the bit line is laid out at right angles at a boundary portion where the width of the bit line varies. The method of claim 1, The phase change memory device according to claim 1, further comprising a contact plug is formed on the N ⁺ bulk region, and the word line to contact the N ⁺ bulk region. The method of claim 1, And the phase change film is formed to be in direct contact with the PN diode. Forming a line type N ⁺ bulk region within the surface of the semiconductor substrate; Forming a plurality of PN diodes spaced apart on the N ⁺ bulk region; Forming a phase change film on the PN diode; Forming a bit line in direct contact with the phase change layer and extending in a direction perpendicular to the N ⁺ bulk region; And To the bit line as well as the upper and also the N ⁺ bulk region and the contact to form a word line extending in a direction parallel to the N ⁺ bulk region; Method of manufacturing a phase change memory device comprising a. The method of claim 9, And the phase change film is formed in a pillar shape. The method of claim 9, And the phase change film is formed on the PN diode to be in contact with a portion of the PN diode. The method of claim 11, And the phase change film is formed to contact the central portion of the PN diode. The method of claim 9, And the bit line is formed to have a width at an upper portion of the N ⁺ bulk region narrower than a width at other portions. The method of claim 13, And the bit line is laid out at right angles at a boundary portion where the width of the bit line varies. The method of claim 9, After forming the bit line, and before forming the word line, Comprising: on the N ⁺ bulk region and the word line form a contact plug that contacts the N ⁺ bulk region; The method of manufacturing a phase change memory device, characterized in that it further comprises. The method of claim 9, And the phase change film is formed in direct contact with the PN diode. A phase change memory cell formed in an active region of a semiconductor substrate; A bit line formed in contact with the phase change memory cell and extending in a direction perpendicular to the active area; And And a word line formed on the bit line and extending in a direction parallel to the active region. And the bit line is formed such that a portion in contact with the phase change memory cell has a narrower width than the other portions. The method of claim 17, And the bit line is laid out at right angles at a boundary portion where the width of the bit line varies.

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