KR20090013941A - Semiconductor device fabrication installation - Google Patents

Semiconductor device fabrication installation Download PDF

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Publication number
KR20090013941A
KR20090013941A KR1020070078111A KR20070078111A KR20090013941A KR 20090013941 A KR20090013941 A KR 20090013941A KR 1020070078111 A KR1020070078111 A KR 1020070078111A KR 20070078111 A KR20070078111 A KR 20070078111A KR 20090013941 A KR20090013941 A KR 20090013941A
Authority
KR
South Korea
Prior art keywords
substrate
unit
transfer unit
substrate transfer
guide
Prior art date
Application number
KR1020070078111A
Other languages
Korean (ko)
Inventor
최기훈
최중봉
Original Assignee
세메스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세메스 주식회사 filed Critical 세메스 주식회사
Priority to KR1020070078111A priority Critical patent/KR20090013941A/en
Publication of KR20090013941A publication Critical patent/KR20090013941A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67196—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67389—Closed carriers characterised by atmosphere control
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67742—Mechanical parts of transfer devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S414/00—Material or article handling
    • Y10S414/135—Associated with semiconductor wafer handling
    • Y10S414/139—Associated with semiconductor wafer handling including wafer charging or discharging means for vacuum chamber

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Robotics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A semiconductor device fabrication installation is provided to prevent contamination of a wafer mounted a substrate transferring unit due to a particle by installing a fan filter unit on the top of the substrate transferring unit. In a semiconductor device fabrication installation, a substrate is transferred by the substrate transferring unit(35) to the processing part. A main fan filter unit, positioned on the substrate transferring unit, generates the first descending air current in the sliding window of the substrate transferring unit. The substrate transferring unit comprises a pocket unit, a secondary fan filter unit(70), a base body(37), more than one arm(36a). The supplementary fan filter unit comprises the filter and it is positioned on the pocket unit and generates the second descending air current around the pocket unit.

Description

Semiconductor manufacturing equipment {SEMICONDUCTOR DEVICE FABRICATION INSTALLATION}

The present invention relates to a semiconductor manufacturing facility that can reduce contamination of a substrate.

The semiconductor manufacturing process proceeds with various processes applied to a semiconductor substrate or a glass substrate to form an electronic circuit on the semiconductor substrate or the glass substrate.

The photolithography process, which is a typical unit process in the semiconductor manufacturing process, is largely composed of a photoresist coating process, an exposure process, and a developing process. The photoresist coating step is a step of coating the photoresist on the surface of the substrate, and the exposure step is a step of irradiating ultraviolet rays to the substrate after covering the substrate with a mask having a pattern formed thereon. In addition, the developing step is a step of partially removing the photoresist film using a developer, and the photoresist film cured in the exposure process is not removed by the developer so that a photoresist pattern is formed on the substrate.

Facilities for performing the photolithography process include in-line equipment and spinner local equipment. The local facility consists of a process processor consisting of indexer, application, development and bake modules. The indexer is a unit for the purpose of interfacing the user to the wafer and the process module (application modules and bake module). When the cassette is provided to the indexer's load port by the operator (or AGP), the indexer robot The wafer is extracted to transfer the substrate to the substrate transfer apparatus, which is loaded into the process module by the substrate transfer apparatus. When the process is completed for the substrate, the wafer is recovered by the substrate transfer device and stored in the wafer cassette.

However, in the process of moving the substrate transfer apparatus in the vertical and horizontal directions along the transfer guide to load the wafer into the process module, surrounding particles may contaminate the wafer. If the wafer is contaminated by particles, the wiring formed in the semiconductor manufactured from the wafer into the substrate may be shorted or broken to reduce the semiconductor manufacturing yield.

It is an object of the present invention to provide a semiconductor manufacturing facility having a substrate transfer unit that can reduce the contamination of a substrate by particles.

In order to achieve the above object, the semiconductor manufacturing equipment according to the present invention is provided with a substrate processing unit for processing a substrate, a substrate transfer unit for moving within the substrate transfer region and transferring the substrate from the outside to the processing unit side, the substrate comprising a filter And a main fan filter unit provided above the transfer unit and generating a first downdraft in a region to which the substrate transfer unit moves.

The substrate transfer unit may include a base body, at least one arm portion coupled to the base body, a pocket portion coupled to the arm portion and a substrate on which the substrate is placed, and a second descending air flow around the pocket portion. And an auxiliary fan filter unit for generating.

The semiconductor manufacturing equipment according to the present invention is provided with a separate auxiliary fan filter unit on top of the substrate transfer unit, and as a result, contamination of the wafer seated on the substrate transfer unit by particles is reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The objects, features and effects of the present invention described above will be readily understood through embodiments related to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be applied and modified in various forms. Rather, the following embodiments are provided to clarify the technical spirit disclosed by the present invention, and furthermore, to fully convey the technical spirit of the present invention to those skilled in the art having an average knowledge in the field to which the present invention belongs. Therefore, the scope of the present invention should not be construed as limited by the embodiments described below. On the other hand, the drawings presented in conjunction with the following examples are somewhat simplified or exaggerated for clarity, the same reference numerals in the drawings represent the same components.

1 is a plan view of a semiconductor manufacturing facility according to an embodiment of the present invention, and is a side view of the semiconductor manufacturing facility shown in FIG. 1.

1 and 2, the semiconductor manufacturing facility 10 includes a process processor 30, a first indexer 20, and a second indexer 50.

The process processor 30 includes a first processor 31a and a second processor 31b facing the first processor 31a, a substrate transfer unit 35, and a main fan filter unit 60.

Each of the first processor 31a and the second processor 31b is divided into a plurality of layers, and each layer is provided with a processing module 40. For example, a lower processing unit 32a is provided below the first processing unit 31a, and an upper processing unit 32b is provided above the first processing unit 31a.

The processing module 40 is for carrying out the coating process and the developing process. The processing modules include a module for performing an application process, a module for performing wafer cooling, and a photoresist on a wafer surface. A module for applying, and a module for performing a soft bake process may be provided. The module for heating the exposed wafer to a predetermined temperature, the module for cooling the wafer, the developer for the wafer as a module for performing the developing process. A module for removing the exposed area or the reverse area by spraying the light, and a module for performing a hard bake process may be provided.

The substrate transfer unit 35 includes an auxiliary fan filter unit 70 at an upper portion thereof. The substrate transfer unit 35 is positioned between the first processing unit 31a and the second processing unit 31b. 2 is provided with a wafer from the indexer 50 to the processing module 40 side. A more detailed description of the substrate transfer unit 35 is described with reference to FIGS. 3 and 4.

The first indexer 20 and the second indexer 50 are portions for the purpose of interfacing the user with the wafer and the process processor 30.

The first indexer 20 is installed at the front end of the processing unit 30, and includes a first load port 22 on which the cassette C is placed and a first indexer robot 100a. The first indexer robot 100a is responsible for transferring the substrate between the first load port 22 and the first processor 32a.

The second indexer 50 is installed at the rear end of the processing unit 30 in a symmetrical manner with the first indexer 20, the second load port 52 on which the cassette C is placed, and the second indexer. The robot 100b is included. The second indexer robot 100b is responsible for transferring the substrate between the second load port 52 and the second processor 32b.

As described above, since the first indexer robot 100a and the second indexer robot 100b are respectively installed at front and rear ends of the process processor 30, interference between substrate transfers does not occur.

Each of the first indexer robot 100a and the second indexer robot 100b is coupled to a horizontal guide 110 for moving left and right with respect to the ground and a vertical guide 120 for moving up and down with respect to the ground. The second indexer robot 100b has a vertical guide 120 that is relatively longer than the first indexer robot 100a for substrate transfer with the second processor 32b.

Therefore, when a wafer is provided to the cassette C of the first load port 22 by an operator (or AGP), the first indexer robot 100a is a cassette (set in the first load port 22). The substrate is taken out from C), and the substrate is provided to the substrate transfer unit 35 side of the processing unit 30.

In addition, the second indexer robot 100b extracts a wafer provided in the cassette C of the second load port 52 and provides the wafer to the substrate transfer unit 35 side of the processing unit 30. The wafer provided to the substrate transfer unit 35 is loaded into the processing module 40, and the processing is performed on the wafer in the processing module 40, and after the processing is completed on the wafer, the substrate transferring is performed. The wafer is recovered by the unit 35.

3 is a cross-sectional view illustrating a portion taken along line II ′ of FIG. 1, and FIG. 4 is an exploded perspective view of the substrate transfer unit illustrated in FIG. 1.

3 and 4, the substrate transfer unit 35 is provided on the horizontal support 38 coupled with the first transfer guide 80 so that the substrate transfer unit 35 is provided with the first transfer guide 80. ) May move in the first direction D1. In addition, the first transfer guide 80 is coupled to the second transfer guide 90, and as a result, the substrate transfer unit 35 is in the second direction D2 in which the second transfer guide 90 extends. I can move it.

Meanwhile, a main fan filter unit 60 is provided above the substrate transfer unit 35. The main fan filter unit 60 includes a fan and a filter therein, and primarily purifies the air flowing into the main fan filter unit 60 from the outside, and generates a first downdraft DF1.

The substrate transfer unit 35 includes a base body 37, a first arm portion 36a, a first pocket portion 39a, a second arm portion 36b, a second pocket portion 39b, a cover portion 95 and Auxiliary fan filter unit 70 is included.

The base body 37 is a part of the substrate transfer unit 35 that engages with the horizontal support 38, and the first arm 36a and the second arm 36b are each the base body 37. In combination with the handle, the wafer is handled to transfer the wafer to the correct position. In addition, one end of the first arm portion 36a is coupled to the first pocket portion 39a on which the first wafer W1 is placed, and one end of the second arm portion 36b is formed of the second wafer W2. Engage with the second pocket portion 39b to be laid.

The auxiliary fan filter unit 70 generates a second downward air flow DF2 around the wafers W1 and W2 respectively disposed on the first pocket portion 39a and the second pocket portion 39b. The auxiliary fan filter unit 70 includes a fan and a filter (not shown) therein to purify the first downdraft DF1 generated from the main fan filter unit 60 once more, and the first The second falling air stream DF2 having a larger moving speed than the first falling air stream DF1 is generated using the falling air stream DF1.

The cover part 95 has an upper end 91 and a side wall 92 extending from the upper end 91 to be coupled to the auxiliary fan filter unit 70. The cover part 95 isolates the first downdraft DF1 and the second downdraft DF2 from each other so that the air pressure is maintained around the wafers W1 and W2 more than the periphery of the cover part.

Therefore, the inner region of the cover portion 95 is kept cleaner than the cover portion 95 outer region by the auxiliary fan filter unit 70 and the cover portion 95, and as a result, the substrate Contamination of the wafer seated on the transfer unit 35 by the particles is reduced.

Although described with reference to the above embodiments, those skilled in the art can be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

1 is a plan view of a semiconductor manufacturing facility according to an embodiment of the present invention.

FIG. 2 is a side view of the semiconductor manufacturing facility shown in FIG. 1.

3 is a cross-sectional view illustrating a portion taken along line II ′ of FIG. 1.

4 is an exploded perspective view of the substrate transfer unit shown in FIG. 1.

* Description of the symbols for the main parts of the drawings *

10-semiconductor manufacturing equipment 20-primary indexer

22-1st load port 30-Process treatment part

31a-first processor 31b-second processor

32a-lower part 32b-upper part

35-substrate transfer unit 36a-first arm

36b-2nd arm 37-Base body

38-horizontal support 39a-first pocket

39b-second pocket 40-processing module

50-Second Indexer 52-Second Loadport

60-main fan filter unit 70-auxiliary fan filter unit

80-1st transport guide 90-2nd transport guide

95-Cover 100a-First Indexer Robot

100b-2nd indexer robot C-cassette

Claims (7)

A process processor which processes the substrate; A substrate transfer unit for transferring a substrate provided from the outside to the process processor; And A main fan filter unit provided with a filter on the substrate transfer unit and generating a first downdraft in a region where the substrate transfer unit moves; The substrate transfer unit, Base body; At least one arm coupled to the base body; A pocket part coupled to the arm part and on which the substrate is placed; And And an auxiliary fan filter unit provided on the pocket part and having a filter to generate a second air flow around the pocket part. The method of claim 1, wherein the substrate transfer unit, And a blocking member covering the pocket part to isolate the first downdraft and the second downdraft from each other. The semiconductor manufacturing facility according to claim 2, wherein the blocking member has an upper end and side walls extending from the upper end to cover the pocket part. 4. The semiconductor manufacturing facility according to claim 3, wherein an opening is formed in at least one of the sidewalls so that a substrate is provided from the outside to the pocket side through the opening. The method of claim 1, A first transfer guide coupled to the substrate transfer unit to guide the substrate transfer unit up and down about the process processor; And And a second transfer guide coupled to the first transfer guide to guide the substrate transfer unit to move from side to side around the process processor. The method of claim 5, wherein the processing unit is divided into layers, and the substrate transfer unit transfers a substrate provided from the outside to each of the layers using the first transfer guide and the second transfer guide. Semiconductor manufacturing equipment. The semiconductor manufacturing apparatus according to claim 1, wherein the moving speed of the second downdraft is greater than the moving speed of the first downdraft.
KR1020070078111A 2007-08-03 2007-08-03 Semiconductor device fabrication installation KR20090013941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070078111A KR20090013941A (en) 2007-08-03 2007-08-03 Semiconductor device fabrication installation

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Application Number Priority Date Filing Date Title
KR1020070078111A KR20090013941A (en) 2007-08-03 2007-08-03 Semiconductor device fabrication installation

Publications (1)

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KR20090013941A true KR20090013941A (en) 2009-02-06

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170054241A (en) * 2015-10-20 2017-05-17 램 리써치 코포레이션 Service tunnel for use on capital equipment in semiconductor manufacturing and research fabs

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170054241A (en) * 2015-10-20 2017-05-17 램 리써치 코포레이션 Service tunnel for use on capital equipment in semiconductor manufacturing and research fabs

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