KR20090011951A - Semiconductor pacakge and method for fabricating of the same - Google Patents

Abstract

A semiconductor package and a method for fabricating the same are provided to improve the electrical characteristic and the reliability by forming the electric connection between stacked semiconductor chips. A semiconductor package(200) is formed by stacking at least two semiconductor chips(210a,210b) using penetration silicon via and non conductive paste(250). The penetration silicon via comprises a pad(232) and a via pattern(230). The pad is formed on the semiconductor chip including the via pattern. The via pattern is formed within the semiconductor chip in order to be connected with the pad. The via pattern is exposed to the lower-part of the semiconductor chip and has a cone shape.

Description

Semiconductor package and method for manufacturing the same {Semiconductor pacakge and method for fabricating of the same}

The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same that can improve the electrical characteristics of the semiconductor package having a through-silicon via form.

Packaging technology for semiconductor integrated devices is continuously developed according to the demand for miniaturization and high capacity, and recently, various technologies for stack packages that can satisfy miniaturization, high capacity, and mounting efficiency have been developed.

The term "stack" in the semiconductor industry refers to a technology of vertically stacking at least two semiconductor chips or packages, and in the case of a memory device, a product having a memory capacity larger than the memory capacity that can be realized in a semiconductor integration process may be implemented and mounted. The efficiency of the use of the area can be improved.

The stacked semiconductor package may be classified into a method of stacking individual semiconductor chips according to a manufacturing technology, packaging the stacked semiconductor chips at once, and stacking and forming packaged individual semiconductor chips. The package is electrically connected through metal wires or through silicon vias or the like.

However, the stack type semiconductor package using the conventional metal wire is slow because electrical signal exchange is performed through the metal wire, and a large number of wires are used to cause deterioration of electrical characteristics of each chip. In addition, an additional area is required for the substrate to form the metal wire, thereby increasing the size of the package, and a gap (Gap) for wire bonding to the bonding pads of each chip is required, thereby increasing the overall height of the package.

Accordingly, the stack-type semiconductor package using through silicon vias (TSVs) is used to overcome the problems of the stacked-type semiconductor package using metal wires, and to prevent the deterioration and miniaturization of electrical characteristics of the stacked-type semiconductor package. A structure has been proposed.

1 is a cross-sectional view illustrating a stacked semiconductor package using a conventional through silicon via.

As illustrated, the stacked semiconductor package 100 using the through silicon vias may include the through silicon vias 130 having the through silicon vias 130 formed therein on the substrate 120. ) Are stacked to be interconnected.

Reference numeral 112 denotes a bonding pad, 122 denotes a connection pad, 124 denotes a borland, 126 denotes circuit wiring, 132 denotes a wiring, and 140 denotes an external connection terminal.

In the stack-type semiconductor package using the through silicon vias, electrical connection is made through the through silicon vias, thereby preventing electrical degradation, thereby improving the operation speed of the semiconductor chip and miniaturization thereof.

Meanwhile, the stacked semiconductor package using the through silicon vias described above uses a non conductive paste (NCP) for easy physical connection between upper and lower semiconductor chips.

2 is a cross-sectional view illustrating a conventional stacked semiconductor package using NCP.

As illustrated, the semiconductor chips 110a and 110b in which the via pattern 130 and the pad 132 on the top surface are integrally formed are stacked through the NCP 150.

Electrical connection of the stacked semiconductor package using the through silicon via using the NCP is performed by contacting the upper surface of the lower semiconductor chip with the lower portion of the through silicon via formed in the upper semiconductor chip passing through the NCP.

However, in the case of a stacked semiconductor package using NCP, the lower portion of the through-silicon via is formed in a cylindrical shape or a non-sharp shape, so that when the stack is not sufficiently penetrated through the NCP, electrical connection is not easily performed, thus stackable semiconductor package. Deterioration of electrical properties and deterioration of reliability occurs.

The present invention provides a semiconductor package and a method of manufacturing the same that can improve the electrical characteristics of the semiconductor package having a through-silicon via form.

In the semiconductor package according to the present invention, a semiconductor package formed by stacking at least two semiconductor chips through a through silicon via and a non conductive paste, wherein the through silicon via includes the via pattern. A pad formed on an upper surface of the semiconductor chip; And a via pattern formed in the semiconductor chip so as to be connected to the pad, and having a bottomed cone exposed to the bottom surface of the semiconductor chip having a pointed cone shape.

In addition, the semiconductor package according to the present invention is a semiconductor package formed by stacking at least two or more semiconductor chips through a through silicon via and a non conductive paste, wherein the through silicon via is formed within the semiconductor chip. Formed via patterns; And a pad formed in a conical shape on an upper surface of the semiconductor chip including the via pattern.

In addition, the method of manufacturing a semiconductor package according to the present invention comprises the steps of: forming a plurality of grooves having a conical bottom shape in a semiconductor chip; Forming a via layer in the semiconductor chip by filling a metal film on the semiconductor chip to fill the groove, and forming a pad on an upper surface of the semiconductor chip; Removing a bottom surface of the semiconductor chip to a partial thickness to expose a bottom surface of the via pattern; And stacking at least two or more semiconductor chips having the same structure as the via pattern through the non-conductive paste such that the via pattern of the semiconductor chip disposed thereon is connected to the pad of the semiconductor chip disposed below. It is characterized by including.

The groove having a conical bottom shape may be formed by any one of a laser drilling process or a plasma etching process or by using them together.

The connection between the lower surface of the via pattern having the cone shape of the stacked upper semiconductor chip and the upper pad of the lower semiconductor chip may be performed by any one of a method using solder, thermal-sonic, and ultrasonic. It is done.

Forming the plurality of grooves and stacking at least two or more semiconductor chips through non-conductive pastes may be performed at the wafer level.

The present invention is provided in each semiconductor chip, the lower portion of the via pattern of the through-silicon vias exposed to the lower portion of the semiconductor chip is formed in the form of a pointed cone, or the through-silicon pads formed on the upper surface of the semiconductor chip in the form of a cone It is formed to form a stacked semiconductor package through the NCP.

Accordingly, when the stacked semiconductor package is formed using NCPs and semiconductor chips having through-silicon vias formed of cone-shaped via patterns or pads, the via-patterns or pads having the conical shape may be formed. It is easily connected with via patterns or pads of the upper or lower semiconductor chip through the NCP.

Therefore, a semiconductor package excellent in electrical characteristics and reliability can be easily formed.

Hereinafter, a stack-type semiconductor package using a semiconductor chip having a cone-shaped via pattern or a pad according to an embodiment of the present invention and a manufacturing method thereof will be described in detail.

3 is a cross-sectional view illustrating a stacked semiconductor package using an NCP according to an embodiment of the present invention.

As illustrated, the semiconductor package 200 according to the present invention includes NCP 250 having semiconductor chips 210a and 210b having through silicon vias formed of via patterns 230 formed therein and pads 232 formed on an upper surface thereof. Stacked via

The lower portion of the via pattern 230 exposed to the lower portions of the semiconductor chips 210a and 210b is formed in a pointed cone shape.

Accordingly, in the case of forming a stacked semiconductor package using NCP, a cone-shaped via pattern provided in each semiconductor chip can easily penetrate the NCP, thereby easily making an electrical connection with the pad of the lower semiconductor chip.

Unexplained reference numeral 212 denotes a bonding pad.

Meanwhile, the stacked semiconductor package using the NCP and through silicon vias is formed by the same method as in FIGS. 4A to 4C below.

Referring to FIG. 4A, a groove T for forming a via pattern is formed on a wafer 210 formed of a plurality of semiconductor chips 210a having the manufacturing process completed and bonding pads 212 formed thereon. The groove T has a conical shape with a pointed bottom, and the groove T is formed by using a laser drilling process or a plasma etching process or by using them together.

Referring to FIG. 4B, after the metal seed film 216 is formed on the wafer 210 including the groove T, a plating process is performed such that the groove T is buried on the metal seed film 216. To form a metal film.

Then, after forming a mask pattern (not shown) covering the pad area on the metal film, the metal film and the metal seed film 216 are etched to form a pad 232 on a wafer and the mask pattern is removed. Remove Accordingly, a plurality of via patterns 230 and pads 232 are formed on the semiconductor chip 210a.

Referring to FIG. 4C, a thickness of the wafer 210 is reduced to a required height by performing a backgrinding process on a lower surface of the wafer 210, and then a selective etching process is performed on the lower surface of the wafer 210. The lower surface of the via pattern 230 having a conical shape is exposed to the lower surface of the wafer 210.

Referring to FIG. 4D, after stacking a plurality of wafers 210 having the above structure through the NCP 250, cutting the wafer to a chip level to manufacture the stacked semiconductor package 200 using the NCP 250. To complete. In this case, since the bottom surface of the via pattern 230 has a conical shape, the NCP 250 may be easily penetrated to easily make electrical connections between the upper and lower semiconductor chips 210a and 210b.

Connection between the pointed cone-shaped via pattern 230 of the upper semiconductor chip 210b and the pad 232 of the lower semiconductor chip 210a may be performed using solder, thermal-sonic, and ultrasonic waves. It is carried out in one of the methods.

In addition, the present invention may form a stacked semiconductor package by forming a pad formed on a semiconductor chip in a conical shape when forming a stacked semiconductor package using NCP.

5 is a cross-sectional view illustrating a stacked semiconductor package in accordance with another embodiment of the present invention.

As shown, the stacked semiconductor package 300 according to the present invention includes semiconductor chips 310a and 310b formed with a via pattern 330 formed therein and through silicon vias formed of a pad 332 having a conical shape formed on an upper surface thereof. Are stacked and formed via the NCP 350.

The conical pad 332 is formed by repeatedly performing a plating process. That is, first, a pad having a large area connected to the via pattern is formed, and then a pad having a small area is sequentially patterned thereon.

Therefore, when the pad 332 forms the stacked semiconductor package 300 using the NCP 350 and the semiconductor chips 310a and 310b having the through-silicon vias having a conical shape, the semiconductor chips 310a and The cone-shaped pad 332 provided in the 310b may easily penetrate the NCP 350, thereby easily making an electrical connection with the via pattern 330 of the upper semiconductor chip 310b.

Unexplained reference numeral 312 denotes a bonding pad.

As described above, the present invention is provided in each semiconductor chip, the lower portion of the via pattern exposed to the lower portion of the semiconductor chip is formed in the shape of a pointed cone, or the pad formed on the upper surface of the semiconductor chip in the form of a cone Thus, the via-shaped via pattern or pad may easily penetrate the NCP to form an easy electrical connection between the stacked semiconductor chips, thereby manufacturing a semiconductor package having excellent electrical characteristics and reliability.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a cross-sectional view illustrating a conventional stacked semiconductor package using through silicon vias.

2 is a cross-sectional view illustrating a conventional stacked semiconductor package using NCP.

3 is a cross-sectional view illustrating a stacked semiconductor package using an NCP according to an embodiment of the present invention.

4A to 4D are cross-sectional views of processes for describing a method of manufacturing a stacked semiconductor package according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a stacked semiconductor package according to another embodiment of the present invention.

Claims (6)

In the semiconductor package formed by stacking at least two or more semiconductor chips through the through-silicon via and the non-conductive paste, The through silicon vias, A pad formed on an upper surface of the semiconductor chip including the via pattern; And A via pattern formed in the semiconductor chip so as to be connected to the pad, and having a pointed cone shape at a lower portion exposed to a bottom surface of the semiconductor chip; A semiconductor package comprising a. In the semiconductor package formed by stacking at least two or more semiconductor chips through the through-silicon via and the non-conductive paste, The through silicon vias, A via pattern formed in the semiconductor chip; And A pad formed in a conical shape on an upper surface of the semiconductor chip including the via pattern; Semiconductor package comprising a. Forming a plurality of grooves having a conical bottom shape in the semiconductor chip; Forming a via layer in the semiconductor chip by filling a metal film on the semiconductor chip to fill the groove, and forming a pad on an upper surface of the semiconductor chip; Removing a bottom surface of the semiconductor chip to a partial thickness to expose a bottom surface of the via pattern; And Stacking at least two or more semiconductor chips having the same structure with the via patterns through the non-conductive paste such that the via patterns of the semiconductor chips disposed thereon are connected to the pads of the semiconductor chips disposed below; Method for producing a semiconductor package comprising a. The method of claim 3, wherein The groove having a conical bottom shape is formed by any one of a laser drilling process or a plasma etching process or is formed by using them together. The method of claim 3, wherein The connection between the lower surface of the via pattern having the cone shape of the stacked upper semiconductor chip and the upper pad of the lower semiconductor chip may be performed by any one of a method using solder, thermal-sonic, and ultrasonic. The manufacturing method of the semiconductor package made into. The method of claim 3, wherein Forming the plurality of grooves and stacking at least two or more semiconductor chips through non-conductive pastes at a wafer level.

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