KR20090011812A

KR20090011812A - Apparatus for low power semiconductor chip

Info

Publication number: KR20090011812A
Application number: KR1020070075769A
Authority: KR
Inventors: 김민수
Original assignee: 삼성전자주식회사
Priority date: 2007-07-27
Filing date: 2007-07-27
Publication date: 2009-02-02

Abstract

A low-power semiconductor device is provided to reduce dynamic power consumption and static power consumption and to simplify a manufacturing process. A low power semiconductor device(300) includes a core logic(10) and a plurality of slip control transistors(20,30). The core logic includes a logic transistor having a first threshold voltage. The slip control transistors have a second threshold voltage having the same voltage level as the voltage level f the first threshold voltage. The slip control transistors are connected between the core logic and a positive power source(VDD) or a negative power source(VSS).

Description

Low power semiconductor device {Apparatus for low power semiconductor chip}

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a low power semiconductor device.

In general, low threshold voltage MOS (Metal Oxide Semiconductor) can operate at high speed in a dynamic state, but the static current consumption is large because a large leakage current in a static state. On the other hand, the high threshold voltage MOS has a small leakage current in the static state, so the static power consumption is small, but high-speed operation is difficult in the dynamic state. In order to compensate for such drawbacks, MTCMOS (Multiple Threshold Complementary Metal Oxide Semiconductor) circuits are generally used in low power semiconductor chip designs.

The MTCMOS circuit uses a high threshold sleep control transistor to connect to VDD and / or VSS, and the internal core logic circuit has a low threshold voltage of metal oxide semiconductor (MOS). Is implemented using Therefore, in the dynamic state, the sleep control transistor is turned on so that the core logic circuit operates based on the low threshold voltage of the core logic circuit without being affected by the high threshold voltage of the sleep control transistor, thereby enabling high-speed operation. On the other hand, in the static state, by turning off the sleep control transistor, the leakage current is cut off based on the high threshold voltage of the sleep control transistor, thereby reducing the static power consumption.

Due to the expansion of the mobile market, SOC (System On Chip) that can run for a long time with a high performance processing capacity with a limited battery is required in the market. On the other hand, as the cost of semiconductor chips is getting lower and lower, there is a need for a device that can simplify the manufacturing process while consuming low power. However, the MTCMOS circuit can not reduce the dynamic power consumption in the dynamic state, and above all, there is a problem that a separate dual threshold voltage process is required to realize the dual threshold voltage. In addition, such MTCMOS circuits are not suitable for Ultra High Speed processes that require high speed operation. Accordingly, not only static power consumption in the static state but also dynamic power consumption in the dynamic state can be reduced, and a low power semiconductor device that does not require a separate dual threshold voltage process is required.

In order to solve the above problems, it is an object of the present invention to provide a low power semiconductor device capable of reducing dynamic power consumption and static power consumption and simplifying the manufacturing process.

In order to achieve the aforementioned object of the present invention, a low-power semiconductor device according to an embodiment of the present invention includes a core logic including a logic transistor having a first threshold voltage, and a second voltage having the same voltage level as the first threshold voltage. And a sleep control transistor having a threshold voltage and connected between the core logic and a positive power supply unit or a negative power supply unit.

In some embodiments, the sleep control transistor may include a P type first sleep control transistor, and the first sleep control transistor may be connected between the positive power supply unit and the core logic.

In some embodiments, the sleep control transistor may include an N type second sleep control transistor, and the second sleep control transistor may be connected between the negative power supply unit and the core logic.

According to an embodiment, the sleep control transistor includes a P type first sleep control transistor and an N type second sleep control transistor, wherein the first sleep control transistor is connected between the positive power supply and the core logic. The second sleep control transistor may be connected between the negative power supply unit and the core logic.

In some embodiments, the logic transistor and the sleep control transistor may have a minimum channel length in a MOS process.

A low power semiconductor device according to another embodiment of the present invention has a core logic including a logic transistor having a first threshold voltage, and a second threshold voltage having a voltage level lower than the first threshold voltage. And a slip control transistor connected between the power supply unit or the negative power supply unit.

The low power semiconductor device according to embodiments of the present invention may reduce dynamic power consumption and static power consumption, and simplify the manufacturing process.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Similar reference numerals are used for the components in describing the drawings.

Terms such as first and second may be used to describe various components, but the components are not limited by these terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may be present in the middle. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it may be understood that there is no other component in between. Other expressions describing the relationship between the components may be interpreted as well, such as "between" and "immediately between" or "neighboring to" and "directly neighboring".

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It will be understood that it does not exclude in advance the possibility of the presence or the addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, a method of manufacturing a transistor according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In general, in a MOS transistor, W is a channel width, L is a channel length, Vgs is a voltage difference between a gate and a source, Vth is a threshold voltage, and Vds is a voltage difference between a drain and a source. The drain current at is roughly proportional to (W / L), (Vgs-Vth), and Vds, and the drain current at saturation region is roughly proportional to (W / L), and squared of (Vgs-Vth). The drain current in the threshold region is proportional to exp (Vgs / Vth). Therefore, at low threshold voltages, drain current flows even when the voltage difference between the gate and source is relatively small, so that high speed operation is possible in a dynamic state, but leakage current occurs in a static state. On the other hand, at high threshold voltages, the drain current flows only when the voltage difference between the gate and the source is relatively high, so that the leakage current in the static state decreases, but it is difficult to operate at high speed in the dynamic state.

1 is a circuit diagram illustrating a low power semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1, the low power semiconductor device 100 includes a core logic 10 and a P type first sleep control transistor 20.

The threshold voltage of the logic transistor in the core logic 10 is equal to the threshold voltage of the P type first sleep control transistor 20. The first sleep control transistor 20 is connected between the positive power supply unit VDD and the core logic 10, and the core logic 10 is directly connected to the negative power supply unit VSS.

In the dynamic state, the first sleep control transistor 20 is turned on so that the positive virtual power supply unit VDDV has a voltage level close to that of the positive power supply unit VDD. Since the threshold voltage of the logic transistor inside the core logic 10 and the threshold voltage of the first sleep control transistor 20 are implemented to have a low voltage level, high-speed operation is possible based on sufficient current driving force in a dynamic state. Therefore, when the voltage level of the positive power supply unit VDD is lowered, since the low threshold voltage has sufficient current driving force in a dynamic state, high-speed operation can be performed as before. Therefore, the low power semiconductor device 100 according to the embodiment of the present invention can reduce the dynamic power consumption.

In the static state, the first sleep control transistor 20 is turned off, but because of the low threshold voltage, a leakage current occurs. However, since the total leakage current is dependent on the leakage current of the first slip control transistor 20 due to the connection of one first slip control transistor 20, the total amount of leakage current is lower than that of the first slip control transistor 20. Leakage current is reduced. In addition, since the first sleep control transistor 20 is connected in series with the core logic 10, the width of the entire low power semiconductor device 100 is reduced and the drain and source of the first sleep control transistor 20 are reduced. The effect of reducing the voltage difference between them is shown, whereby the total leakage current is further reduced. Therefore, the low power semiconductor device 100 according to the embodiment of the present invention can reduce the static power consumption. In general, the channel lengths of the logic transistors in the first sleep control transistor 20 and the core logic 10 may have 0.18 μm, 0.13 μm, 0.09 μm, etc., depending on the process. It may have a minimum length of phase, i.e., the minimum length recommended by the MOS process.

2 is a circuit diagram illustrating a low power semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 2, the low power semiconductor device 200 includes a core logic 10 and an N type second sleep control transistor 30.

The threshold voltage of the logic transistor in the core logic 10 is equal to the threshold voltage of the N type second sleep control transistor 30. The second sleep control transistor 30 is connected between the negative power supply unit VSS and the core logic 10, and the core logic 10 is directly connected to the positive power supply unit VDD.

In the dynamic state, the second sleep control transistor 30 is turned on so that the negative virtual power supply unit VSSV has a voltage level close to the voltage level of the negative power supply unit VSS. Since the threshold voltage of the logic transistor inside the core logic 10 and the threshold voltage of the second sleep control transistor 30 are implemented to have a low voltage level, high-speed operation is possible based on sufficient current driving force in a dynamic state. Therefore, when the voltage level of the positive power supply unit VDD is lowered, since the low threshold voltage has sufficient current driving force in a dynamic state, high-speed operation can be performed as before. Therefore, the low power semiconductor device 200 according to the embodiment of the present invention can reduce the dynamic power consumption.

In the static state, the second slip control transistor 30 is turned off, but because of the low threshold voltage, a leakage current occurs. However, since the total leakage current is dependent on the leakage current of the second slip control transistor 30 due to the connection of one second slip control transistor 30, the total amount of leakage current depends on the leakage current of the second slip control transistor 30. Leakage current is reduced. In addition, since the second sleep control transistor 30 is connected in series with the core logic 10, the width of the entire low power semiconductor device 200 is reduced, and the drain and source of the second sleep control transistor 30 are reduced. The effect of reducing the voltage difference between them is shown, whereby the total leakage current is further reduced. Therefore, the low power semiconductor device 200 according to the embodiment of the present invention can reduce the static power consumption. In general, the channel lengths of the second sleep control transistor 30 and the logic transistor inside the core logic 10 may have 0.18 μm, 0.13 μm, 0.09 μm, etc., depending on the process. It may have a minimum length of phase, i.e., the minimum length recommended by the MOS process.

3 is a circuit diagram illustrating a low power semiconductor device according to a third embodiment of the present invention.

Referring to FIG. 3, the low power semiconductor device 300 includes a core logic 10, a P type first sleep control transistor 20, and an N type second sleep control transistor 30.

The threshold voltage of the logic transistor in the core logic 10 is equal to the threshold voltage of the P type first sleep control transistor 20 and the threshold voltage of the N type second sleep control transistor 30. The first sleep control transistor 20 is connected between the positive power supply unit VDD and the core logic 10, and the second sleep control transistor 30 is connected to the negative power supply unit VSS and the core logic unit 10. ) Is connected between.

In the dynamic state, the first sleep control transistor 20 is turned on so that the voltage level of the positive virtual power supply unit VDDV has a voltage level that is close to the voltage level of the positive power supply unit VDD. The voltage level of the negative virtual power supply unit VSSV is turned on to have a voltage level that is close to the voltage level of the negative power supply unit VSS. Since the threshold voltages of the logic transistors in the core logic 10 and the threshold voltages of the first and second sleep control transistors 20 and 30 are implemented to have low voltage levels, high-speed operation is possible based on sufficient current driving force in a dynamic state. Therefore, when the voltage level of the positive power supply unit VDD is lowered, since the low threshold voltage has sufficient current driving force in a dynamic state, high-speed operation can be performed as before. Therefore, the low power semiconductor device 300 according to the embodiment of the present invention can reduce the dynamic power consumption.

In the static state, the first and second sleep control transistors 20 and 30 are turned off, but because of the low threshold voltage, leakage current occurs. However, due to the connection of the first and second slip control transistors 20 and 30, the amount of total leakage current depends on the leakage currents of the first and second slip control transistors 20 and 30, and thus, the first and second sleep. The total leakage current is reduced as compared with the absence of the control transistors 20 and 30. In addition, since the first and second sleep control transistors 20 and 30 are connected in series with the core logic 10, the width of the entire low power semiconductor device 300 is reduced and the first and second sleep control are reduced. The voltage difference between the drain and the source of the transistors 20 and 30 is reduced, thereby reducing the total leakage current. Therefore, the low power semiconductor device 300 according to the embodiment of the present invention can reduce the static power consumption. In general, the channel lengths of the first sleep control transistor 20, the second sleep control transistor 30, and the logic transistor inside the core logic 10 may have 0.18 μm, 0.13 μm, 0.09 μm, etc., depending on the process. This may have a minimum length in the MOS process, that is, the minimum length recommended by the MOS process, according to the development of process technology.

4 is a circuit diagram illustrating a low power semiconductor device according to a fourth embodiment of the present invention.

Referring to FIG. 4, the low power semiconductor device 400 includes a core logic 60 and a P type first sleep control transistor 70.

The threshold voltage of the first sleep control transistor 70 is lower than the threshold voltage of the logic transistor in the core logic 60. The first sleep control transistor 70 is connected between the positive power supply unit VDD and the core logic 60, and the core logic 60 is directly connected to the negative power supply unit VSS.

Due to the low threshold voltage of the logic transistor inside the core logic 60 and the lower threshold voltage of the first sleep control transistor 70, as shown in the low power semiconductor device 100 of FIG. 1, sufficient current driving force is provided in a dynamic state. In the dynamic state, high speed operation may be performed as before, and even in the static state, the static power consumption may be reduced because the total leakage current depends on the leakage current of the first sleep control transistor 70. In general, the channel lengths of the logic transistors inside the first sleep control transistor 70 and the core logic 60 may have 0.18 μm, 0.13 μm, 0.09 μm, etc., depending on the process. It may have a minimum length of phase, i.e., the minimum length recommended by the MOS process.

5 is a circuit diagram illustrating a low power semiconductor device according to a fifth embodiment of the present invention.

Referring to FIG. 5, the low power semiconductor device 500 includes a core logic 60 and an N type second sleep control transistor 80.

The threshold voltage of the second sleep control transistor 80 is lower than the threshold voltage of the logic transistor in the core logic 60. The second sleep control transistor 80 is connected between the negative power supply unit VSS and the core logic 60, and the core logic 60 is directly connected to the positive power supply unit VDD.

Due to the low threshold voltage of the logic transistor inside the core logic 60 and the lower threshold voltage of the second sleep control transistor 80, as in the low power semiconductor device 200 of FIG. In the dynamic state, the high speed operation can be performed as before, and even in the static state, the static power consumption can be reduced because the total leakage current depends on the leakage current of the second sleep control transistor 80. In general, the channel lengths of the logic transistors inside the second sleep control transistor 80 and the core logic 60 may have 0.18 μm, 0.13 μm, 0.09 μm, etc., depending on the process. It may have a minimum length of phase, i.e., the minimum length recommended by the MOS process.

6 is a circuit diagram illustrating a low power semiconductor device according to a sixth embodiment of the present invention.

Referring to FIG. 6, the low power semiconductor device 600 includes a core logic 60, a P type first sleep control transistor 70, and an N type second sleep control transistor 80.

The threshold voltages of the first and second sleep control transistors 70 and 80 are lower than the threshold voltages of the logic transistors in the core logic 60. The first sleep control transistor 70 is connected between the positive power supply unit VDD and the core logic 60, and the second sleep control transistor 80 is connected between the negative power supply unit VSS and the core logic unit 60. Is connected to.

Due to the low threshold voltage of the logic transistors inside the core logic 60 and the lower threshold voltages of the first and second sleep control transistors 70 and 80, sufficient power in a dynamic state, such as the low power semiconductor device 300 of FIG. Because of the current driving force, the high speed operation can be performed in the dynamic state as before, and even in the static state, the static power consumption is increased because the total leakage current depends on the leakage current of the first and second slip control transistors 70 and 80. Can be reduced. In general, the channel lengths of the first sleep control transistor 70, the second sleep control transistor 80, and the logic transistor inside the core logic 60 may have 0.18 μm, 0.13 μm, 0.09 μm, etc., depending on the process. This may have a minimum length in the MOS process, that is, the minimum length recommended by the MOS process, according to the development of process technology.

According to the present invention, the low power semiconductor device can reduce the dynamic power consumption and the static power consumption and simplify the manufacturing process. Therefore, the low power semiconductor device according to the present invention can be applied to a circuit capable of operating at low power and a system on chip (SOC).

Although described above with reference to the preferred embodiment of the present invention, those skilled in the art that various modifications and changes within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below It will be appreciated that it can be changed.

300: low power semiconductor device 10: core logic

20: first slip control transistor

30: second slip control transistor

Claims

Core logic including a logic transistor having a first threshold voltage; And

And a sleep control transistor having a second threshold voltage having the same voltage level as the first threshold voltage and connected between the core logic and a positive power supply unit or a negative power supply unit.

The low power semiconductor device of claim 1, wherein the sleep control transistor comprises a P type first sleep control transistor, and the first sleep control transistor is connected between the positive power supply unit and the core logic.

The low power semiconductor device of claim 1, wherein the sleep control transistor comprises an N type second sleep control transistor, and the second sleep control transistor is connected between the negative power supply unit and the core logic.

The sleep control transistor of claim 1, wherein the sleep control transistor comprises a first sleep control transistor of a P type and a second sleep control transistor of an N type, and the first sleep control transistor is connected between the positive power supply and the core logic. And the second sleep control transistor is connected between the negative power supply unit and the core logic.

The low power semiconductor device according to any one of claims 1 to 4, wherein the logic transistor and the sleep control transistor have a minimum channel length in a MOS process.

Core logic including a logic transistor having a first threshold voltage; And

And a sleep control transistor having a second threshold voltage having a voltage level lower than the first threshold voltage and connected between the core logic and a positive power supply unit or a negative power supply unit.

7. The low power semiconductor device of claim 6, wherein the sleep control transistor comprises a P type first sleep control transistor, and the first sleep control transistor is connected between the positive power supply and the core logic.

The low power semiconductor device of claim 6, wherein the sleep control transistor comprises an N type second sleep control transistor, and the second sleep control transistor is connected between the negative power supply unit and the core logic.

7. The sleep control transistor of claim 6, wherein the sleep control transistor comprises a first sleep control transistor of a P type and a second sleep control transistor of an N type, wherein the first sleep control transistor is disposed between the positive power supply and the core logic. And the second sleep control transistor is connected between the negative power supply unit and the core logic.

10. The low power semiconductor device of any one of claims 6 to 9, wherein the logic transistor and the sleep control transistor have a minimum channel length in a MOS process.