KR20090010601A - Phase change memory device - Google Patents

Abstract

A phase change memory device is provided to reduce a line resistance of a global word line by forming a global word line shared by a plurality of sub cell arrays. A cell array(120) comprises a plurality of sub cell arrays(SCA-1~SCA-n) and a plurality of sub row switches(SRSW-0~SRSW-(n+1)). A global row decoder block(GXDEC-B) comprises a global pre-charge control part(130), a global row switch(140), and a global row decoder(150). A sub row decoder(100) outputs a sub row switch control signal(SRS-0~SRS-n) by decoding a row address. The global pre-charge control part outputs a word line pre-charge signal(WL-PREC) according to a signal of a global row decoder line(GXDEC) and a word line active signal(WL-ACT). The global row switch pre-charges a word line according to the word line pre-charge signal. A global row decoder selects the global row decoder line by decoding a plurality of row addresses(Xadd0-Xaddn).

Description

Phase change memory device

1A and 1B are diagrams for explaining a conventional phase change resistance element.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

4 is a block diagram of a phase change memory device according to the present invention;

5 is an overall configuration diagram of a phase change memory device according to the present invention.

6 illustrates a cross-sectional structure of a word line and a global row decoder line on a cell array in accordance with the present invention.

7 illustrates a cross-sectional structure of a word line and a global row decoder line on a cell array according to the present invention.

FIG. 8 is a circuit diagram illustrating a connection relationship of global row decoder lines in the cell array of FIG. 7. FIG.

FIG. 9 is a detailed circuit diagram illustrating a sub cell array and a sub row switch of FIG. 4. FIG.

FIG. 10 illustrates another embodiment of the sub cell array and sub row switch of FIG. 4. FIG.

FIG. 11 is another embodiment of a subcell array and subrow switch of FIG. 4; FIG.

FIG. 12 is a detailed circuit diagram of the global row switch of FIG. 4. FIG.

FIG. 13 is another embodiment of the global row switch of FIG. 4; FIG.

FIG. 14 is yet another embodiment of the global row switch of FIG. 4; FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device, and is a technique of improving the structure of a loo decoder and a lodo decoder line in a memory device including a phase change resistance element.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the state of electrical conduction according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2. In addition, the phase change layer 2 uses a chalcogenide (chalcogenide) mainly composed of chalcogen elements (S, Se, Te), specifically, a germanium antimony tellurium alloy material consisting of Ge-Sb-Te (Ge2Sb2Te5). ).

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, if the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the top electrode 1 and the bottom electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the top electrode 1 and the bottom electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

The present invention has the following object.

First, in a phase change memory device, an object of the present invention is to improve the structure of a row decoder and a global row decoder line so as to reduce layout size and simplify circuit configuration.

Second, the purpose is to implement a global row decoder line shared by a plurality of sub-cell arrays to reduce line resistance of the global word line and improve metal process margins.

Third, the purpose is to improve and simplify the circuit configuration of the global row decoder and sub row switch.

A phase change memory device according to an embodiment of the present invention includes: a plurality of subcell arrays including a phase change resistance cell configured to store a data corresponding to a change in resistance by sensing a crystallization state that changes according to a magnitude of current; A global row decoder line shared by the plurality of subcell arrays; A sub row decoder configured to decode a row address and output a sub row switch control signal; A sub row switch for outputting a sub row switch control signal to the plurality of sub cell arrays according to a voltage level of the global row decoder line; And a global row decoder block for selecting word lines of the plurality of subcell arrays and controlling voltage levels of the global row decoder lines according to the word line active signals.

The present invention also provides a plurality of word lines arranged in a row direction; A plurality of bit lines arranged in a column direction; A plurality of cell arrays formed at areas where word lines and bit lines cross each other and including phase change resistance cells configured to store a data corresponding to a change in resistance by sensing a crystallization state that changes according to a magnitude of a current; And a global row decoder line shared by the plurality of cell arrays, wherein the global row decoder line is formed on a metal layer at the same level as the word line.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a configuration diagram illustrating a phase change memory device according to the present invention.

The present invention includes a sub row decoder 100, a cell array 120, and a global row decoder block GXDEC_B. Here, the cell array 120 includes a plurality of sub cell arrays SCA_1 to SCA_n and a plurality of sub row switches SRSW_0 to SRSW_ (n + 1). The global row decoder block GXDEC_B includes a global precharge control unit 130, a global row switch 140, and a global row decoder 150.

Each of the subcell arrays SCA_1 to SCA_n is disposed such that a plurality of bit lines BL and word lines WL cross each other. Each word line WL is connected to a sub row switch SRSW, respectively. That is, one end of the sub row switch SRSW is connected to the word line WL, and the other end is connected to the sub row decoder 100. The sub row decoder 100 decodes the row address and outputs the sub row switch control signals SRS_0 to SRS_n.

In addition, the gate terminals of the plurality of sub row switches SRSW_1 to SRSW_n are commonly connected to the global row decoder line GXDEC. Sub-low switch control signals SRS_0 to SRS_n, which are outputs of the sub-row decoder 100, are respectively applied to the plurality of sub-row switches SRSW_0 to SRSW_ (n + 1).

In addition, the global precharge control unit 130 outputs the word line precharge signal WL_PREC according to the signal of the global row decoder line GXDEC and the word line active signal WL_ACT.

The global row switch 140 is connected to the word line WL and precharges the word line according to the word line precharge signal WL_PREC. In addition, the global row switch 140 is controlled by the word line precharge signal WL_PREC and shares the word line precharge signal WL_PREC.

In addition, the global row decoder 150 is connected to the global row decoder line GXDEC. The global row decoder 150 decodes the plurality of row addresses Xadd0 to Xaddn to select the global row decoder line GXDEC.

5 is an overall configuration diagram of a phase change memory device according to the present invention.

The cell array 120 of the present invention includes a plurality of word lines WL arranged in a row direction and a plurality of bit lines BL arranged in a column direction. The unit cell C is included in an area where the plurality of word lines WL and the plurality of global bit lines GBL intersect. The global bit line GBL (or bit line BL) is connected to the sense amplifier S / A and the write driver W / D.

Here, the sense amplifier S / A senses and amplifies cell data applied from the global bit line GBL. The write driver W / D supplies a driving voltage corresponding to write data stored in the unit cell C.

The global row decoder block GXDEC_B selects the word line WL and the global row decoder line GXDEC of the cell array 120. Here, the global row decoder line GXDEC is formed using a metal layer having the same level as the word line WL. The global row decoder line GXDEC (for example, one) is arranged for each specific number (for example, seven) of word lines WL.

6 is a cross-sectional view of the word line WL and the global row decoder line GXDEC on the cell array 120 according to the present invention.

As shown in the cross-sectional structure of FIG. 6, the word line WL and the global row decoder line GXDEC are formed using the same level metal layer. Based on the same level metal layer, the word line WL disposed at a specific position among the plurality of word lines WL is used as the global row decoder line GXDEC.

7 illustrates a cross-sectional structure of a word line WL and a global row decoder line GXDEC on a cell array 120 according to the present invention.

As shown in the cross-sectional structure of FIG. 7, the word line WL and the global row decoder line GXDEC are composed of lines of the same size. The row decoder line GXDEC formed using the word line WL is not connected to the cell.

That is, the word line WL forms a contact line connected to the cell, and the row decoder line GXDEC opens without forming a contact line with the cell.

FIG. 8 is a circuit diagram illustrating a connection relationship between the global row decoder lines GXDEC in the cell array 120 of FIG. 7.

The unit cell C formed in the region where the bit line BL and the word line WL cross each other includes a phase change resistance element PCR and a diode D. Here, the phase change resistance element PCR is connected between the bit line BL and the P-type region of the diode D. In the diode D, the P-type region is connected to the phase change resistance element PCR, and the N-type region is connected to the word line WL.

On the other hand, the unit cell DEC_C connected to the global row decoder line GXDEC includes the phase change resistance element PCR and the diode D in the same way as the unit cell C. The phase change resistance device PCR is connected between the bit line BL and the P-type region of the diode D.

However, in the diode D included in the unit cell DEC_C, the P-type region is connected to the phase change resistance element PCR, and the N-type region is opened without being connected to the word line WL. That is, the P-type region of the diode D is connected to the phase change resistance element PCR, but the N-type region is open because no contact is made with the global decoder line GXDEC.

The present invention forms the same unit cell DEC_C as the unit cell C for convenience and regularity of the process, but forms the diode D included in the unit cell DEC_C in an open state so as not to be used as a substantial cell. That is, the word line WL formed on the same metal layer as the word line WL is used as the global row decoder line GXDEC to reduce the area of the entire cell array.

FIG. 9 is a detailed circuit diagram of the sub cell array SCA and the sub row switch SRSW of FIG. 4.

Each sub cell array SCA_1 to SCA_n includes a unit cell C disposed in an area where a plurality of bit lines BL and a plurality of word lines WL0 to WLn cross each other. The unit cell C includes a phase change resistance element PCR and a diode D. Here, the diode D is preferably made of a PN diode element.

One electrode of the phase change resistance element PCR is connected to the bit line BL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL. The phase of the phase change resistance element PCR is changed according to the set current Iset and the reset current Ireset flowing in the bit line BL, so that data can be written.

Each word line WL is connected to a sub row switch SRSW. That is, the sub row switch SRSW includes a plurality of switching elements connected between the word line WL and the sub row decoder 100.

Here, the plurality of switching elements are preferably made of NMOS transistors N0 to N3. In the embodiment of the present invention, the sub-row switch SRSW has been described as an NMOS transistor. However, the present invention is not limited thereto and may be implemented as a PMOS transistor.

The drain terminals of the NMOS transistors N0 to N3 are connected to respective word lines WL0 to WL3 corresponding thereto, and the gate terminal is commonly connected to the global row decoder line GXDEC. The NMOS transistors N0 to N3 are supplied with sub-row switch control signals SRS_0 to SRS_3 that are outputs of the sub-row decoder 100 through respective source terminals.

FIG. 10 is another embodiment of the sub-cell array SCA and sub-row switch SRSW of FIG. 4.

Each sub cell array SCA_1 to SCA_n includes a unit cell C disposed in an area where a plurality of bit lines BL and a plurality of word lines WL0 to WLn cross each other. Here, the unit cell C includes a phase change resistance device PCR and a diode D.

One electrode of the phase change resistance element PCR is connected to the bit line BL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL. The phase of the phase change resistance element PCR is changed according to the set current Iset and the reset current Ireset flowing in the bit line BL, so that data can be written.

Each word line WL is connected to a sub row switch SRSW. That is, the sub row switch SRSW includes a plurality of switching elements connected between the word line WL and the sub row decoder 100.

Here, it is preferable that the plurality of switching elements consist of bipolar junction transistors (BJTs) B0 to B3. In the exemplary embodiment of the present invention, the sub-row switch SRSW is described as an NPN type bipolar junction transistor. However, the present invention is not limited thereto and may be implemented as a PNP type bipolar junction transistor.

The collector terminals of the bipolar junction transistors B0 to B3 are connected to their respective wordlines WL0 to WL3, and the base terminals are commonly connected to the global row decoder line GXDEC. Sub-polar switch control signals SRS_0 to SRS_3, which are outputs of the sub-row decoder 100, are applied to the bipolar junction transistors B0 to B3 through respective emitter terminals.

FIG. 11 is yet another embodiment of a subcell array SCA and a sub-row switch SRSW of FIG. 4.

Each sub cell array SCA_1 to SCA_n includes a unit cell C disposed in an area where a plurality of bit lines BL and a plurality of word lines WL0 to WLn cross each other. Here, the unit cell C includes a phase change resistance device PCR and a diode D.

One electrode of the phase change resistance element PCR is connected to the bit line BL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL. The phase of the phase change resistance element PCR is changed according to the set current Iset and the reset current Ireset flowing in the bit line BL, so that data can be written.

Each word line WL is connected to a sub row switch SRSW. That is, the sub row switch SRSW includes a plurality of switching elements connected between the word line WL and the sub row decoder 100.

Here, it is preferable that the some switching element consists of PNPN diode switches PNSW0-PNSW3. In the embodiment of the present invention, the sub-row switch SRSW has been described as a PNPN diode device, but the present invention is not limited thereto, and may be implemented as a NPNP diode device.

The P-type regions of the PNPN diode switches PNSW0 to PNSW3 are connected to the respective word lines WL0 to WL3, and the P-type region is commonly connected to the global row decoder line GXDEC. The PNPN diode switches PNSW0 to PNSW3 are supplied with sub-row switch control signals SRS_0 to SRS_3 that are outputs of the sub-row decoder 100 through respective N-type emitter terminals.

The detailed structure and operating principle of the PNPN diode switch is disclosed in Patent Application No. 2003-0090962 filed by the same inventor.

12 is a detailed circuit diagram of the global row switch 140 of FIG.

The global row switch 140 includes a plurality of switching elements each connected to the word line WL of the cell array 120. Here, the switching element preferably consists of PMOS transistors P0 to P3.

In the exemplary embodiment of the present invention, the global row switch is implemented as a PMOS transistor for low voltage driving characteristics. However, the present invention is not limited thereto and may be implemented as an NMOS transistor.

Here, the drain terminals of the respective PMOS transistors P0 to P3 are connected to the word lines WL0 to WL3, and the word line precharge signal WL_PREC is commonly applied through the gate terminal. The source terminal of each PMOS transistor P0 to P3 is connected to the pumping voltage VPP applying terminal, which is a word line power supply.

The plurality of PMOS transistors P0 to P3 have one word line precharge signal WL_PREC applied through a common gate terminal to share the word line precharge signal WL_PREC. Accordingly, when the word line precharge signal WL_PREC is activated, the word line WL is precharged to the pumping voltage VPP level.

FIG. 13 is another embodiment of the global row switch 140 of FIG. 4.

The global row switch 140 includes a plurality of switching elements connected to the word lines WL0 to WL3 of the cell array 120, respectively. Here, the switching element is preferably made of a bipolar junction transistor (BJT) B4 ~ B7.

In the exemplary embodiment of the present invention, the global row switch is described as an NPN type bipolar junction transistor. However, the present invention is not limited thereto and may be implemented as a PNP type bipolar junction transistor.

Here, the emitter terminals of each of the bipolar junction transistors B4 to B7 are connected to the word lines WL0 to WL3, and the word line precharge signal WL_PREC is commonly applied through the base terminal. The collector terminal of each of the bipolar junction transistors B4 to B7 is connected to the pumping voltage VPP applying stage, which is a word line power supply.

In the plurality of bipolar junction transistors B4 to B7, one word line precharge signal WL_PREC is applied through a common base terminal to share the word line precharge signal WL_PREC. Accordingly, when the word line precharge signal WL_PREC is activated, the word line WL is precharged to the pumping voltage VPP level.

FIG. 14 is yet another embodiment of the global row switch 140 of FIG. 4.

The global row switch 140 includes a plurality of switching elements connected to the word lines WL0 to WL3 of the cell array 120, respectively. Here, it is preferable that a switching element consists of PNPN diode switches PNSW4-PNSW7.

In the exemplary embodiment of the present invention, the global row switch is described as a PNPN diode device, but the present invention is not limited thereto, and may be implemented as an NPNP diode device.

Here, the N-type regions (Emitters) of the respective PNPN diode switches PNSW4 to PNSW7 are connected to the word lines WL0 to WL3, and the word line precharge signal WL_PREC is commonly applied through the P-type region Base. The P-type collector of each PNPN diode switch PNSW4 to PNSW7 is connected to the pumping voltage VPP applying stage, which is a word line power source.

In the plurality of PNPN diode switches PNSW4 to PNSW7, one word line precharge signal WL_PREC is applied through a common P-type region to share the word line precharge signal WL_PREC. Accordingly, when the word line precharge signal WL_PREC is activated, the word line WL is precharged to the pumping voltage VPP level.

In the present invention having such a configuration, the global row decoder 150 is in a high state in an active operation mode. When the word line WL is enabled at the low level, the word line active signal WL_ACT is at the high level, and the global row switches P0 to P3 maintain the turn-off state. Then, the sub row decoder 100 is in a low state and the word line WL is in a floating state.

On the other hand, in the present invention, the global row decoder 150 goes low in the inactive mode. When the word line WL is disabled at a high level, the word line active signal WL_ACT is at a low level. Accordingly, the global row switches P0 to P3 are turned on to precharge the word line WL to the pumping voltage VPP level.

At this time, the sub row switches N0 to N3 are turned on, and the sub row decoder 100 is in a high state. Therefore, the sub row switch control signals SRS_0 to SRS_3, which are outputs of the sub row decoder 100, are applied to the word line WL.

As described above, the present invention provides the following effects.

First, in the phase change memory device, the structure of the row decoder can be improved to reduce the layout size and simplify the circuit configuration.

Second, by implementing a global word line shared by a plurality of sub-cell array to reduce the line resistance of the global word line and to improve the metal process margin.

Third, the circuit configuration of the global row decoder and sub row switch can be improved and simplified.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (19)

A plurality of subcell arrays including a phase change resistance cell configured to store a data corresponding to a change in resistance by sensing a crystallization state that changes according to a magnitude of a current; A global row decoder line shared by the plurality of subcell arrays; A sub row decoder configured to decode a row address and output a sub row switch control signal; A sub row switch configured to output the sub row switch control signal to the plurality of sub cell arrays according to a voltage level of the global row decoder line; And a global row decoder block configured to select word lines of the plurality of subcell arrays and to control voltage levels of the global row decoder lines according to a word line active signal. The method of claim 1, wherein the global row decoder block A global precharge control unit configured to output a word line precharge signal according to the voltage level of the global row decoder line and the word line active signal; A global row switch for selectively precharging the word line according to the word line precharge signal; And And a global row decoder to decode the row address to select the global row decoder line. The phase change memory device as claimed in claim 2, wherein the global row switch includes a plurality of switching elements connected between the word line and an application end of a word line power source and controlled according to the word line precharge signal. . The phase change memory device as claimed in claim 3, wherein the plurality of switching elements are PMOS transistors. 4. The phase change memory device of claim 3, wherein the plurality of switching elements are bipolar junction transistors. The phase change memory device as claimed in claim 3, wherein the plurality of switching elements are PNPN diode elements. The phase change memory device of claim 3, wherein the word line power source is a pumping voltage. The sub row switch of claim 1, wherein the sub row switch includes a plurality of switching elements connected between the word line and an application terminal of the sub row switch control signal and controlled by a voltage level of the global row decoder line. Phase change memory device. The phase change memory device as claimed in claim 8, wherein the plurality of switching elements are NMOS transistors. The phase change memory device as claimed in claim 8, wherein the plurality of switching elements are bipolar junction transistors. The phase change memory device as claimed in claim 8, wherein the plurality of switching elements are PNPN diode elements. The phase change memory device of claim 1, wherein the global row decoder line is formed on a metal layer having the same level as the word line. The method of claim 1, wherein the phase change resistance cell A phase change resistance element configured to store a data corresponding to a change in resistance by sensing a crystallization state that changes according to the magnitude of the current; And And a diode element connected between the phase change resistance element and the word line. The method of claim 1, wherein the unit cell formed in the global row decoder line A phase change resistance element configured to store a data corresponding to a change in resistance by sensing a crystallization state that changes according to the magnitude of the current; And A diode device connected to the phase change resistance device, And the diode device forms an open state by opening a connection contact with the global row decoder line. A plurality of word lines arranged in a row direction; A plurality of bit lines arranged in a column direction; A plurality of cell arrays formed in an area where the word line and the bit line cross each other and including a phase change resistance cell configured to store a data corresponding to a change in resistance by detecting a crystallization state that changes according to a magnitude of a current; And A global row decoder line shared by the plurality of cell arrays, And the global row decoder line is formed on a metal layer having the same level as the word line. 16. The phase change memory device as claimed in claim 15, wherein the global row decoder line forms an open state by opening a connection contact with the phase change resistance cell. The method of claim 15, wherein the phase change resistance cell A phase change resistance element connected to the bit line; And And a diode element connected between one end of the phase change resistance element and the word line. The method of claim 15, wherein the unit cell formed in the global row decoder line A phase change resistance element connected to the bit line; And A diode device connected to the phase change resistance device, And the diode device forms an open state by opening a connection contact with the global row decoder line. 16. The phase change memory device as claimed in claim 15, wherein one global row decoder line is disposed for each specific number of word lines.

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