KR20090008604A - Test circuit for memory apparatus - Google Patents

Abstract

A test circuit for memory apparatus is provided to produce a plurality of address test mode signals corresponding to a plurality of addresses based on a test information signal successively. A test clock generating part(300) corresponds to a run test signal and an address signal and produces a test clock(SET CLOCK) of a pulse shape. A BENK0 corresponds with the test clock and successively produces a plurality of test mode signals inside and tests a plurality of cell regions. The test clock generating part comprises: a logic gate performing NAND operation to the run test signal outputted from a test mode register set(TMRS) and the address signal inputted from outside; and an inverter inverting the output of the logic gate and producing a test clock. The run test signal is the internal command which is periodically outputted from the test mode register set. While N-bit address(N is the natural number) inputted from outside exists, the address signal is activated.

Description

TEST CIRCUIT FOR MEMORY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a method and an internal configuration for testing the operation of semiconductor memory devices after the manufacture of large capacity semiconductor memory devices.

In a system composed of a plurality of semiconductor devices, the semiconductor memory device is for storing data. When data is requested from a data processing device such as a central processing unit (CPU), the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or at a position corresponding to the address. Stores data provided from the data requesting device.

BACKGROUND OF THE INVENTION As the operating speed of a system composed of semiconductor devices becomes faster and technology related to semiconductor integrated circuits develops, semiconductor memory devices have been required to output or store data at a higher speed. In recent years, there is a continuing demand for semiconductor memory devices that can store more data and execute read and write operations faster. As a result, the design and manufacture of semiconductor memory devices has become more complicated, and the process of testing the manufactured semiconductor memory devices has become complicated and difficult.

1 is a block diagram illustrating a test circuit of a semiconductor memory device according to the prior art.

As illustrated, the semiconductor memory device includes a plurality of banks BANK0 and a test mode signal generator 100.

The test mode signal generator 100 receives a test mode register set (TMRS) signal and an address (ADD <0: i-1>) composed of i bits and tests a plurality of banks in the bank BANK0. The test mode signals (T0, T1, ..., Tn-2, and Tn-1) for controlling the signal are output. The test mode register set signal TMRS is configured to generate and activate test control signals when the semiconductor memory device starts to operate in test mode and generates and activates internal test control signals for performing various test operations. A signal that is activated, such as activation. That is, the test mode register set signal TMRS controls the generation and activation of each test control signal or enables the various test circuits of the semiconductor memory device to accurately recognize the test control signals generated or activated.

Assuming that the total number of bits of the address input to the test mode signal generator 100 is i bits, the total number of test mode signals generated by the test mode signal generator 100 is 2 ⁱ . That is, a natural number in the illustrated test mode signal (Tn-1) n is a 2 ^i. Recently, a semiconductor memory device has a large storage space, and thus the number of addresses is increasing. As a result, in order to test a semiconductor memory device having a large storage space, a plurality of test mode signals corresponding to a plurality of addresses must be generated. Such a test mode signal should be connected to a plurality of banks included in the semiconductor memory device and a plurality of signal transmission lines for connection should be included in the semiconductor memory device.

Many signal transmission lines can cause great difficulties in the design of semiconductor memory devices. For example, if the number of addresses is eight, the number of signal transmission lines is 256, which is 2 ⁸ , and if the number of addresses is more, the number of signal transmission lines also increases rapidly. In addition, a line connected to each bank in the semiconductor memory device from the test mode signal generator 100 may be formed to be much longer than a data line for signal transmission in the bank. In addition, in order to design a signal having a long length in a semiconductor memory device, it is necessary to consider factors that adversely affect signal transmission due to signal interference or parasitic capacitors, which may make it difficult to design a highly integrated semiconductor memory device. have.

The present invention relates to a method and an internal configuration for testing an operation of a semiconductor memory device after fabrication of the semiconductor memory device, and sequentially generates a plurality of address test mode signals corresponding to a plurality of addresses based on one test information signal. It is a feature of the present invention to provide a test device that enables high integration and reduces components for testing in a semiconductor memory device.

According to the present invention, a test clock generator for generating a test clock in a pulse form corresponding to a test execution signal and an address signal and a plurality of test mode signals are sequentially generated in response to the test clock to test a plurality of cell regions. A semiconductor memory device including a bank capable of providing the same is provided.

The present invention also provides a test clock generator for generating a pulsed test clock and a test mode signal generator for sequentially generating and supplying a plurality of test mode signals for testing a plurality of system regions corresponding to the test clocks. It provides a test control circuit comprising.

The semiconductor memory device according to the present invention increases the design and manufacturing margins by reducing the size of the test circuit and the number of signal transmission lines capable of testing a large storage space. Specifically, test errors due to interference between signal transmission lines may be prevented by significantly reducing the number of signal transmission lines instead of a plurality of signal transmission lines required to correspond to a large capacity in the semiconductor memory device. The design limitation of the semiconductor memory device may be overcome due to a process limitation with a plurality of data lines in the semiconductor memory device.

In addition, the number of signal transmission lines outside each bank can be kept constant even as the storage capacity and the number of address bits of the semiconductor memory device increase, so that the semiconductor memory device of various specifications can be easily applied without large design changes. There is this.

A separate circuit and a signal transmission line for conducting an operation test after fabrication of the semiconductor memory device are included in the semiconductor memory device as circuits for performing an operation of a normal semiconductor memory device. According to the present invention, a plurality of address test mode signals corresponding to a plurality of addresses may be sequentially generated based on a test information signal, thereby reducing a component for a test in a semiconductor memory device and enabling a high integration. As a result, it is possible to overcome design limitations of the semiconductor memory device due to process limitations with a plurality of data lines in the semiconductor memory device for normal operation.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a block diagram illustrating a test circuit of a semiconductor memory device according to an embodiment of the present invention.

As illustrated, the semiconductor memory device may include a test clock generator 300 and a test clock SET_CLOCK for generating a pulse-shaped test clock SET_CLOCK in response to the test execution signal TMRS and the address signal ADD_CODE. The bank BANK0 may be configured to sequentially generate a plurality of test mode signals T0, T1,..., T _{n -2} , and T _{n -1} to test a plurality of cell regions. .

Specifically, the test clock generator 300 may include a logic gate that performs a negative AND operation on a test execution signal TMRS output from a test mode register set and an address signal ADD_CODE input from an external device; And an inverter for inverting the output of the logic gate to generate a test clock SET_CLOCK.

Here, the test execution signal TMRS is a signal for notifying generation and activation of internal test control signals for performing various test operations after the semiconductor memory device starts to operate in a test mode. Register set) to control the generation and activation of each test control signal or to allow the various test circuits of the semiconductor memory device to accurately recognize the test control signals generated or activated. The test execution signal TMRS is periodically output from the test mode register set during the test period for testing a cell region including a plurality of cells in the semiconductor memory device. In addition, the address signal ADD_CODE is a signal that can be activated when an external address is input in the semiconductor memory device or when a test of a cell region is in progress, and ORs all bits of the externally input address. This can be done by specifying one of several bits of the address, or by combining two or more.

Each bank BANK0 receiving the test clock SET_CLOCK receives a plurality of test mode signals T0 and T1 corresponding to the number of address bits for controlling the plurality of cell regions and the plurality of cell regions corresponding to the test clock SET_CLOCK. , ..., T _{n -2} , T _{n -1} ) includes a test mode signal generator 200 sequentially generating. The number of test mode signals T0, T1, ..., T _{n -2} , T _{n -1} is determined by the number of address bits as in the prior art. For example, if the number of address bits is i, then the number of test mode signals n is equal to 2 ⁱ .

As illustrated, each bank BANK0 in the semiconductor memory device performs a test on a cell region in response to one test clock SET_CLOCK. That is, the semiconductor memory device can be implemented by including one signal transmission line and one signal input to each bank to perform the test. Therefore, as in the semiconductor memory device according to the related art, the unit cell in the bank becomes larger, so that the number of test mode signals and the number of signal transmission lines do not increase in proportion to the increase in the number of bits of the address input from the outside, but rather the number of bits of the address. One signal line is enough for any number.

FIG. 3 is a waveform diagram illustrating the operation of a test circuit of the semiconductor memory device shown in FIG. 2. Specifically, FIG. 3 illustrates the operation of the test clock generator 300 and the test mode signal generator 200.

As illustrated, a test execution signal TMRS is periodically input to the test clock generator 300 in order to proceed with a test operation. At this time, when the address signal ADD_CODE is in an activated state, the test clock SET_CLOCK becomes a pulse type signal that is periodically activated corresponding to the input of the test execution signal TMRS, and is output to the test mode signal generator 200. . The test mode signal generator 200 outputs test mode signals T0, T1, T2,..., Tn-1 sequentially activated corresponding to the activation time of the test clock SET_CLOCK. In detail, the test mode signal generator 200 counts the number of test clocks SET_CLOCK activated to activate a corresponding test mode signal. Accordingly, the semiconductor memory device may test a plurality of cell regions in each bank BANK0 in response to the test mode signals T0, T1, T2,..., Tn-1 sequentially activated. In addition, the first test mode signal T0 is activated again in response to the (N + 1) th test clock input after the Nth test clock is input.

Through the operations of the test clock generator 300 and the test mode signal generator 200 described above, the semiconductor memory device according to the present invention can test a plurality of cell regions existing in each bank from the outside. One line to transfer the test clock (SET_CLOCK) per bank, greatly reducing the number of signal transmission lines (here n) that must be connected for the transfer of (T0, T1, T2, ..., Tn-1) I can cope with it.

4 is a circuit diagram illustrating an example of the test mode signal generator 200 shown in FIG. 2.

As illustrated, the test mode signal generator 200A includes a loop including a plurality of D flip-flops 210_0 to 210_n−1 that receive the test clock SET_CLOCK from the clock input terminal. Here, the number of D flip-flops is equal to the number of test mode signals T0, T1, ..., T _{n -2} , T _{n -1} .

As illustrated in FIG. 3, the test clock SET_CLOCK output from the test clock generator 300 is input to the clock input terminal of each of the D flip-flops 210_0 to 210_n−1, thereby providing a plurality of test mode signals T0 and T1. , T2, ..., Tn-1) may be sequentially activated in response to the test clock SET_CLOCK.

Initially, the plurality of test mode signals T0, T1, T2, ..., Tn-2 are all initialized to a logic low level '0'. The Nth test mode signal Tn-1 is brought to the logic high level '1'. When the test clock SET_CLOCK is activated, the first D flip-flop 210_0 shifting the Nth test mode signal Tn-1 makes the first test mode signal T0 a logic high level '1'. The N th test mode signal Tn-1 is shifted to the logic low level '0' by shifting the (N-1) th test mode signal Tn-2. This operation is repeated whenever the test clock SET_CLOCK is activated and input.

The initialization values of the plurality of test mode signals T0, T1, T2,..., And Tn-1 described above may be adjusted according to the test environment of the semiconductor memory device. However, the plurality of D flip-flops 210_0 may be configured. At least one of 210_n-1) must be initialized to a logic high level '1'. Before the test, the test execution signal TMRS may be applied as many times as desired to activate the specific test mode signal for the first time. In addition, when the initialization is desired at the time of the test, the reset signal RST may be applied to each of the D flip-flops 210_0 to 210_n-1.

FIG. 5 is a circuit diagram illustrating another example of the test mode signal generator 200 shown in FIG. 2.

As shown, the test mode signal generator 200B outputs the M bit counters 250_0 to 250_m-1 and M bit counters for counting the number of pulses of the test clock SET_CLOCK and the plurality of test mode signals T0. N bit decoder 260 for decoding with T1, T2, ..., Tn-1). Here, when there are N test mode signals, M is equal to or greater than log ₂ N in the M bit counter.

Similarly, the test mode signal generator 200B including the counter also receives the test clock SET_CLOCK output from the test clock generator 300 and uses the M bit counters 250_0 to 250_m-1 to determine the number of pulses. Counts. In response to the number of pulses, the N-bit decoder 260 allows the plurality of test mode signals T0, T1, T2, ..., Tn-1 to be sequentially activated. That is, when the test mode signal generator 200B is initialized, the outputs B0 to Bm-1 of the M bit counters 250_0 to 250_m-1 all output logic low levels '0'. Thereafter, when the pulse of the test clock SET_CLOCK is input, the number is counted and the result of the corresponding M-digit binary number is output to the N-bit decoder 260. The N-bit decoder 260 decodes the M-digit binary result to be input so that the N test mode signals T0, T1, T2, ..., Tn-1 are sequentially activated.

Initialization values of the plurality of test mode signals T0, T1, T2, ..., Tn-1 output from the test mode signal generator 200B may also be adjusted according to the test environment of the semiconductor memory device. , it makes it to make the output of the counter to "0" is applied as per ^m 2 a test clock (SET_CLOCK). In addition, if it is desired to initialize at a desired time point, the reset signal RST is input to each one-bit counter constituting the illustrated M bit counters 250_0 to 250_m-1.

6A and 6B are waveform diagrams for describing an operation of the test mode signal generator 200B illustrated in FIG. 5. As shown in FIG. 3, when the test execution signal TMRS and the address signal ADD_CODE are activated, the test clock SET_CLOCK is periodically activated in response to an input of the test execution signal TMRS. The signal is output to the test mode signal generator 200B. 6A illustrates a case where N is the number of test mode signals and M is equal to log ₂ N in the M bit counter.

The plurality of 1-bit counters 250_0 to 250_m−1 included in the test mode signal generator 200 count an activation time of the test clock SET_CLOCK. Whenever the test clock is activated and input, the output B0 to Bm-1 of the M bit counters 250_0 to 250_m-1 is transferred to the N-bit decoder 260, as shown in the operation of the binary counter. Delivered. The N bit decoder 260 sequentially activates the test mode signals T0, T1, T2, ..., Tn-1 corresponding to the outputs B0 to Bm-1 of the M bit counters 250_0 to 250_m-1. )). Accordingly, the semiconductor memory device may test a plurality of cell regions in each bank BANK0 in response to the test mode signals T0, T1, T2,..., Tn-1 sequentially activated.

6B illustrates a case in which M is greater than log ₂ N in the M bit counter when the number of test mode signals is N unlike in FIG. 6A.

When the test clock SET_CLOCK is input when the test execution signal TMRS and the address signal ADD_CODE are activated, the test mode signal generator 200B sequentially activates the test mode signals T0, T1, T2, ..., Tn-1) is output. As shown, if the number of test mode signals is four and M is greater than log ₂ 4, then no test mode signals T0 to T4 are activated, such as when the fifth test clock is input (TMRS 5th). Do not. That is, when M is greater than log ₂ N, the test mode signal is not activated for a value counted more than the number of test mode signals. After the initialization, the first test mode signal T0 is activated again.

Through the operations of the test clock generator 300 and the test mode signal generator 200 described above, the semiconductor memory device according to the present invention can test a plurality of cell regions existing in each bank from the outside. One line to transfer the test clock (SET_CLOCK) per bank, greatly reducing the number of signal transmission lines (here n) that must be connected for the transfer of (T0, T1, T2, ..., Tn-1) I can cope with it.

As described above, the semiconductor memory device according to the present invention has an advantage of reducing the number of signal transmission lines for delivering a plurality of test mode signals that need to be input for testing a large cell area outside each bank. . There is a drawback that the test time can be a little longer compared to delivering a large number of test mode signals directly outside the bank. However, in recent years, the data storage capacity of semiconductor memory devices has become very large and the number of signal transmission lines for testing them has increased significantly. There is an advantage in overcoming the difficulties in design and manufacturing (lack of design and manufacturing margins).

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a block diagram illustrating a test circuit of a semiconductor memory device according to the prior art.

2 is a block diagram illustrating a test circuit of a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a waveform diagram illustrating the operation of a test circuit of the semiconductor memory device shown in FIG. 2.

FIG. 4 is a circuit diagram for describing an exemplary embodiment of the test mode signal generator illustrated in FIG. 2.

FIG. 5 is a circuit diagram illustrating another embodiment of the test mode signal generator shown in FIG. 2.

6A and 6B are waveform diagrams for describing an operation of the test mode signal generator shown in FIG. 5.

Claims (17)

A test clock generator configured to generate a test clock in a pulse form in response to the test execution signal and the address signal; And And a bank capable of testing a plurality of cell regions by sequentially generating a plurality of test mode signals in response to the test clock. The method of claim 1, The test clock generator A logic gate configured to perform a negative AND operation on the test execution signal output from a test mode register set TMRS and an address signal input externally; And And an inverter configured to invert the output of the logic gate to generate the test clock. The method of claim 2, And the test execution signal is an internal command periodically output from the test mode register set, and the address signal is activated while an externally input N-bit address (N is a natural number) exists. The method of claim 3, wherein And the address signal is generated by ORing all N-bits of an externally input address. The method of claim 3, wherein And the number of the test mode signals is 2 ^N , and the test clock is always one signal regardless of the number of bits of the address. The method of claim 1, The bank is The plurality of cell regions; And And a test mode signal generator configured to sequentially generate a plurality of test mode signals corresponding to the number of address bits for controlling a plurality of cell regions in response to one of the test clocks. The method of claim 6, And the test mode signal generation unit counts an activation time of the test clock and activates a test mode signal corresponding to the number thereof. The method of claim 7, wherein The test mode signal generator includes a loop including a plurality of D flip-flops that receive the test clock from a clock input terminal. The method of claim 8, The number of the D flip-flop is the same as the number of the test mode signal, the semiconductor memory device. The method of claim 7, wherein The test mode signal generator is An M bit counter for counting the number of pulses of the test clock; And And a decoder for decoding the output of the M bit counter into the plurality of test mode signals. The method of claim 10, And N in the M bit counter is greater than or equal to log ₂ N when the test mode signals are N. The method of claim 1, The bank may count cell activation times of the test clocks and test cell regions within the bank corresponding to the number of the test clocks. A test clock generator for generating a pulsed test clock; And And a test mode signal generator for sequentially generating and supplying a plurality of test mode signals for testing a plurality of system regions in response to the test clock. The method of claim 13, The test clock generator A logic gate configured to perform a negative AND operation on a test enable signal and an externally input test region signal; And And an inverter for inverting the output of the logic gate to generate the test clock. The method of claim 14, The test mode signal generator includes a loop including a plurality of D flip-flops that receive the test clock from a clock input terminal. The method of claim 14, The test mode signal generator is A counter for counting the number of pulses of the test clock; And And a decoder for decoding the output of the counter into the plurality of test mode signals. The method of claim 13, And the test mode signal generation unit counts an activation time of the test clock and activates a test mode signal corresponding to the number thereof.

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