KR20090008564A - An array substrate of liquid crystal display device and the method for fabricating thereof - Google Patents

Abstract

An array panel for a liquid crystal display and a manufacturing method thereof are provided to solve the lift-off process fault by inducing the penetration of stripper to the protrusions of pixel electrode. N and n-1 gate wirings(120a, 120b) are comprised in the substrate(100). The n, and the n+1 data lines(130a, 130b) are comprised on the substrate for defining pixel region. A thin film transistor(T) is placed at the crossing point of the n data line(130a) and the n gate wiring(120a). A pixel electrode(170) which is extended from the drain electrode(138) is comprised corresponds to the pixel region. The pixel electrode is extended in order to be overlapped with n-1 gate wiring.

Description

An array substrate for a liquid crystal display device and a method of manufacturing the same {An Array Substrate of Liquid Crystal Display Device and the method for fabricating

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to improving a defect caused by a lift-off process, which is a core process of an array substrate for a three mask liquid crystal display device.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display (AM-LCD) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and ability to implement video.

Hereinafter, a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a plan view illustrating a unit pixel of a conventional array substrate for a liquid crystal display device.

As shown, the n-th and n-th gate lines 20a and 20b spaced in parallel in one direction on the substrate 10, and the n-th and n-th gate lines 20a and 20b, respectively. The nth and nth + 1th data lines 30a and 30b are formed in the direction perpendicular to each other.

In this case, an area defined by the n-th and n-th gate lines 20a and 20b and the n-th and n-th data lines 30a and 30b cross each other is referred to as a pixel area P. FIG.

A thin film transistor T is formed at an intersection point of the nth gate line 20a and the nth data line 30a. The thin film transistor T includes a gate electrode extending from the nth gate line 20a. 25, an active layer 40 overlapping with the gate electrode 25, an ohmic contact layer (not shown) on the active layer 40, and an n-th data line 30a. And a drain electrode 34 spaced apart from the source electrode 32.

The active layer 40 is made of pure amorphous silicon (a-Si: H), and the ohmic contact layer (not shown) is made of impurity amorphous silicon (n + a-Si: H). At this time, the active layer 40 and the ohmic contact layer (not shown) to form a semiconductor layer (not shown).

The pixel electrode 70 extending in the same pattern as the drain electrode 34 is configured to correspond to the pixel region P. As shown in FIG. In this case, the pixel electrode 70 is spaced apart from the n-th and n-th gate lines 20a and 20b and the n-th and n-th data lines 30a and 30b at regular intervals, and the pixel region ( It is common to be comprised in rectangular shape corresponding to P).

2A and 2B are cross sectional views taken along the line II-II of FIG. 1, illustrating the lift-off process step.

As shown in FIG. 2A, the gate insulating film 45 is formed on the substrate 10, and the n-th data wire 30a and the n-th +1 data wire 30b are formed on both sides of the gate insulating film 45. Each is composed. The pixel electrode 70 is formed corresponding to the space between the nth and nth + 1th data lines 30a and 30b.

In this case, the n-th and n-th data lines 30a and 30b and the pixel electrode 70 may be formed of a double layer in which a transparent conductive metal layer 70a and a source and drain metal layer 75 are sequentially stacked.

First and second passivation patterns 55 and 56 are formed on the nth and n + 1th data lines 30a and 30b, respectively, and a photosensitive pattern made of a photosensitive material corresponding to an upper portion of the pixel electrode 70 ( 72 and the third protective film pattern 57 are sequentially laminated. In this case, a part of the lower surface of the photosensitive pattern 72 at both ends of the pixel electrode 70 is exposed.

Next, as shown in FIG. 2B, a lift-off using a stripper to simultaneously remove the photosensitive pattern 72 of FIG. 2A and the third passivation pattern 57 (FIG. 2A). As the process proceeds, the stripper penetrates into the lower surface of the exposed photosensitive pattern (72 of FIG. 2A), thereby replacing the photosensitive pattern (72 of FIG. 2A) and the third passivation pattern (57 of FIG. 2A). At the same time, the pixel electrode 70 positioned under the third passivation layer pattern 57 of FIG. 2A is exposed.

Next, the source and drain metal layers (75 of FIG. 2A) positioned at the top of the pixel electrode 70 are removed to be made of a transparent conductive metal.

However, in the lift-off process using the stripper described above, the stripper penetrates from four corners of the pixel electrode 70.

In detail, referring to FIG. 1 and FIG. 2A, the rectangular pixel electrode 70 described above has four side lengths, in particular, between the nth data line 30a and the n + 1th data line 30b. When the length of the corresponding pixel electrode 70 is designed to be 200 μm or more, the result is that the stripper does not penetrate to the center portion of the pixel electrode 70, and thus the photosensitive pattern 72 corresponding to the portion It is a situation that the second protective film pattern 56 is not removed and causes a lift-off process defect that remains, which serves as an obstacle to fabricating the array substrate for the liquid crystal display device in the three mask process.

When such a lift-off process defect occurs, a problem occurs that the remaining photosensitive pattern 72 and the liquid crystal (not shown) react to cause image quality defects such as afterimages.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to fabricate an array substrate for a liquid crystal display using a three mask process by more efficiently performing a lift-off process through a change in pixel design.

In addition, another object of the present invention is to be able to proceed the lift-off process more efficiently by forming a protective film pattern using a sputtering method.

According to an exemplary embodiment of the present invention, an array substrate for a liquid crystal display device includes a substrate, a plurality of gate wirings spaced apart in parallel in one direction on the substrate, and a pixel region vertically crossing the plurality of gate wirings. A plurality of data lines having protrusions in the direction of the pixel region, a gate electrode which is a part of the gate lines, a semiconductor layer in which the gate electrode and a portion thereof overlap at an intersection point of the gate lines and the data lines; A source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and a drain electrode extending in the same pattern as the drain electrode and having a protrusion of the data line corresponding to the pixel area. A pixel electrode is included.

At this time, the protruding portion of the data line is not more than half the length of the gate line corresponding to the pixel area at a position that is divided into three distances between the gate line and the front gate line located at the front end of the gate line. It is characterized by consisting of protrusions.

In addition, the protrusion of the data line is configured to protrude to the right or left side of the pixel area, and the pixel electrode has a plurality of corners formed by the indentation and the protrusion of the pixel electrode.

The pixel electrode is configured to extend so as to overlap the gate wiring at the front end, and a storage capacitor having the gate wiring at the front end as the first electrode and the pixel electrode superimposed thereon as the second electrode is configured.

In this case, the plurality of gate lines may further include protrusions extending in the pixel area direction.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: preparing a substrate divided into a switching region, a pixel region, and a data region; A first mask process step of forming a plurality of gate wirings and a gate electrode which is a part of the plurality of gate wirings;

Forming a gate insulating film on the substrate on which the plurality of gate wirings and the plurality of gate electrodes are formed, and forming an island-shaped semiconductor layer on which the gate electrode and a portion of the gate electrode on the substrate including the gate insulating film overlap A second mask process step;

A plurality of data wires vertically intersecting with the plurality of gate wires on the substrate including the semiconductor layer and having protrusions in the pixel area direction, and at a position where the gate electrode and a portion thereof overlap each other; An extended source electrode, a drain electrode spaced apart from the source electrode, and a pixel electrode extending in the same pattern as the drain electrode and including an indentation and a protrusion by a protrusion of the data line corresponding to the pixel area; And forming a first to fourth passivation layer pattern on the substrate on which the plurality of data lines, the source and drain electrodes, and the pixel electrode are formed by using a sputtering method. It is done.

At this time, the protruding portion of the data line is not more than half the length of the gate line corresponding to the pixel area at a position that is divided into three distances between the gate line and the front gate line located at the front end of the gate line. It is characterized by consisting of protrusions.

The protrusion of the data line may protrude to the right or left side of the pixel area, and the pixel electrode may have a plurality of edges formed by the indentation and the protrusion of the pixel electrode.

The pixel electrode is formed to extend so as to overlap the gate wiring at the front end, and a storage capacitor having the gate wiring at the front end as the first electrode and the pixel electrode superimposed thereon as the second electrode is formed.

The third mask process may include forming a transparent conductive metal layer, a source and a drain metal layer, and a photosensitive layer on the substrate including the semiconductor layer in order, and the switching region on the spaced apart portion of the photosensitive layer. Aligning a mask comprising transmissive portions between the transflective portions on both sides corresponding to the transmissive portions, a blocking portion corresponding to the pixel region, a transflective portion corresponding to the data region, and all other portions except the transmissive portions; Performing exposure and development steps toward the substrate to form first to fourth photosensitive patterns;

By performing an isotropic wet etching process using the first to fourth photosensitive patterns as a mask, a plurality of source and drain electrodes correspond to the switching region, a pixel electrode corresponding to the pixel region, and a plurality of data regions corresponding to the data region. Forming a data line and abutting the first to fourth photosensitive patterns to remove the first photosensitive pattern and the third and fourth photosensitive patterns, wherein the second photoresist corresponds to the pixel region. The photosensitive pattern is reduced in height by about half;

Forming first to fourth passivation layer patterns on the substrate including the second photosensitive pattern by sputtering; and lifting off the second photosensitive pattern and the second passivation layer pattern corresponding to the pixel region. And removing the pixel electrode to expose the lower portion of the pixel electrode.

The first to fourth photosensitive patterns may be formed to correspond to the upper portions of the source and drain electrodes, the pixel electrode, and the plurality of data lines, respectively.

And removing the source and drain metal layers positioned at the top of the pixel electrode.

Therefore, the present invention can, firstly, improve the leaf off capability by changing the pixel design.

Second, it is possible to minimize the lift off process failure through the sputtering method.

Third, the aperture ratio may be secured by reducing the overlapping area of the first and second electrodes of the storage capacitor.

Fourth, the production yield can be improved by manufacturing an array substrate for a liquid crystal display using a three mask process.

--- Example ---

The present invention is characterized in that the defects caused by the lift-off process can be improved through a pixel design capable of efficiently carrying out the lift-off process, which is the core of the three mask process.

Specifically, a plurality of gate wires and a plurality of data wires defining a pixel area perpendicularly intersecting with the plurality of gate wires and having a protrusion in the pixel area direction correspond to the indentation and the protrusion in correspondence with the pixel area. To configure a pixel electrode comprising a.

In addition, another feature is that the lift-off process can be performed more efficiently by forming a protective film pattern using a sputtering method.

Hereinafter, a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

3 is a plan view illustrating unit pixels of an array substrate for a liquid crystal display according to the present invention.

As shown, the n-th and n-th gate wirings 120a and 120b are formed on the substrate 100 in one direction and vertically intersect the n-th and n-th gate wirings 120a and 120b. The n-th and n-th data lines 130a and 130b defining the pixel region P are formed.

In this case, the n-th data line 130a may include first and second vertical portions 131a and 132a respectively corresponding to regions perpendicular to the n-th and n-th gate lines 120a and 120b, respectively. First and second protrusions extending from the first and second vertical portions 131a and 132a toward the pixel region P and vertically spaced apart in a direction parallel to the n-th and n-th gate lines 120a and 120b; The second horizontal portion 133a and 134a and the third vertical portion 135a connecting the first and second horizontal portions 133a and 134a into one are included.

In addition, the n + 1th data line 130b may include the fourth and fifth vertical portions 131b and 132b respectively corresponding to regions perpendicular to the nth and n−1th gate lines 120a and 120b. And protruding and extending from the fourth and fifth vertical parts 131b and 132b toward the pixel region P and vertically spaced apart in a direction parallel to the n-th and n-th gate lines 120a and 120b. And a sixth vertical portion 135b connecting the third and fourth horizontal portions 133b and 134b and the third and fourth horizontal portions 133b and 134b into one.

In this case, the first and second horizontal parts 133a and 134a and the third and fourth horizontal parts 133b and 134b divide the separation distances of the nth and n-th gate lines 120a and 120b by three. In this case, the protrusion may be formed in a range not exceeding half of the length of the n-th and n-th gate lines 120a and 120b corresponding to the pixel region P.

In this case, the first and second horizontal parts 133a and 134a and the third and fourth horizontal parts 133b and 134b are formed of the first and second vertical parts 131a and 132a and the fourth and fifth vertical parts. Although it is configured to protrude to the right on the basis of each of (131b, 132b), it may be configured to protrude in the left direction symmetrical to this.

A thin film transistor T is formed at an intersection point of the n-th gate line 120a and the n-th data line 130a. The thin film transistor T is a gate electrode that is a part of the n-th gate line 120a. 125, a semiconductor layer (not shown) overlapping the gate electrode 125 and a portion thereof, and having an island shape, and a U-shape extending from the n-th data line 130a on the semiconductor layer (not shown). And a drain electrode 138 configured to be spaced apart from the source electrode 136 and to be engaged with each other therein.

The semiconductor layer (not shown) includes an active layer 140 made of pure amorphous silicon (a-Si: H), an ohmic contact layer (not shown) made of impurity amorphous silicon (n + a-Si: H), and a buffer pattern. (Not shown).

In this case, in order to improve ohmic contact of the source and drain electrodes 136 and 138, the buffer pattern (not shown) may be formed between the source and drain electrodes 136 and 138 and the ohmic contact layer (not shown). The buffer pattern (not shown) preferably comprises molybdenum (Mo) having a thickness of 50 kPa.

The pixel electrode 170 extending in the same pattern from the drain electrode 138 is configured to correspond to the pixel region P. Referring to FIG. The pixel electrode 170 is in a state in which an opaque conductive metal is removed and only a transparent conductive metal is present.

The pixel electrode 170 extends to overlap the n-th gate line 120b positioned at the front end of the n-th gate line 120a, so that the n-th gate line 120b is firstly formed. The storage capacitor Cst is configured as an electrode and the pixel electrode 170 superimposed thereon is used as a second electrode.

The pixel electrode 170 is spaced apart from the n-th and n-th gate lines 120a and 120b and the n-th and n + 1th data lines 130a and 130b corresponding to the pixel region P. FIG. Configure to be spaced apart.

Here, the pixel electrode 170 has an indentation F formed corresponding to the first and second horizontal portions 133a and 134a and the third vertical portion 135a of the n-th data line 130a. The protrusion H is formed corresponding to the third and fourth horizontal portions 133b and 134b and the sixth vertical portion 135b of the n + 1th data wire 130b.

Unlike the conventional rectangular pixel electrode 70 of FIG. 1, the above-described configuration secures a plurality of edges to the pixel electrode 170 through the indentation F and the protrusion H of the pixel electrode 170. There is an advantage to this.

Such a configuration is assumed to be the same area as that of the conventional pixel electrode 70 of FIG. 1. The pixel electrode 170 is formed by the indentation F and the protrusion H of the pixel electrode 170. Since the corresponding length between the sides facing each other is greatly reduced, there is an advantage that the lift off process can be carried out more efficiently. In addition, the above-described configuration has an advantage that the stripper can easily penetrate to the center portion of the pixel electrode 170 through a plurality of edges.

Therefore, in the present invention, not only the length corresponding to the side of the pixel electrode 170 configured to correspond to the pixel region P and the side between the sides can be reduced, but also the number of the n th data line 130a can be reduced. Even if the length corresponding to the side of the pixel electrode 170 corresponding to the sixth vertical portion 135b of the third vertical portion 135a and the n + 1th data line 130b is 200 μm or more, the majority By the edges of the lift off process failure can be eliminated.

In addition, although not shown in detail in the drawings, it can be designed to have a symmetrical structure with the above-described pixel design, which will be described in the vertical configuration of the n-th and n + 1th data lines 130a and 130b in a straight line form. The n-th and n-th gate lines 120a and 120b extending along the n-th and n + 1th data lines 130a and 130b to define the pixel region P extend in the direction of the pixel region P. It may be configured to have a protrusion (not shown) in the n-th and n-th gate wirings (120a, 120b).

The n-th and n-th data lines 130a and 130b and the n-th and n-th gate lines 120a and 120b may have protrusions (not shown).

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention will be described in detail.

The method of manufacturing an array substrate for a liquid crystal display device according to the present invention proceeds to a three mask process step.

4A to 4H and FIGS. 5A to 5H are cross-sectional views illustrating a process sequence by cutting along lines IV-IV and V-V of FIG. 3, respectively.

4A and 5A are cross-sectional views illustrating a first mask process step.

As shown in FIGS. 4A and 5A, the step of defining the switching region S, the pixel region P, and the data region D on the substrate 100 is performed.

The gate metal layer is selected from a group of conductive metals such as copper (Cu), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) on the substrate 100 in which the plurality of regions S, P, and D are defined. (Not shown) are formed and patterned to form an n-th gate line (120a in FIG. 3) and an n-th gate line (120b in FIG. 3) in one direction. In this case, a portion of the nth gate line 120a of FIG. 3 corresponding to the switching region S is used as the gate electrode 125.

Next, an inorganic material, such as silicon nitride (SiNx) and silicon oxide (SiO ₂ ), may be formed on the substrate 100 on which the gate electrode 125 and the n-th and n-th gate wirings 120a and 120b of FIG. 3 are formed. A gate insulating layer 145 is formed by depositing one selected from the group of insulating materials.

4B and 5B are cross-sectional views illustrating a second mask process step.

As shown in FIGS. 4B and 5B, a pure amorphous silicon layer (not shown), an impurity amorphous silicon layer (not shown), and a buffer metal layer (not shown) are formed on the substrate 100 on which the gate insulating layer 145 is formed. Lamination is formed in turn. In this case, the buffer metal layer preferably forms molybdenum to a thickness of 50 kPa.

Next, the pure and impurity amorphous silicon layer (not shown) and the buffer metal layer (not shown) are collectively patterned, and the island in which the gate electrode 125 and a portion thereof overlap with the switching region S is formed. A semiconductor layer 143 having a shape is formed.

In this case, the semiconductor layer 143 may include a triple layer in which an active layer 140 made of pure amorphous silicon, an ohmic contact layer 141 made of impurity amorphous silicon, and a buffer pattern 142 made of molybdenum are stacked. Have

4C to 4H and 5C to 5H are cross-sectional views illustrating a third mask process step.

As shown in FIGS. 4C and 5C, a transparent conductive metal group, such as indium tin oxide (ITO) or indium zinc oxide (IZO), may be formed on the substrate 100 including the semiconductor layer 143. A transparent conductive metal layer 170a is formed with one selected.

On the substrate 100 on which the transparent conductive metal layer 170a is formed, copper (Cu), molybdenum (Mo), molybdenum alloy (MoTi), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) and Since the source and drain metal layers 175 are formed of one or more selected from the same conductive metal group, it is preferable to use copper (Cu) having low resistance and excellent electrical conductivity.

Next, a photoresist is formed on the substrate 100 on which the transparent conductive metal layer 170a and the source and drain metal layers 175 are formed to form the photosensitive layer 180, and the transmissive portion A and the upper portion spaced apart therefrom. The halftone mask HTM including the transflective portion B and the blocking portion C is aligned.

The halftone mask HTM forms a translucent film on the transflective portion B to lower the intensity of light or to reduce the amount of light transmitted so that the photosensitive layer 180 may be incompletely exposed. In this case, in addition to the halftone mask HTM, a slit mask may be used to control the amount of light transmitted by placing a slit shape on the transflective portion B.

In addition, the blocking unit (C) is a function to block the light completely, the transmission unit (A) is a function to transmit the light so that the photosensitive layer 180 exposed to the light causes a chemical change to be fully exposed. do.

At this time, the blocking part C corresponding to the pixel area P and the transmissive part A between the transflective parts B on both sides corresponding to the switching area S are half corresponding to the data area D. The transmissive portion B, and all areas except this, are aligned so that the transmissive portion A is located.

Next, as shown in FIGS. 4D and 5D, the process of exposing and developing the upper portion spaced apart from the halftone mask (HTM of FIGS. 4C and 5C) is performed. The photosensitive layer (180 in FIG. 4C) corresponding to the transmissive portion (A in FIG. 4C) between the transflective portions (B in FIG. 4C) on both sides is removed, and the source and drain metal layers 175 thereunder are exposed, and A portion of the photosensitive layer (180 of FIG. 4C) corresponding to the semi-transmissive portion (B of FIG. 4C) on both sides is removed, leaving the first photosensitive pattern 182 having a lowered height on both sides.

Then, the photosensitive layer corresponding to the pixel region P (180 of FIGS. 4C and 5C) remains as it is, leaving the second photosensitive pattern 183, and the photosensitive layer corresponding to the data region D (FIG. The portions 180 of 5c may be partially removed to leave the third and fourth photosensitive patterns 184 and 185 having a lowered height, respectively, and all of the photosensitive layers (180 of FIGS. 4c and 5c) except for this may be removed. The source and drain metal layer 175 beneath it is exposed.

Next, as shown in FIGS. 4E and 5E, using the first to fourth photosensitive patterns 182 to 185 as masks, the exposed source and drain metal layers (175 of FIGS. 4D and 5D) and The process of collectively patterning the transparent conductive metal layer (170a of FIGS. 4D and 5D) is performed to form source and drain electrodes 136 and 138 spaced apart from both sides in correspondence to the switching region S. The pixel electrode 170 is formed to correspond to the pixel area P.

At the same time, the n-th data line 130a and the n-th + 1th data line 130b are formed to correspond to the data area D, respectively.

In this case, the above-described pattern process is a source and drain metal layer (175 in Figs. 4d and 5d) and a transparent conductive metal layer (under the first to fourth photosensitive patterns 182 to 185) using a wet etching having an isotropic property 170a of FIGS. 4D and 5D are overetched to partially expose the lower edges of the first to fourth photosensitive patterns 182 to 185.

That is, the source and drain electrodes 136 and 138, the pixel electrode 170, and the n-th and n-th data lines 130a and 130b may be formed at both ends of each wire by a wet etching process having the above-described isotropy. A portion is over-etched, and the first to fourth photosensitive patterns 182 to 185 are partially etched at both ends of the first to fourth photosensitive patterns 182 to 185. It is exposed.

The above configuration has an advantage that a stripper can easily penetrate the exposed edge lower surface of the first to fourth photosensitive patterns 182 to 185, particularly the second photosensitive pattern 183.

The source and drain electrodes 136 and 138, the pixel electrode 170, and the n-th and n + 1 data lines 130a and 130b may be formed by stacking a transparent conductive metal layer 170a and a source and drain metal layer 175. It is formed into a double layer. In addition, the pixel electrode 170 extends to overlap the n-th gate line 120a of FIG. 3.

 Next, using the first to fourth photosensitive patterns 182 to 185 as a mask, the buffer patterns exposed between the source and drain electrodes 136 and 138 spaced apart from each other corresponding to the switching region S Patterning the 142 and the ohmic contact layer 141 is performed.

In the above-described pattern process, the buffer pattern 142 and the ohmic contact layer 141 are separated at both sides in the same width as the source and drain electrodes 136 and 138. In this case, a portion of the active layer 140 exposed to the lower portion of the ohmic contact layer 141 separated on both sides is overetched to use this portion as a channel ch.

Here, the gate electrode 125, the source and drain electrodes 136 and 138, the buffer pattern 142, and the active and ohmic contact layers 140 and 141 form a thin film transistor (T).

Next, as shown in FIGS. 4F and 5F, the remaining first to fourth photosensitive patterns (182 to 185 of FIGS. 4E and 5E) are processed.

 When the ashing process described above is performed, the second photosensitive pattern 183 corresponding to the pixel region P is lowered by about half of the height, and is formed in the switching region S and the data region D. The corresponding first photosensitive pattern (182 of FIG. 4E) and the third and fourth photosensitive patterns (184, 185 of FIG. 5E) are respectively removed so that the first photosensitive pattern (182 of FIG. 4E) and the third and third The source and drain electrodes 136 and 138 and the n-th and n-th data lines 130a and 130b corresponding to the lower portions of the fourth photosensitive patterns 184 and 185 of FIG. 5E are exposed.

Next, as shown in FIGS. 4G and 5G, one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride on the substrate 100 including the remaining second photosensitive pattern 183. A process of forming the fourth passivation layer patterns 155, 156, 157, and 158 is performed.

In general, the first to fourth passivation layer patterns 155 to 158 are formed by a plasma chemical vapor deposition method using an inorganic insulating material.

However, a high temperature process of 350 ° C. or higher is required in the deposition process using the plasma chemical vapor deposition method. In particular, a second photosensitive pattern 183 formed of an organic insulating material having photosensitive characteristics under the second protective layer pattern 156. ), The heat resistance is only up to about 150 ° C., so that the second photosensitive pattern 183 may be pressed or deformed.

When the first to fourth passivation layer patterns 155 to 158 are continuously deposited in the above-described problem state, the second photosensitive pattern 183 eventually forms the first to fourth passivation layer patterns 155 to 158. ), The stripper may not penetrate during the lift-off process, which may cause the lift-off defect in which the second photosensitive pattern 183 and the second passivation pattern 156 remain. have.

When the lift-off process failure occurs, the remaining second photosensitive pattern 183 may react with the liquid crystal to generate a poor image quality such as an afterimage.

In order to solve this problem, the present invention is characterized in that the first to fourth passivation layer patterns 155 to 158 are formed using a sputtering method.

When the sputtering method is used, the second photosensitive pattern 183 may be deposited at a temperature lower than 150 ° C., which is lower than the heat resistance of the second photosensitive pattern 183, so that the second photosensitive pattern 183 may not be pressed or deformed. There is an advantage that can be applied to a flexible substrate such as plastic.

In this case, the first passivation layer pattern 155 may cover the source and drain electrodes 136 and 138, and the third and fourth passivation layer patterns 157 and 158 may include the nth and nth + 1th data lines 130a, 130b) respectively. The second passivation layer pattern 156 covers a portion of an upper side of the second photosensitive pattern 183, and a portion corresponding to both edges due to a step of the second photosensitive pattern 183 and a lower portion of the edge thereof. There is no deposition on the surface.

Next, as shown in FIGS. 4H and 5H, when the lift-off process using the stripper is performed, the stripper penetrates into the exposed portion of the edge lower surface of the second photosensitive pattern 183, and the second The photosensitive pattern 183 and the second passivation layer pattern 156 covering the second photosensitive pattern 183 are removed together to expose the pixel electrode 170. The first passivation layer pattern 155 and the third and fourth passivation layer patterns 157 and 158 are present as they are.

3, the length corresponding to the side of the pixel electrode 170 facing each other by the indentation F and the protrusion H of the pixel electrode 170 according to the present invention. Significantly reducing the efficiency of the lift-off process can be carried out.

In addition, in the present invention, a plurality of edges can be secured by the indentation F and the protrusion H of the pixel electrode 170. The stripper easily penetrates to the center of the pixel electrode 170 through this portion. As a result, the lift-off process can be performed more efficiently.

In this case, the pixel electrode 170 is in a state in which the transparent conductive metal layer 170a and the source and drain metal layers 175 are stacked.

Next, in the pattern process using the first passivation layer pattern 155 and the third and fourth passivation layer patterns 157 and 158 as a mask, the source and drain metal layers 175, which are the uppermost layers of the pixel electrode 170b, are removed. Thus, the pixel electrode 170 made of a transparent conductive metal is formed.

In other words, the drain electrode 134 is formed by stacking the source and drain metal layers 175 and the transparent conductive metal layer 170a and extends from the drain electrode 134 to correspond to the pixel region P. Reference numeral 170 is a state made of only a transparent conductive metal.

In this case, the pixel electrode 170 extends to overlap the n-th gate line 120b to make the n-th gate line 120b a first electrode, and the pixel electrode 170 overlaps with the n-th gate line 120b. Is a second electrode, and a storage capacitor Cst is formed using the gate insulating layer 145 interposed between the first and second electrodes as a dielectric layer.

Since the above-described storage capacitor uses only the gate insulating layer 145 as the dielectric layer, the storage capacitor has an advantage of reducing the overlap area of the first and second electrodes.

As described above, the array substrate for the liquid crystal display device according to the present invention may be manufactured in the three mask process through the above-described process.

As described above, in the present invention, the defect of the lift-off process can be minimized by forming the protective film pattern using the sputtering method, and the lift-off capability can be maximized by changing the pixel design.

1 is a plan view showing a unit pixel of a conventional array substrate for a liquid crystal display device.

2A and 2B are cross-sectional views taken along the line II-II of FIG. 1.

3 is a plan view showing unit pixels of an array substrate for a liquid crystal display according to the present invention;

FIGS. 4A to 4H and FIGS. 5A to 5H are cross-sectional views taken along lines IV-IV and V-V of FIG. 3 and shown in a process sequence.

* Explanation of symbols for the main parts of the drawings *

100 substrate 120a nth gate wiring

120b: n-th gate wiring 125: gate electrode

130a: nth data wire 130b: nth + 1 data wire

131a, 132a: first and second vertical portions 131b, 132b: fourth and fifth vertical portions

133a, 134a: first and second horizontal portions 133b, 134b: third and fourth horizontal portions

135a, 135b: third and sixth vertical portions 136: source electrode

138: drain electrode 140: active layer

170: pixel electrode F: indentation

H: protrusion P: pixel area

Claims (14)

A substrate; A plurality of gate lines spaced apart in parallel in one direction on the substrate; A plurality of data lines defining a pixel area perpendicular to the plurality of gate lines and having protrusions in the pixel area direction; A gate electrode which is a part of the gate wiring, a semiconductor layer overlapping the gate electrode and a portion thereof, a source electrode extending from the data wiring, and a spaced apart from the source electrode at an intersection point of the gate wiring and the data wiring A drain electrode; A pixel electrode extending in the same pattern as the drain electrode and including an indentation and a protrusion by the protrusion of the data line corresponding to the pixel region; Array substrate for a liquid crystal display device comprising a. The method of claim 1, The protruding portion of the data line is protruded in a range not more than half of the length of the gate line corresponding to the pixel area at a position that is divided into three distances between the gate line and the front gate line positioned at the front end of the gate line. An array substrate for a liquid crystal display device, characterized in that. The method of claim 1, And the protrusion of the data line is configured to protrude to the right or left side of the pixel area. The method of claim 1, And a plurality of corners of the pixel electrode formed by the indentation and the protrusion of the pixel electrode. The method of claim 1, The pixel electrode is configured to extend so as to overlap the gate wiring at the front end, and a storage capacitor having the gate wiring at the front end as the first electrode and the pixel electrode as the second electrode superimposed thereon is configured. Array substrate for. The method according to claim 1, wherein And the gate lines further include protrusions extending in the pixel area direction. Preparing a substrate divided into a switching region, a pixel region, and a data region; A first mask process step of forming a plurality of gate lines spaced in parallel in one direction on the substrate and a gate electrode which is a part of the plurality of gate lines; Forming a gate insulating film on the substrate on which the plurality of gate lines and the plurality of gate electrodes are formed; A second mask process step of forming an island-shaped semiconductor layer on which the gate electrode and a portion thereof overlap on the substrate including the gate insulating film; A plurality of data wires vertically intersecting with the plurality of gate wires on the substrate including the semiconductor layer and having protrusions in the pixel area direction, and at a position where the gate electrode and a portion thereof overlap each other; An extended source electrode, a drain electrode spaced apart from the source electrode, and a pixel electrode extending in the same pattern as the drain electrode and including an indentation and a protrusion by a protrusion of the data line corresponding to the pixel area; Making a step; A third mask process step of forming first to fourth passivation layer patterns on the substrate on which the plurality of data lines, the source and drain electrodes, and the pixel electrode are formed by sputtering; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 7, wherein The protruding portion of the data line is protruded in a range not more than half of the length of the gate line corresponding to the pixel area at a position that is divided into three distances between the gate line and the front gate line positioned at the front end of the gate line. A method of manufacturing an array substrate for a liquid crystal display device, characterized in that. The method of claim 7, wherein The protrusion of the data line is formed to protrude to the right or left side of the pixel area. The method of claim 7, wherein And a plurality of corners of the pixel electrode are formed by the indentation and the protrusion of the pixel electrode. The method of claim 7, wherein The pixel electrode extends to overlap the gate wiring at the front end, and a storage capacitor is formed so that the gate wiring at the front end is the first electrode, and the storage capacitor is formed as the second electrode. Method of manufacturing an array substrate for use. The method of claim 6, The third mask process step, Sequentially forming a transparent conductive metal layer, a source and a drain metal layer, and a photosensitive layer on the substrate including the semiconductor layer; A mask comprising a transmissive portion between the transflective portions on both sides of the upper portion spaced apart from the photosensitive layer, a transmissive portion corresponding to the pixel region, a transflective portion corresponding to the data region, and all portions except the transmissive portion Sorting; Performing exposure and development processes in the direction of the substrate on the mask to form first to fourth photosensitive patterns; By performing an isotropic wet etching process using the first to fourth photosensitive patterns as a mask, a plurality of source and drain electrodes correspond to the switching region, a pixel electrode corresponding to the pixel region, and a plurality of data regions corresponding to the data region. Forming a data line; The first to fourth photosensitive patterns are removed, and the first photosensitive pattern and the third and fourth photosensitive patterns are removed, and the second photosensitive pattern corresponding to the pixel region is about half lower in height. Losing step; Forming first to fourth passivation layer patterns on the substrate including the second photosensitive pattern by sputtering; Removing the second photosensitive pattern and the second passivation layer pattern corresponding to the pixel region by a lift-off process to expose the lower pixel electrode; Method of manufacturing an array substrate for a liquid crystal display device further comprising. The method of claim 12, And the first to fourth photosensitive patterns are formed in correspondence with the source and drain electrodes, the pixel electrode, and the plurality of data lines, respectively. The method of claim 12, And removing the source and drain metal layers positioned on the top of the pixel electrode.

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