KR20090006359A - Circuit and method for controlling column redundancy in semiconductor memory apparatus - Google Patents

Circuit and method for controlling column redundancy in semiconductor memory apparatus Download PDF

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Publication number
KR20090006359A
KR20090006359A KR1020070069621A KR20070069621A KR20090006359A KR 20090006359 A KR20090006359 A KR 20090006359A KR 1020070069621 A KR1020070069621 A KR 1020070069621A KR 20070069621 A KR20070069621 A KR 20070069621A KR 20090006359 A KR20090006359 A KR 20090006359A
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South Korea
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address
command
buffering
latch
semiconductor memory
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KR1020070069621A
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Korean (ko)
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구철희
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주식회사 하이닉스반도체
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Publication of KR20090006359A publication Critical patent/KR20090006359A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A circuit and method for controlling column redundancy in semiconductor memory apparatus is provided to improve the area efficiency by setting up the fuse set unit in the peripheral circuit redundancy control unit. In a circuit and method for controlling column redundancy in semiconductor memory apparatus, an address buffer(302) outputs the buffering address(add buf(1:n)). A command buffer(304) outputs the buffering command(cmd buf), and the first flip flop(306) produces the first latch address(add lat1(1:n)). A row selection part(308) produces the second latch address(add lat2(1:j)). A fuse set unit(310) outputs the repair identification signal(rpa) and fuse circuit signal(fs(1:n)). A first delay unit(312) outputs the delayed buffer ring address(add bufd(1:n)). A second delay unit(314) outputs the delayed buffer ring command(cmd bufd). A second flip flop(316) latches the delayed buffer ring address the clock(clk). A third flip flop(318) latches the delayed buffer ring command. A global address generating unit(320) produces the global address(add glb(1:n+1)).

Description

Circuit and Method for Controlling Column Redundancy in Semiconductor Memory Apparatus

The present invention relates to a column redundancy control circuit and method of a semiconductor memory device, and more particularly, to a column redundancy control circuit and method of a semiconductor memory device for improving the area efficiency.

In general, a semiconductor memory device includes a large number of memory cells, and when a defect occurs in any one of the memory cells, the semiconductor memory device malfunctions. Therefore, when a defect occurs in a cell, a redundancy control circuit for recognizing it through a test and then accessing the corresponding cell when a request for access to the corresponding cell occurs is used to switch the connection to a cell included in the redundancy circuit instead of the defective cell. Here, the redundancy circuit is a set of extra memory cells provided separately in the memory cells, and is used as a replacement cell of a cell in which a defect has occurred.

Meanwhile, a semiconductor memory device is largely divided into a core circuit area and a peripheral circuit area. A plurality of memory banks are provided in the core circuit region, and a plurality of memory cells are provided in each memory bank to store data. The peripheral circuit region includes accessory circuits for controlling the operation of the core circuit region, and performs various functions such as operation mode setting, power supply control, and timing control between a clock and data. The redundancy circuit is provided in the memory bank of the core circuit region, and whether or not the redundancy circuit is utilized is determined by the provided fuse set.

Hereinafter, a column redundancy control circuit of a conventional semiconductor memory device will be described with reference to the accompanying drawings.

1 is a block diagram of a column redundancy control circuit of a semiconductor memory device according to the related art.

As illustrated, the column redundancy control circuit of the semiconductor memory device according to the related art is divided into a peripheral circuit redundancy control means 10 and a memory bank redundancy control means 20.

The peripheral circuit redundancy control means 10 buffers the external address add_ext <1: n> and buffers the address buffer 110 for outputting the buffering address add_buf <1: n> and the external command cmd_ext. The command buffer 120 outputting the buffering command cmd_buf, the first flip-flop unit 130 latching the buffering address add_buf <1: n> under the control of the clock clk, and the clock clk. According to the control of the second flip-flop unit 140 for latching the buffering command (cmd_buf), the latch address (add_lat <1: n>) and the second flip-flop output from the first flip-flop unit 130 A global address generator 150 and a bank address add_bnk <1: m> that receive the first internal command cmd_int1 output from the unit 140 and generate a global address add_glb <1: n>; The command converting unit 160 receives the first internal command cmd_int1 and generates a second internal command cmd_int2. It includes.

The memory bank redundancy control unit 20 generates a local address add_loc <1: n> from the global address add_glb <1: n> in response to the input of the second internal command cmd_int2. An address generator 210 and a fuse set unit 220 which receives the local address add_loc <1: n> and generates a repair determination signal rpa by comparing the output signals of the plurality of fuse circuits. A delay unit 230 for delaying the local address add_loc <1: n> by a predetermined time and outputting a delayed local address add_locd <1: n> according to whether the repair determination signal rpa is enabled. The delay local address according to whether the repair decoding signal rpa is enabled and the redundant decoding unit 240 that decodes the delay local address add_lcld <1: n> to activate one of the redundant bit lines RBL. decode (add_locd <1: n>) And a main decoding unit 250 to enable the slower one of the main bit line (MBL).

Here, n and m, which represent the number of bits of each address, are positive integers, and may be the same number or different numbers. That is, the first flip-flop unit 130 includes n flip-flop circuits, and the buffering address add_buf <1: n> is latched in each flip-flop circuit by one bit.

The external command cmd_ext is a signal input to indicate an active mode of the semiconductor memory device.

The global address generator 150 generates the global address add_glb <1: n> from the latch address add_lat <1: n> according to the instruction of the first internal command cmd_int1. In addition, the command converting unit 160 converts the first internal command cmd_int1 to generate the second internal command cmd_int2, and converts the first internal command cmd_int1 to a memory bank designated by the bank address add_bnk <1: m>. To pass.

In general, since a plurality of memory banks are provided in the semiconductor memory device, the memory bank redundancy control means 20 includes a plurality of memory banks. The second internal command cmd_int2 instructs the operation of any one of the local address generators 210 provided in each of the plurality of memory bank redundancy control means 20, and by the second internal command cmd_int2. The selected local address generator 210 receives the global address add_glb <1: n> and generates the local address add_loc <1: n>.

The fuse set unit 220 includes n fuse circuits, and the n fuse circuits generate signals as the fuses are connected or opened as set in the test step. When the local address add_loc <1: n> is input to the n fuse circuits of the fuse set unit 220 in the active mode, the fuse set unit 220 outputs the output signal of the fuse circuit and the local address add_loc < 1: n>) is compared by one bit to generate the repair determination signal rpa. The repair determination signal rpa activates the redundant decoding unit 240 or the main decoding unit 250 according to its potential level. For example, when the potential of the repair determination signal rpa is high level, the redundant decoding unit 240 is activated. When the potential of the repair determination signal rpa is low level, the redundancy decoding unit 240 is activated. The main decoding unit 250 is activated.

The delay unit 230 is a timing at which the local address (add_loc <1: n>) is input to the redundant decoding unit 240 and the main decoding unit 250 and the repair determination signal rpa is the redundant decoding It is provided to equalize the timings transmitted to the unit 240 and the main decoding unit 250. Thereafter, the redundant decoding unit 240 activated by the repair determination signal rpa performs a function of activating an arbitrary redundancy bit line RBL from the local address add_loc <1: n>. The main decoding unit 250 activated by the repair determination signal rpa performs a function of activating an arbitrary main bit line MBL from the local address add_loc <1: n>.

As described above, the semiconductor memory device according to the related art includes a column redundancy control circuit to replace a defective memory cell with a redundancy cell. However, the column redundancy control circuit of the semiconductor memory device according to the related art has a problem in that the area margin decreases as the fuse set unit 220 is provided in the memory bank redundancy control means 20. In general, since a fuse circuit must be artificially controlled by using a laser or the like after designing, a technical limitation exists in reducing its area. It also does not form a stacked structure for artificial control, thus affecting the area problem in areas other than the fuse circuit. However, in the related art, a fuse circuit is provided in a memory bank having a relatively smaller available area than a peripheral circuit area, and thus, it is not easy to implement high integration of a semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a column redundancy control circuit and method for a semiconductor memory device which increases the area efficiency by increasing the available area of the memory bank area.

The column redundancy control circuit of a semiconductor memory device according to an embodiment of the present invention for buffering and latching an external command to generate an internal command, buffering and latching an external address, and a preset fuse circuit Peripheral circuit redundancy control means for generating a global address in comparison with an output signal of the? And memory bank redundancy control means for selectively activating a redundancy bit line or a main bit line in response to an input of the internal command, wherein the fuse circuit is provided in the peripheral circuit redundancy control means. It is characterized by.

In addition, the column redundancy control circuit of the semiconductor memory device according to another embodiment of the present invention may include a second latch address buffered and latched from an external address and respective fuse circuits in response to the first latch address generated by latching a row address. A fuse set unit configured to generate a repair determination signal by comparing the output signals of the first and second signals; A global address generator configured to receive a buffered and latched third latch address from an external address and an output signal of each fuse circuit of the fuse set unit, and generate a global address according to control of the repair determination signal and a first internal command; A local address generator configured to generate a local address from the global address in response to an input of a second internal command; A redundant decoding unit activating a redundancy bit line according to the indication of the local address; And a main decoding unit activating a main bit line according to the indication of the local address.

In the method for controlling column redundancy of a semiconductor memory device according to the present invention, a) a repair is performed by comparing output signals of a plurality of fuse circuits having a predetermined short circuit with an address transmitted from the outside in response to a row address latched by a row command. Generating a discrimination signal; b) receiving a first latch address and an output signal of each fuse circuit of the fuse set unit and generating a global address according to control of the repair determination signal and a first internal command; c) generating a local address from the global address in response to a second internal command; And d) selectively activating a redundancy bit line or a main bit line according to the indication of the local address.

The column redundancy control circuit and method of the semiconductor memory device of the present invention have the effect of increasing the available area of the memory bank area by improving the area efficiency by providing a fuse set portion in the peripheral circuit redundancy control means.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of a column redundancy control circuit of a semiconductor memory device according to an embodiment of the present invention.

As shown, the column redundancy control circuit of the semiconductor memory device according to an embodiment of the present invention includes a peripheral circuit redundancy control means 30 and a memory bank redundancy control means 40.

Here, the peripheral circuit redundancy control means 30 buffers an external address add_ext <1: n> to output an address buffer 302 and an external command cmd_ext that output a buffering address add_buf <1: n>. The first latch address add_lat1 <1: n> is received by receiving a command buffer 304 for buffering and outputting a buffering command cmd_buf, the buffering address add_buf <1: n>, and the buffering command cmd_buf. The first flip-flop unit 306 to generate a row selector to generate a second latch address add_lat2 <1: j> by latching the row address add_row <1: k> in response to the row command cmd_row. 308, in response to the second latch address add_lat2 <1: j>, the repair determination signal rpa is compared by comparing the first latch address add_lat1 <1: n> with the output signals of the respective fuse circuits. ) And a fuse that encodes the output signal of each fuse circuit and outputs it as a fuse circuit signal (fs <1: n>). The set unit 310, a first delay unit 312 outputting a delay buffering address add_bufd <1: n> by delaying the buffering address add_buf <1: n> a predetermined time, and the buffering command cmd_buf. Second delay unit 314 outputting a delay buffering command cmd_bufd by delaying a predetermined time, and a second flip-flop unit latching the delay buffering address add_bufd <1: n> under the control of the clock clk. 316, in the third flip-flop unit 318, the repair determination signal rpa, and the third flip-flop unit 318 which latch the delay buffering command cmd_bufd under the control of the clock clk. From the third latch address (add_lat3 <1: n>) and the fuse circuit signals fs <1: n> output from the second flip-flop unit 316 in response to the outputted first internal command cmd_int1. The global address generator 320 and the bank address add_bnk <1: m> for generating the global address add_glb <1: n + 1> and the first address. And a command converting unit 322 that receives the first internal command cmd_int1 and generates a second internal command cmd_int2.

In addition, the memory bank redundancy control means 40 is configured to generate a local address add_loc <1: n + 1> from the global address add_glb <1: n + 1> in response to the input of the second internal command cmd_int2. A local address generation unit 410 for generating a plurality of input signals, and generates an auxiliary repair determination signal arpa by receiving the local address add_loc <1: n + 1> and comparing them with output signals of a plurality of fuse circuits. An auxiliary fuse set unit 420 and a third delay unit 430 outputting a delayed local address add_locd <1: n + 1> by delaying the local address add_loc <1: n + 1> by a predetermined time; Redundant decoding unit 440 and the delay to decode the delay local address add_lcld <1: n + 1> to activate any one of the redundant bit lines RBL under the control of the auxiliary repair determination signal rpa. Decode the local address (add_locd <1: n + 1>) to either main bit line (MBL) And a main decoding unit 450 to activate.

Here, n, m, k, and j, which represent the number of bits in each address, are each positive integers, and may be the same number or different numbers. That is, each of the first flip-flop unit 306 and the second flip-flop unit 314 includes n flip-flop circuits, and each of the buffering address add_buf <1: n> and the delay buffering address add_bufd <1: n> is latched into each flip-flop circuit by one bit.

The external command cmd_ext is a signal input to indicate an active mode of the semiconductor memory device.

The first flip-flop unit 306 generates the first latch address add_lat1 <1: n> from the buffering address add_buf <1: n> when the buffering command cmd_buf indicates an active mode. .

The row address add_row <1: k> is a name of a bank address add_bnk <1: m> and a row block address add_blk <1: k-m>. The row selector 308 latches and decodes the bank address add_bnk <1: m> and the row block address add_blk <1: km> in response to the row command cmd_row to thereby provide the second latch address. Create (add_lat2 <1: j>). Accordingly, the second latch address add_lat2 <1: j> contains information about the memory bank and the memory blocks in the memory bank.

The fuse set unit 310 includes n fuse circuits, and the n fuse circuits generate signals as the fuses are connected or opened as set in the test step. At this time, the n signals generated from the n fuse circuits are controlled by the second latch address add_lat2 <1: j>. The fuse set unit 310 generates the repair determination signal rpa by comparing the output signal of each of the n fuse circuits thus output and the first latch address add_lat1 <1: n> by one bit. do. The repair determination signal rpa provides information on whether the first latch address add_lat1 <1: n> is a normal address or a repair address according to its potential level. In addition, the output signal of each of the n fuse circuits is encoded to output the fuse circuit signals fs <1: n>.

If the first internal command cmd_int1 indicates an active mode when the repair determination signal rpa is disabled, the global address generator 320 may repair the third latch address add_lat3 <1: n> and the repair. The determination signal rpa is combined to generate the global address add_glb <1: n + 1>. Therefore, the number of bits of the global address add_glb <1: n + 1> is increased by one bit from the third latch address add_lat3 <1: n>, and whether the repair determination signal rpa provides repair Contains information about That is, the global address generator 320 transmits information on whether to repair the memory bank through one bit (eg, most significant bit) of the global address add_glb <1: n + 1>.

The command converting unit 322 converts the first internal command cmd_int1 to generate the second internal command cmd_int2, and then converts the first internal command cmd_int1 to a memory bank designated by the bank address add_bnk <1: m>. To pass.

The memory bank redundancy control means 40 is provided with a plurality of memory banks. The second internal command cmd_int2 instructs the operation of any one of the local address generators 410 provided in the plurality of memory bank redundancy control means 40, and in response to the second internal command cmd_int2. The selected local address generator 410 receives the global address add_glb <1: n + 1> and generates the local address add_loc <1: n + 1>.

The auxiliary fuse set unit 420 is provided to replace another memory cell when a defect occurs in the redundant memory cell. The auxiliary fuse set unit 420 also includes a plurality of fuse circuits, and compares the signals output therefrom with the local address add_loc <1: n + 1>, so that the redundancy bit line RBL is different from each other. When it is necessary to replace the redundancy bit line RBL, the auxiliary repair determination signal arpa is enabled. In this case, since the auxiliary fuse set part 420 has a smaller number of fuse circuits than the fuse set part 310, the area margin loss due to the arrangement of the auxiliary fuse set part 420 is not large. Can be.

The third delay unit 430 may include a timing at which the local address add_loc <1: n + 1> is input to the redundant decoding unit 440 and the main decoding unit 450, and the auxiliary repair determination signal ( arpa) is provided so that the timing transmitted to the redundant decoding unit 440 is the same.

Thereafter, when the auxiliary repair determination signal arpa is disabled, the redundant decoding unit 440 indicates that the local address when a predetermined bit of the local address add_loc <1: n + 1> indicates a repair operation. Activates any one of the redundancy bit lines RBL from (add_loc <1: n + 1>). In addition, when the auxiliary repair determination signal arpa is enabled, any one of the redundancy bit lines RBL corresponding thereto is activated.

When a predetermined bit of the local address (add_loc <1: n + 1>) indicates a normal operation, the main decoding unit 450 decodes the local address (add_loc <1: n + 1>) to any one. It activates the main bit line (MBL).

As described above, the column redundancy control circuit of the semiconductor memory device of the present invention includes the fuse set unit 310 in the peripheral circuit redundancy control means 30 to increase the available area in the memory bank and increase the area margin. In order for the memory bank to distinguish between the repair mode and the normal mode, one bit of the global address (add_glb <1: n + 1>) contains information about it. This increases the number of bits of the global address (add_glb <1: n + 1>).

FIG. 3 is a detailed configuration diagram of the first flip-flop unit shown in FIG. 2 and shows only one flip-flop circuit latching an address of one bit. It can be inferred that the first flip-flop unit to be implemented according to the present invention is provided with n illustrated flip-flop circuits.

The flip-flop circuit non-inverts the signal transmitted from the first switch 3062 and the first latch 3062 through one bit of the buffering address add_buf <i> under the control of the buffering command cmd_buf. And a first driver 3064 for outputting one bit of the first latch address add_lat1 <i>.

The first switch 3062 includes a first passgate PG1 that passes the one-bit buffering address add_buf <i> when the potential of the buffering command cmd_buf is at a low level. . The buffering command cmd_buf is a low enable signal.

The first driver 3064 includes first and second inverters IV1 and IV2 for non-inverting driving the signal transmitted from the first switch 3062.

When the buffering command cmd_buf is enabled in the active mode of the semiconductor memory device, the one-bit buffering address add_buf <i> passes through the first passgate PG1 of the first switch 3062. The first driver 3064 is transmitted. Thereafter, the first driver 3064 drives the signal transmitted from the first switch 3062 and outputs the first latch address add_lat1 <i> of one bit.

4 is a configuration diagram illustrating a row selector illustrated in FIG. 2.

As shown in the drawing, the row selector 308 may select one of the bank address add_bnk <1: m> and the row block address add_blk <1: km> under the control of the row command cmd_row. Decode the output signals of the k flip-flops FF <1: k> and the k flip-flops FF <1: k> to latch the signal of the bit to decode the second latch address add_lat2 <1: j>. It includes a decoder (DEC) for generating a).

In this configuration, the second latch address add_lat2 <1: j> generated from the row selector 308 may contain information of a memory bank and a memory block. Thereafter, the fuse set unit 310 controls a signal generated from each fuse circuit in response to the second latch address add_lat2 <1: j>.

FIG. 5 is a detailed block diagram of the global address generator shown in FIG. It can be inferred that the global address generation unit to be implemented by the present invention includes n illustrated circuit configurations. Here, the circuit configuration of the address output terminal for outputting a global address (add_glb <1 + n>) of n + 1 bits by combining a plurality of global addresses (add_glb <i>) and the repair determination signal rpa is not shown. It is revealed.

When the repair determination signal rpa is enabled, the global address generator 320 may include a second switch 3202 and the repair determination signal rpa that pass one bit of the fuse circuit signal fs <i>. When disabled and the first internal command cmd_int1 is enabled, the first latch 3204 and the second switch 3202 and the first latch latching one bit of the third latch address add_lat3 <i>. And a second driver 3206 for non-inverting driving the signal output from 3204 and outputting one bit of the global address add_glb <i>.

Here, the second switch 3202 includes a second pass gate PG2, and the second driver 3206 includes two inverters, third and fourth inverters IV3 and IV4 connected in series.

In the global address generator 320 configured as described above, when the repair determination signal rpa is enabled, one bit of the fuse circuit signal fs <i> is output as one bit of the global address add_glb <i>. do. When the first internal command cmd_int1 is enabled while the repair determination signal rpa is disabled, the third latch address add_lat3 <i> of one bit is the global address add_glb <i> of one bit. Is output as

Thereafter, the output terminal of the global address generator 320 combines each global address (add_glb <1: n>) and the repair determination signal rpa transmitted through the above-described process, thereby globalizing the n + 1 bit. Output the address (add_glb <n + 1>). Accordingly, the global address add_glb <1: n + 1>, which is transmitted to the memory bank redundancy control means 40, contains information on whether a repair operation is performed.

As described above, the column redundancy control circuit of the semiconductor memory device of the present invention includes the fuse set unit 310 in the peripheral circuit redundancy control means 30 to increase the available area in the memory bank and increase the area margin. To this end, the peripheral circuit redundancy control means 30 includes a global address generator 320 for generating a global address add_glb <1: n + 1>, and the global address add_glb <1: n + 1>. One bit of contains information about whether to repair.

Of course, the auxiliary bank set part 420 is also provided in the memory bank redundancy control means 40. However, since the auxiliary fuse set part 420 is provided only for the replacement of the redundancy bit line RBL, the area occupied by the fuse set part in the memory bank is conventionally occupied. This is remarkably small. Therefore, it is possible to increase the utilization of the available area in the memory bank, thereby facilitating high integration of the semiconductor memory device.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a column redundancy control circuit of a conventional semiconductor memory device;

2 is a configuration diagram of a column redundancy control circuit of a semiconductor memory device according to an embodiment of the present invention;

3 is a configuration diagram of the first flip-flop unit illustrated in FIG. 2;

4 is a configuration diagram of a row selector illustrated in FIG. 2;

FIG. 5 is a configuration diagram of the global address generator shown in FIG. 2.

<Description of the symbols for the main parts of the drawings>

30: peripheral circuit redundancy control means 40: memory bank redundancy control means

306: first flip-flop portion 310: fuse set portion

316: second flip-flop portion 318: third flip-flop portion

320: global address generation unit 322: command conversion unit

410: local address generator 420: auxiliary fuse set unit

440: redundant decoding unit 450: main decoding unit

Claims (28)

Peripheral circuit redundancy control means for buffering and latching external commands to generate internal commands, buffering and latching external addresses, and comparing the output signals with preset outputs of the fuse circuit to generate global addresses; And Memory bank redundancy control means for selectively activating a redundancy bit line or a main bit line in response to an input of the internal command; And the fuse circuit is provided in the peripheral circuit redundancy control means. The method of claim 1, And wherein the global address contains information on whether a repair operation is performed. The method of claim 1, The peripheral circuit redundancy control means, A first flip-flop unit configured to receive a buffering address and a buffering command to generate a first latch address; A row selector configured to latch and decode a row address in response to a row command to generate a second latch address; A fuse set unit configured to generate a repair determination signal by comparing the first latch address with an output signal of each fuse circuit in response to the second latch address; A second flip-flop unit for latching a delay buffering address according to a control of a clock; A third flip-flop unit configured to latch a delay buffering command according to the control of the clock; A global address generator configured to receive a second latch address and an output signal of each fuse circuit of the fuse set unit, and generate a global address according to control of the repair determination signal and a first internal command output from the third flip-flop unit; And A command converter configured to receive a bank address and the first internal command and generate a second internal command; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 3, wherein An address buffer configured to output the buffering address by buffering the external address; And A command buffer configured to output the buffering command by buffering the external command; The column redundancy control circuit of the semiconductor memory device further comprising. The method of claim 3, wherein A first delay unit outputting the delay buffering address by delaying the buffering address for a predetermined time; And A second delay unit outputting the delay buffering command by delaying the buffering command for a predetermined time; The column redundancy control circuit of the semiconductor memory device further comprising. The method of claim 3, wherein The first flip-flop unit includes flip-flop circuits equal to the number of bits of the buffering address, Each of the flip-flop circuits, A switch for passing one bit of a buffering address according to the control of the buffering command; And A driving unit for non-inverting driving the signal transmitted from the switch to output the first latch address bit; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 3, wherein The row address includes a bank address and a row block address, The row selector, A plurality of flip-flops for latching a signal of one bit of the bank address and the row block address according to the control of the row command; And A decoder for decoding the output signals of the plurality of flip-flops to generate the second latch address; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 3, wherein The global address generator, A switch for passing one bit of an output signal of a fuse circuit of the fuse set unit when the repair determination signal is enabled; A latch configured to latch one bit of the second latch address when the repair determination signal is disabled and the first internal command is enabled; And A driving unit for non-inverting driving the signals output from the switch and the latch to output a single global address; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 1, And the external command indicates an active mode of the semiconductor memory device. The method of claim 3, wherein The memory bank redundancy control means, A local address generator configured to generate a local address from the global address in response to the input of the second internal command; An auxiliary fuse set unit configured to receive the local address and generate an auxiliary repair determination signal by comparing the output signals of the plurality of fuse circuits; A third delay unit outputting a delayed local address by delaying the local address for a predetermined time; A redundant decoding unit to decode the delayed local address and to activate any one of the redundant bit lines according to the control of the auxiliary repair determination signal; And A main decoding unit for decoding the delay local address to activate any one main bit line; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 10, And the auxiliary fuse set unit generates the auxiliary repair determination signal by comparing the local address with information for replacing a defective redundancy bit line. A fuse set unit configured to generate a repair determination signal by comparing a second latch address buffered and latched from an external address with an output signal of each fuse circuit in response to a first latch address generated by latching a row address; A global address generator configured to receive a buffered and latched third latch address from an external address and an output signal of each fuse circuit of the fuse set unit, and generate a global address according to control of the repair determination signal and a first internal command; A local address generator configured to generate a local address from the global address in response to an input of a second internal command; A redundant decoding unit activating a redundancy bit line according to the indication of the local address; And A main decoder for activating a main bit line according to the indication of the local address; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 12, And wherein the global address contains information on whether a repair operation is performed. The method of claim 12, And the fuse set unit and the global address generator are disposed in a peripheral circuit area, and the local address generator, the redundant decoder, and the main decoder are disposed in a memory bank area. The method of claim 14, An address buffer which buffers the external address and outputs a buffering address; A command buffer that buffers an external command and outputs a buffering command; A first flip-flop unit configured to receive the buffering address and the buffering command to generate the second latch address; And A row selector configured to latch and decode a row address in response to a row command to generate the first latch address; The column redundancy control circuit of the semiconductor memory device further comprising. The method of claim 15, The first flip-flop unit includes flip-flop circuits equal to the number of bits of the buffering address, Each of the flip-flop circuits, A switch for passing one bit of the buffering address according to the control of the buffering command; And A driving unit for non-inverting driving the signal transmitted from the switch to output the second latch address one bit; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 15, The row address includes a bank address and a row block address, The row selector, A plurality of flip-flops for latching a signal of one bit of the bank address and the row block address according to the control of the row command; And A decoder for decoding the output signals of the plurality of flip-flops to generate the first latch address; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 16, A first delay unit configured to output a delay buffering address by delaying the buffering address for a predetermined time; A second delay unit configured to delay the buffering command by a predetermined time and output a delay buffering command; A second flip-flop unit configured to output the third latch address by latching the delay buffering address according to a control of a clock; A third flip-flop unit configured to output the first internal command by latching the delay buffering command according to the control of the clock; And A command converting unit converting the first internal command into the second internal command in response to an input of a bank address; The column redundancy control circuit of the semiconductor memory device further comprising. The method of claim 12, The global address generator, A switch for passing one bit of an output signal of a fuse circuit of the fuse set unit when the repair determination signal is enabled; A latch configured to latch the third latch address one bit when the repair determination signal is disabled and the first internal command is enabled; And A driving unit for non-inverting driving the signals output from the switch and the latch to output a single global address; A column redundancy control circuit of a semiconductor memory device comprising a. The method of claim 12, And an auxiliary fuse set unit configured to receive the local address and generate an auxiliary repair determination signal by comparing the output signals of the plurality of fuse circuits. The method of claim 20, And the auxiliary fuse set unit generates the auxiliary repair determination signal by comparing the local address with information for replacing a defective redundancy bit line. The method of claim 12, And the first and second internal commands indicate an active mode of the semiconductor memory device. a) generating a repair determination signal by comparing output signals of a plurality of fuse circuits in which an address transmitted from the outside and a short circuit are preset in response to the row address latched by the row command; b) receiving a first latch address and an output signal of each fuse circuit of the fuse set unit and generating a global address according to control of the repair determination signal and a first internal command; c) generating a local address from the global address in response to a second internal command; And d) selectively activating a redundancy bit line or a main bit line according to the indication of the local address; A method for controlling column redundancy of a semiconductor memory device comprising a. The method of claim 23, And wherein the global address contains information on whether a repair operation is performed. The method of claim 23, The operations of steps a) and b) are performed in the peripheral circuit area, and the operations of steps c) and d) are performed in the memory bank area. The method of claim 23, B), Passing a bit of an output signal of the fuse circuit when the repair determination signal is enabled; Latching a second latched address one bit buffered and latched from an external address when the repair determination signal is disabled and the first internal command is enabled; And Non-inverting driving one bit of the output signal of the fuse circuit or one bit of the second latch address to output one bit of a global address; A method for controlling column redundancy of a semiconductor memory device comprising a. The method of claim 23, Between step c) and step d), e) generating the auxiliary repair determination signal by comparing the local address with the output signals of the plurality of fuse circuits provided therein, and transmitting the auxiliary repair determination signal to step d) to instruct replacement of the defective redundancy bit line; A method for controlling column redundancy of a semiconductor memory device, comprising: The method of claim 23, And the first internal command and the second internal command indicate an active mode of the semiconductor memory device.
KR1020070069621A 2007-07-11 2007-07-11 Circuit and method for controlling column redundancy in semiconductor memory apparatus KR20090006359A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112164413A (en) * 2019-06-16 2021-01-01 晶豪科技股份有限公司 Electronic fuse circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112164413A (en) * 2019-06-16 2021-01-01 晶豪科技股份有限公司 Electronic fuse circuit
CN112164413B (en) * 2019-06-16 2023-07-18 晶豪科技股份有限公司 Electronic fuse circuit

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