KR20070040745A - Address path circuit comprising row redundant scheme - Google Patents

Abstract

The present invention provides an address buffer for outputting an internal address by buffering an external address; A command buffer configured to receive and buffer a plurality of external commands; A pre-latch unit for latching the internal address using a buffered RAS signal output from a command buffer; A determination unit which receives the internal address latched by the pre-latch unit, determines whether the internal address is a repaired address or a normal address, and outputs at least one determination signal; An address latch unit for latching the internal address using a buffered clock signal; Receiving the at least one determination signal and an internal address from the address latch unit to generate a global row address, and when the determination unit determines that the internal address is a normal address, the internal address from the address latch unit is set to the global address. A low redundancy scheme including a global address generator that outputs a row address and outputs an address encoded by the at least one discrimination signal as the global row address when the internal address is a repaired address as a result of the determination of the discriminator; It relates to an address pass circuit including a row redundant scheme.

Address pass circuit

Description

Address Path Circuit Comprising Row Redundant Scheme with Low Redundancy Scheme

1 shows a configuration of an address path circuit according to the prior art.

2 illustrates a configuration of an address pass circuit according to an embodiment of the present invention.

FIG. 3 shows the configuration of a pre-latch used in the address pass circuit including the low redundant scheme according to the present embodiment.

FIG. 4A shows the configuration of the discriminating unit used in the address pass circuit including the low redundancy scheme according to the present embodiment, and FIG. 4B shows the structure of the discriminating circuit included in the discriminating unit in FIG. 4A.

5 shows the configuration of the global address generator used in the address pass circuit including the low redundancy scheme according to the present embodiment.

6 shows the configuration of a decoder used for the address pass circuit including the low redundant scheme according to the present embodiment.

The present invention relates to an address pass circuit including a low redundancy scheme. More specifically, each bank determines whether an address input through an address buffer is a repaired address or a normal address. The present invention relates to an address pass circuit capable of reducing the chip area of a semiconductor device and improving the operating speed of the semiconductor device by providing the semiconductor device in a ferry region.

In general, when a defect occurs in a cell of a cell array, the semiconductor device is repaired using a redundancy circuit. That is, a specific cell connected to a word line or a bit line of a cell array that stores data may fail due to various factors to read or write data. When you cannot write or lose the data storage capacity, you can replace the cells of the feature word line or bit line with the cells of the word line or bit line that have been spared.

Accordingly, the address pass circuit of the semiconductor device determines whether an externally input address is a normal address or a repaired address, and accordingly outputs a signal for selecting a normal main word line or a redundant main word line. . However, in a conventional address pass circuit including a low redundancy scheme, a discriminating unit for determining whether an address is a normal address or a repaired address is provided in each bank of the core region, thereby increasing the chip area of the semiconductor device and preventing the operation speed from being improved. There was a problem. Hereinafter, the problem of the address pass circuit including the conventional low redundant scheme will be described in more detail with reference to FIG. 1.

1 shows a configuration of an address path circuit according to the prior art.

First, the external clock CLK, the external address an, and the external commands RAS, CAS, WE, and CS are buffered by the clock buffer 105, the address buffer 110, and the command buffer 115, respectively. Subsequently, the address latch unit 120 latches an internal address (add) output from the address buffer 110 in synchronization with the internal clock iCLK output from the clock buffer 105. Meanwhile, the command decoder 130 receives at least one command buffered by the command buffer 115 and outputs a row decoding signal row6.

The global address generator 140 receives an internal address latched by the address latch unit 120 and the row decoding signal row6, and generates a global address to be transmitted through a global address line. . The control circuit 150 receives the row decoding signal row6 and the bank address ba and outputs the row access strobe signal Ratvzp13.

The local address generator 160 latches the global address gax in synchronization with the row access strobe signal Ratvzp13 output from the control circuit 150 and outputs a valid local row address bax for each bank. The determination unit 170 including the fuse circuit receives the local row address bax, determines whether it is a normal row address or a repaired row address, and provides the information to the decoder 180. Finally, the decoder 180 outputs the normal main word line signal mwlz and repairs the row address if the local row address bax is a normal row address using the discrimination information from the determination unit 170. If, the redundant main word line signal rmwlz is output.

As described above, in the conventional address pass circuit, a discriminating unit for determining whether an address is a normal address or a repaired address is provided for each bank of the core region, thereby increasing the chip area in the semiconductor device for accommodating it. In addition, the main main line cannot be selected until discrimination information generated by the determination unit 170 including the fuse circuit is generated, thereby preventing the operation speed of the semiconductor device from being improved.

Therefore, the technical problem to be achieved by the present invention is to reduce the chip area of the semiconductor device by providing a determination unit for determining whether the address input through the address buffer is a repaired address or a normal address in the ferry area instead of in each bank. The present invention provides an address pass circuit that can improve the operation speed of the circuit.

In order to achieve the above technical problem, the present invention provides an address buffer for buffering an external address and outputting an internal address; A command buffer configured to receive and buffer a plurality of external commands; A pre-latch unit for latching the internal address using a buffered predetermined command output from a command buffer; A determination unit which receives the internal address latched by the pre-latch unit, determines whether the internal address is a repaired address or a normal address, and outputs at least one determination signal; An address latch unit for latching the internal address using a buffered clock signal; Receiving the at least one determination signal and an internal address from the address latch unit to generate a global row address, and when the determination unit determines that the internal address is a normal address, the internal address from the address latch unit is set to the global address. A low redundancy scheme including a global address generator that outputs a row address and outputs an address encoded by the at least one discrimination signal as the global row address when the internal address is a repaired address as a result of the determination of the discriminator; It provides an address pass circuit including a.

In the present invention, the address pass circuit including the low redundancy scheme comprises: a local address generator for latching the global row address in synchronization with a predetermined row access strobe signal and outputting a valid local row address for each bank; The decoder may further include a decoder configured to receive the local row address, decode the local row address, and output a main word line signal corresponding to the normal address or a redundant main word line signal corresponding to the repaired address.

The decoder may include: a first decoder configured to receive the local row address and to decode the local row address to output a main wordline signal corresponding to the normal address; and to receive the local row address and to decode the local row address to decode the repaired address. And a second decoder for outputting a redundant mainword line signal corresponding to the second decoder.

In the present invention, it is preferable that the pre-latch unit latches the internal address using a buffered Ras signal output from the command buffer.

In the present invention, the pre-latch unit includes a first delay delaying the internal address by a first interval, a second delay delaying the buffered erase signal by a second interval, and an output signal of the second delay delay. And a latch element for latching an internal address output from the one delay unit in synchronization with the enable point.

In the present invention, the latch element latches the internal address output from the first delay in synchronization with the enable time of the output signal of the second delay and holds it until the next enable time of the output signal of the second delay. It is preferable that it is a flip-flop.

In the present invention, the determination unit and a decoder for decoding the internal address output from the pre-latch unit; And a plurality of discrimination circuits for receiving the plurality of decoded signals outputted from the decoder and outputting the discrimination signal for discriminating whether the internal address is a repaired address or a normal address.

In the present invention, each of the plurality of discrimination circuits comprises: precharge means for precharging the first node in response to a predetermined precharge signal; A plurality of pull-down devices configured to pull-down the first node in response to the plurality of decoded signals; It is preferably configured to include a plurality of fuses respectively provided between the plurality of pull-down elements and the first node.

In the present invention, each of the plurality of discrimination circuits preferably further includes a latch portion for holding the potential of the first node at a predetermined potential.

In the present invention, the combination of whether or not each fuse constituting the plurality of fuses is configured to correspond to an address of a redundant cell.

In the present invention, each of the plurality of discrimination circuits preferably further comprises a plurality of switches provided between the plurality of pull-down elements and the ground terminal and enabling each discrimination circuit in response to a bank active signal.

In an embodiment of the present invention, the global address generator comprises: a logic unit configured to logically operate the at least one discrimination signal; An encoder for encoding the at least one discrimination signal; A first signal transfer unit transferring an internal address from the address latch unit in response to an output signal of the logic unit; And a second signal transfer unit for transmitting an address encoded by the encoder in response to an output signal of the logic unit.

The logic unit may output a gate control signal enabled when any one of the at least one determination signal is enabled.

In the present invention, it is preferable that the logic unit performs a logical sum operation.

In the present invention, the logic unit receives a portion of the at least one discrimination signal and performs a negative logic sum operation, and a NAND gate that receives an output signal of the plurality of NOR gates and performs a negative logic operation. It is preferable to include.

In the present invention, it is preferable that the global address generator further includes an address latch element for latching an internal address from the address latch unit and supplying the internal address to the first signal transfer unit.

In the present invention, it is preferable that the first signal transfer unit and the second signal transfer unit are transfer gates which are turned on and off in response to an output signal of the logic unit.

In the present invention, the global address generation unit may further include a latch unit for latching the output signal of the first signal transfer unit and the second signal transfer unit, and a buffer for buffering the output signal of the latch unit.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

2 is a configuration of an address pass circuit according to an embodiment of the present invention, and FIG. 3 is a configuration of a pre-latch used in an address path circuit including a low redundancy scheme according to the present embodiment. FIG. 4A is a configuration of a discrimination unit used in an address pass circuit including a low redundancy scheme according to the present embodiment, FIG. 4B is a configuration of a discrimination circuit included in the discriminating unit in FIG. 4A, and FIG. 5 is a row according to the present embodiment. A configuration of a global address generator used in an address pass circuit including a redundant scheme is shown. Hereinafter, the present invention will be described with reference to this.

As shown, the address path circuit according to the present embodiment includes an address buffer 210 for buffering an external address an <0:11> and outputting an internal address add <0:11>; A command buffer 215 which receives and buffers a plurality of external commands RAS, CAS, WE, and CS; A pre-latch unit 220 for latching the internal address add <0:11> by using a buffered predetermined command output from the command buffer 215; The pre-latch 220 receives the latched internal addresses to_fuse <0:11> and determines whether the internal address to_fuse <0:11> is a repaired address or a normal address to determine at least one. A discriminating unit 230 for outputting a signal fuse_out <0: 5>; An address latch unit 240 for latching the internal address add <0:11> using a buffered clock signal iCLK; The global row address gax <0:12> is generated by receiving the at least one determination signal fuse_out <0: 5> and the internal address at <0:11> from the address latch unit 240. If the internal address (to_fuse <0:11>) is a normal address, the internal address (at <0:11>) from the address latch unit 240 is determined. Output as a global row address gax <0:12>, and when the internal address to_fuse <0:11> is a repaired address as a result of the determination by the determination unit 230, the at least one determination signal fuse_out A global address generator 260 for outputting an address encoded by <0: 5> as the global row address gax <0:12>; A local address generator 280 which latches the global row address gax <0:12> in synchronization with the row access strobe signal Ratvz13 and outputs a valid local row address bax <0:12> for each bank. )Wow; The local row address bax <0:12> is received and decoded to output a main word line signal mwlz corresponding to the normal address or a redundant main word line signal rmwlz corresponding to the repaired address. It is configured to include a decoder 290.

The operation of this embodiment configured as described above will be described in detail with reference to FIGS. 2 to 6.

First, the clock buffer 205 buffers the external clock CLK to output the clock iCLK, and the address buffer 210 buffers the external address an <0:11> to receive the internal address (add <0: 11>). The command buffer 215 buffers a plurality of external commands RAS, CAS, WE, and CS.

Subsequently, the pre-latch unit 220 receives the buffered erase signal RAS output from the command buffer 215 and latches the internal addresses add <0:11> using the erase signal RAS. The operation of the prelatch 220 will be described in detail with reference to FIG. 3 as follows.

The internal addresses (add <0:11>) input to the prelatch unit 220 are output by being delayed by a predetermined period by the delay unit 221. In addition, the las signal RAS is output by being delayed by a predetermined period by the delay unit 222. Here, the delayer 221 and the delayer 222 adjust the setup-hold time of the signal by delaying the internal addresses add <0:11> and the Ras signal RAS by a predetermined period, respectively. Subsequently, the D-flip-flop 223 latches the internal address add <0:11> output from the delayer 221 in synchronization with the output signal of the delayer 222, thereby causing the internal address to_fuse <0:11. Output>) That is, the D-flip-flop 223 latches the internal address (add <0:11>) delayed by the delayer 221 in synchronization with the rising edge of the lath signal RAS delayed by the delayer 222. The delayed ras signal RAS is maintained until the next rising edge and outputs it.

Next, the determination unit 230 receives an internal address latched by the pre-latch unit 220 (to_fuse <0:11>), and determines whether the internal address (to_fuse <0:11>) is a repaired address or a normal address. A plurality of determination signals fuse_out <0: 5> are output by determining whether the recognition signal is recognized, and a specific operation of the determination unit 230 will be described with reference to FIGS. 4A and 4B.

In the determination unit 230 of FIG. 4A, the decoder 231 receives an internal address (to_fuse <0:11>) and decodes the decoded signals bax2 <0: 1>, bax34 <0: 3>, bax56 < 0: 3>, bax78 <0: 3>, bax9AB <0: 7> Here, as the decoder 231, any decoding circuit generally used in semiconductor devices can be used. The discrimination circuits <0> to <5> receive the decoded signals and determine whether an internal address is a repaired address or a normal address. The number of discrimination circuits used in this case may be provided in, for example, a semiconductor device. Corresponding to the number of redundancy circuits present, the number may be set differently according to the semiconductor device. Specific operations of the discriminating circuits <0> to <5> will be described with reference to FIG. 4B. 4B shows the configuration of the discriminating circuit <0>, and the configuration of the specific circuits of the discriminating circuits <1> to <5> is the same.

First, when the precharge signal wlaz is enabled at a low level, the node A is precharged to a high level while the PMOS P10 is turned on, and the precharge signal wlaz transitions to a high level. Even when P10 is turned off, the potential of the node A is maintained at the high level by the latch 235. When the bank active signal BA is enabled at the high level, the NMOS N51 to N55 are turned on.

In FIG. 4B, the plurality of fuses constituting the fuses 232_1 to 232_5 are configured such that a combination depending on whether the fuses are cut off corresponds to the address of the redundant cell. That is, only one of the fuses constituting the fuse unit 231_1 is cut off, and similarly, only one fuse among the fuses 232_2 to 232_5 is cut off. Accordingly, when it is known which fuses are cut off in each fuse unit, the fuses may be combined to know an address of a redundant cell corresponding thereto.

If a high level is applied among the decoded signals bax2 <0: 1>, bax34 <0: 3>, bax56 <0: 3>, bax78 <0: 3>, and bax9AB <0: 7> If the combination of the in signals coincides with the combination of the cutoff fuses, no current path is generated between the node A and the ground terminal, so the node A maintains a high level of precharge level. That is, for example, if only fuses f11, f13, f17, f21, and f25 are cut off and the remaining fuses are not cut off, bax2 <0>, bax34 <0>, bax56 <0>, bax78 <0>, If only bax9AB <0> is high level, no current path is generated between node A and ground terminal VSS, so node A maintains the high level of the precharge level and the discrimination signal fuse_out <0>. Becomes high level. At this time, it is determined that the input internal address is the repaired address.

On the other hand, if the decoded signals bax2 <0: 1>, bax34 <0: 3>, bax56 <0: 3>, bax78 <0: 3>, bax9AB <0: 7> are applied to the discrimination circuit <0>, If the combination of signals that is level does not match the combination of cutoff fuses, then at least one current path occurs between node A and the ground terminal, so that node A is at a low level. That is, for example, if only fuses f11, f13, f17, f21, and f25 are cut off and the remaining fuses are not cut off, bax2 <0>, bax34 <0>, bax56 <0>, bax78 <0>, When any one of bax9AB <0> is low level, at least one or more other NMOS devices in addition to the above signals become high level and connected to a fuse which is not cut off, so that the node A is turned on. There is a current path between the ground terminals (VSS). Therefore, the node A is at the low level, and the determination signal fuse_out <0> is also at the low level. In this case, since the input internal address does not correspond to the address of the redundant cell, it is determined that the address is a normal address.

The above discriminating operation is performed not only in the discriminating circuit <0> but also in the discriminating circuits <1> to <5>. Therefore, if any one of the discrimination signals fuse_out <0> to <5>, which are outputs of the discriminating circuits <0> to <5>, is at a high level, it is determined that the internal address input to the semiconductor device is a repaired address. .

Meanwhile, the address latch unit 240 latches the internal addresses add <0:11> in synchronization with the buffered clock signal iCLK. That is, the address latch unit 240 outputs the internal addresses at <0:11> latched in synchronization with the clock signal iCLK. The command decoder 250 receives at least one or more commands buffered by the command buffer 215 and outputs a row decoding signal row6.

Subsequently, the global address generator 260 receives the determination signal fuse_out <0: 5>, the internal address at <0:11>, and the low decoding signal row6, and transmits the data through the global address line. The first to thirteenth global row addresses gax <0:12> are generated. The operation of the global address generator 260 will be described in more detail with reference to FIG. 5.

First, the address latch element 261 latches and outputs the internal addresses at <0:11> by using the row decoding signal rowp6. The encoder 262 receives the plurality of determination signals fuse_out <0: 5>, encodes them, and outputs an internal address corresponding to the redundant cell.

In addition, the logic unit 263 receives the plurality of determination signals fuse_out <0: 5> and logically performs the operation to output a control signal for controlling the transfer gate TG11 and the transfer gate TG12. At this time, if the internal address is a repaired address, that is, if any one of the discrimination signals fuse_out <0> to <5>, which are outputs of the discrimination circuits <0> to <5>, is at a high level, Since at least one of the signals output from the NOR gates NR11 to NR13 and input to the NAND gate ND11 is at a low level, the output signal of the logic unit 263 is at a high level. Therefore, in this case, since the transfer gate TG11 is turned off and the transfer gate TG12 is turned on, the internal address encoded by the encoder 262 is removed through the latch unit 264 and the inverter IV24. It is output as the 1st to 12th global row addresses gax <0:11>. The output signal of the logic unit 263 is output as the thirteenth global row address gax <0:11> through the inverters IV21 and IV25.

On the other hand, if the internal address is a normal address, that is, when the discrimination signals fuse_out <0> to <5>, which are outputs of the discriminating circuits <0> to <5>, are all at the low level, the NOR gates NR11 to ... Since the signals output from the NR13 and input to the NAND gate ND11 are all at the high level, the output signal of the logic unit 263 is at the low level. Therefore, in this case, since the transfer gate TG11 is turned on and the transfer gate TG12 is turned off, the internal address at <0:11> is set to the first to twelfth global row addresses gax <0: 11>). The thirteenth global row address gax <12> indicates whether the input address is a repaired address or a normal address. That is, for example, if the thirteenth global row address gax <12> is at a high level, it is a repaired address, and if it is a low level, it is a normal address.

Meanwhile, in FIG. 2, the control circuit 270 receives the row decoding signal row6 and the bank address ba and outputs a row access strobe signal Ratvzp13, which is a kind of strobe signal. In addition, the local address generator 280 latches the first to thirteenth global row addresses gax <0:12> in synchronization with the row access strobe signal Ratvzp13 output from the control circuit 270, and thus each bank. Outputs a valid local row address (bax <0:12>).

Finally, the decoder 290 receives the local row address bax <0:12> and decodes the local row address bax <0:12>, so that the main word line signal mwlz corresponding to the normal address or the redundant main word line corresponding to the repaired address is received. Output the signal (mwlz). Looking at the operation of the decoder 290 in detail with reference to FIG. 6, the decoder 290 determines whether the address input to the semiconductor device is a repaired address or a normal address according to the level of the local row address bax <12>. It works differently. That is, if the input address is a normal address, the first decoder 291 operates to output a normal main word line signal mwlz. If the input address is a repaired address, the second decoder 291 is used. Operates to output the redundant main wordline signal rmwlz.

As described above, in the address pass circuit including the low redundancy scheme according to the present embodiment, a determination unit for determining whether an address input to the semiconductor device is a repaired address or a normal address is not provided in each bank of the semiconductor device, but in a ferry area. Installed in Accordingly, according to the present embodiment, the chip area of the semiconductor device can be reduced, the arrangement of the fuse circuits in the discriminating unit can be freed, and the normal main word line can be maintained even before the discriminating information is generated by the discriminating unit. It can be selected to improve the operating speed of the semiconductor device.

As described above, in the address path circuit according to the present invention, a determination unit for determining whether an address input through the address buffer is a repaired address or a normal address is provided in the ferry area instead of in each bank. The chip area of the semiconductor device can be reduced and the operating speed of the semiconductor device can be improved.

Claims (18)

An address buffer for buffering an external address and outputting an internal address; A command buffer configured to receive and buffer a plurality of external commands; A pre-latch unit for latching the internal address using a buffered predetermined command output from a command buffer; A determination unit which receives the internal address latched by the pre-latch unit, determines whether the internal address is a repaired address or a normal address, and outputs at least one determination signal; An address latch unit for latching the internal address using a buffered clock signal; Receiving the at least one determination signal and an internal address from the address latch unit to generate a global row address, and when the determination unit determines that the internal address is a normal address, the internal address from the address latch unit is set to the global address. A low redundancy scheme including a global address generator that outputs a row address and outputs an address encoded by the at least one discrimination signal as the global row address when the internal address is a repaired address as a result of the determination of the discriminator; An address pass circuit including a. The method of claim 1, The address pass circuit including the low redundancy scheme comprises: a local address generator for latching the global row address in synchronization with a predetermined row access strobe signal and outputting a valid local row address for each bank; An address pass circuit including a low redundancy scheme further comprising a decoder configured to receive the local row address and decode the local row address and output a main word line signal corresponding to the normal address or a redundant main word line signal corresponding to the repaired address . The method of claim 2, The decoder receives a local row address and decodes the first row decoder to output a main wordline signal corresponding to the normal address, and receives the local row address and decodes the redundant row corresponding to the repaired address. An address pass circuit comprising a low redundant scheme comprising a second decoder for outputting a main word line signal. The method of claim 1, And the pre-latch unit latches the internal address using a buffered erase signal output from a command buffer. The method of claim 4, wherein The pre latch unit A first delayer delaying the internal address by a first interval; A second delayer delaying the buffered erase signal by a second interval; And a latch element for latching an internal address output from the first delay in synchronization with the enable time of the output signal of the second delay. The method of claim 5, The latch element is a flip-flop that latches an internal address output from the first delayer in synchronization with the enable time of the output signal of the second delayer and maintains it until the next enable time of the output signal of the second delayer. Address path circuitry. The method of claim 1, The determining unit A decoder for decoding an internal address output from the pre-latch unit; And a plurality of discrimination circuits for receiving the plurality of decoded signals output from the decoder and outputting the discrimination signal for discriminating whether the internal address is a repaired address or a normal address. The method of claim 7, wherein Each of the plurality of discrimination circuits Precharge means for precharging the first node in response to a predetermined precharge signal; A plurality of pull-down devices configured to pull-down the first node in response to the plurality of decoded signals; And a low redundancy scheme including a plurality of fuses respectively provided between the plurality of pull-down elements and the first node. The method of claim 8, And each of the plurality of discrimination circuits further comprises a latch portion for holding a potential of the first node at a predetermined potential. The method of claim 8, And a combination of whether or not each fuse constituting the plurality of fuses is cut-off corresponds to an address of a redundant cell. The method of claim 8, Each of the plurality of discrimination circuits includes an address pass circuit including a low redundancy scheme further comprising a plurality of switches provided between the plurality of pull-down elements and a ground terminal to enable each discrimination circuit in response to a bank active signal. . The method of claim 1, The global address generator A logic unit configured to logically operate the at least one discrimination signal; An encoder for encoding the at least one discrimination signal; A first signal transfer unit transferring an internal address from the address latch unit in response to an output signal of the logic unit; And a low redundancy scheme comprising a second signal transfer unit for transmitting an address encoded by the encoder in response to an output signal of the logic unit. The method of claim 12, And the logic unit outputs a gate control signal enabled when any one of the at least one determination signal is enabled. The method of claim 13, And the logic unit performs a logic operation. The method of claim 14, The logic section A plurality of NOR gates that receive a portion of the at least one discrimination signal and perform a negative logic sum operation; And a NAND gate configured to receive output signals of the plurality of NOR gates and perform a negative logic operation. The method of claim 12, And the global address generator further comprises an address latch element for latching an internal address from the address latch unit and supplying the internal address to the first signal transfer unit. The method of claim 12, And the first signal transfer unit and the second signal transfer unit include a low redundancy scheme which is a transfer gate that is turned on and off in response to an output signal of the logic unit. The method of claim 12, And the global address generator further comprises a latch unit for latching output signals of the first signal transfer unit and the second signal transfer unit, and a buffer configured to buffer the output signal of the latch unit.

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