KR20090004104A - Organic light emitting display and driving method of the same - Google Patents

Abstract

An organic light emitting display and driving method of the same is provided to solve the brightness of the organic light emitting diode due current reduction by the variation of thread voltage of a driving transistor by improving the structure of a sub-pixel. An organic light emitting display and driving method of the same is comprised of the steps: initializing of turning a second transistor and then turning on the first transistor; detecting whether the first transistor is turned off or not while the second transistor is turned on; writing a data into a fist and second capacitor by turning off the second transistor and then turning on the first transistor; turning on a third and a fourth transistor by a voltage data stored in the first and the second capacitor, and then radiating an organic light emitting diode.

Description

Organic Light Emitting Display and Driving Method of the same

1 is a diagram illustrating a subpixel circuit of an organic light emitting display device according to a first embodiment of the present invention.

2 is an exemplary view of a drive waveform according to the first embodiment of the present invention.

3 is an exemplary view schematically showing the driving waveform of FIG. 2 in one frame; FIG.

4 is a diagram illustrating a gate voltage of a fourth transistor included in a subpixel structure according to the first embodiment of the present invention.

5 is a diagram illustrating a driving current of an organic light emitting diode included in a subpixel structure according to the first embodiment of the present invention.

6 is a diagram illustrating a subpixel circuit of an organic light emitting display device according to a second embodiment of the present invention.

7 is a photocurrent simulation graph of a transistor.

8 is a graph showing an average current increase with decreasing luminance efficiency of an organic light emitting diode.

9 is a simulation graph for negative bias anneal.

10 is an exemplary view of a drive waveform according to a second embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

VDD: First Power Wiring GND: Second Power Wiring

T1, T2, T3, T4, T5: first, second, third, fourth and fifth transistors

SCAN [n]: scan wiring DATA [n]: data wiring

D: organic light emitting diodes C1, C2: first and second capacitors

The present invention relates to an organic light emitting display device and a driving method thereof.

Recently, the importance of flat panel displays (FPDs) has increased with the development of multimedia. In response, a number of liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), organic light emitting devices (Organic Light Emitting Devices), etc. Branch-type flat panel displays have been put into practical use.

The organic light emitting display device may be driven by a passive matrix method and an active matrix method using a thin film transistor (hereinafter, referred to as a transistor). In this case, the passive matrix method is formed so that the anode and the cathode are orthogonal and the line is selected and driven, whereas the active matrix method connects a thin film transistor to each indium tin oxide (ITO) pixel electrode and a capacitor connected to the gate electrode of the thin film transistor. Drive according to the maintained voltage.

In order to structurally compensate subpixels of the organic light emitting display device, a 5T2C structure including five transistors and two capacitors is used. In the conventional subpixel structure, a power supply is cut off during writing in which the organic light emitting diode does not emit light and power is supplied to a light emitting step in which the organic light emitting diode emits light.

This method has a problem in that the amount of current flowing through the organic electroluminescent device changes according to the threshold voltage Vth variation in the subpixel. Thus, the 5T2C structure is used for the subpixel structure as described above in order to solve such a problem, but the structure has a complicated structure with four signal wires. A separate wiring was needed to synchronize the data signal and the gate voltage. Thus, the increase in power wiring located in the panel not only complicates the layout, but also inevitably adopts a complex driving method, which is difficult to realize high resolution and is not applicable to the actual panel.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to improve the sub-pixel structure of the organic light emitting display device to solve the problem of current reduction and luminance reduction of the organic light emitting diode due to the threshold voltage change of the driving transistor. In addition, the present invention provides an organic light emitting display device suitable for high resolution as well as improving display quality.

The present invention for solving the above problems includes a display panel in which subpixels connected to a plurality of first and second power supply wirings, scan wirings, and data wirings are positioned in a matrix, wherein the subpixels are gated to the scan wiring. Is connected to the first electrode and the first electrode is connected to the data line, the first transistor is connected to the first node, the gate is connected to the scan line located in the front end, the first electrode is connected to the second node and the third node A second transistor having a second electrode connected to the organic light emitting diode; an organic light emitting diode having a first electrode connected to the first power line; a first electrode connected to a second electrode of the organic light emitting diode; and a gate connected to the first node; A third transistor having a second electrode connected to the node, a fourth transistor having a gate connected to the second node, a first electrode connected to the third node, and a second electrode connected to the second power line, and a first transistor connected to the first node 1 electrode is connected An organic light emitting display device includes a first capacitor having a second electrode connected to a second node, and a second capacitor having a first electrode connected to a first node and a second electrode connected to a second power line.

The first, second, third and fourth transistors may be N-Mos type.

The first, second, third and fourth transistors may be a-Si transistors.

The subpixel may include a third power line, a fifth transistor having a first electrode connected to the third power line, a gate connected to a scan line positioned at the front end, and a second electrode connected to the first node.

The third power supply line may supply a reference voltage to the first electrode of the fifth transistor so as to perform negative bias annealing on the third and fourth transistors.

In another aspect, the present invention provides a method of driving an organic light emitting display device including a display panel in which subpixels including first, second, third, and fourth transistors, a capacitor, and an organic light emitting diode are positioned in a matrix form. A method, comprising: an initialization step of turning on a second transistor and turning on a first transistor, a sensing step of turning off a first transistor while the second transistor is turned on, and turning off a second transistor and turning on a first transistor; A write step of turning on the transistor to store data in the first and second capacitors; turning off the second transistor, turning off the first transistor, and using the data voltages stored in the first and second capacitors in the third and fourth capacitors. A method of driving an organic light emitting display device, the method comprising: turning on a transistor to emit an organic light emitting diode;

In the sensing step, the gate voltage of the third transistor may be sensed through the second transistor, and the data voltage to be stored in the first and second capacitors may be changed according to the sensed gate voltage of the third transistor.

In the sensing step, the sensing step may be performed while the second transistor is turned on, or the sensing step may be performed by turning on and then turning off the second transistor.

If the subpixel includes a fifth transistor for supplying a reference voltage, a negative bias for turning on the fifth transistor and supplying a reference voltage to the third and fourth transistors to restore threshold voltage characteristics of the third and fourth transistors. Negative Bias Anneal can be performed selectively.

As the timing at which the gate bias of the third and fourth transistors reaches the reference voltage can be set flexibly, when the period in which the negative bias annealing is performed varies, the degree of recovery of the threshold voltage characteristics of the third and fourth transistors can also be changed. have.

The reference voltage may be a negative voltage value of −4 [V] to −12 [V].

The initialization step may be performed so as not to overlap with the write step of storing the data voltage in the first and second capacitors.

The first, second, third and fourth transistors may be N-Mos type formed of a-Si.

First Embodiment

1 is a diagram illustrating a subpixel circuit of an organic light emitting display device according to a first embodiment.

Referring to FIG. 1, an organic light emitting display device according to a first embodiment of the present invention includes a plurality of first and second power supply wirings VDD and GND, a scan wiring SCAN1 [n], and a data wiring DATA [ n]) includes a display panel in which a subpixel (1pixel) connected in a matrix form is positioned.

Here, one subpixel 1pixel has a gate connected to the scan line SCAN1 [n], a first electrode connected to the data line DATA [n], and a second electrode connected to the first node A. It includes a first transistor (T1).

In addition, a second transistor having a gate connected to the scan line SCAN1 [n-1] positioned at the front end, a first electrode connected to the second node B, and a second electrode connected to the third node C T2).

In addition, the organic light emitting diode D may include an organic light emitting diode D connected to the first power line VDD, and the first electrode may be connected to the second electrode of the organic light emitting diode D, and the gate may be connected to the first node A. Is connected to the third node (C) includes a third transistor (T3) connected to the second electrode.

Also, a fourth transistor T4 includes a gate connected to the second node B, a first electrode connected to the third node C, and a second electrode connected to the second power line GND.

In addition, the first capacitor C1 is connected to the first node A and the second electrode is connected to the second node B, and the first electrode is connected to the first node A. The second capacitor C2 has a second electrode connected to the power line GND.

The first and second electrodes of the first, second, third and fourth transistors T1, T2, T3, and T4 described above may be selected as a source and a drain or a drain and a source electrode, respectively. It may be an N-Mos type transistor formed of Si (Amorphous Silicon). In addition, the first electrode and the second electrode of the organic light emitting diode D may also be selected as an anode and a cathode or a cathode and an anode, respectively, according to the subpixel circuit configuration.

The organic light emitting diode (D) includes an organic light emitting layer (EML) interposed between a common film such as a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). .

In such a circuit configuration, the first power line VDD may be commonly connected to the subpixels positioned in a matrix form or may be divided and connected to each of R, G, and B subpixels. That is, all of the sub pixels can be supplied with the same power through the first power line VDD, or different power can be supplied for each of the R, G, and B sub pixels.

Meanwhile, in the sub-pixel circuit including 4 transistors 2 capacitors (4T2C) as in the present invention, the third transistor T3 and the fourth transistor T4, which are some transistors, are saturated by the current scaling. The fourth transistor T4 may be driven in the saturation region, and the fourth transistor T4 may be driven in the linear region. The supplementary description thereof will be described in more detail in the following driving method.

For reference, the organic light emitting display device as described above supplies power to the plurality of first and second power lines VDD and GND positioned on the display panel, and supplies a scan signal to the scan line SCAN1 [n]. When the data signal is supplied to the data line DATA [n], the sub-pixel selected by the scan line SCAN1 [n] emits light to implement an image on the display panel.

Here, the first and second power supply wirings VDD and GND are referred to as "VDD" and "GND" in the description of the description, but the power supplied to the first and second power supply wirings VDD and GND has a mutual voltage difference. Of course, it can be based on the positive or negative power level supplied.

The apparatus for supplying power and signals for driving to the first and second power wirings VDD and GND, the scan wiring SCAN1 [n], and the data wiring DATA [n] described above may be a display panel or an external display panel. It may be selectively positioned on the back.

Such devices may generally include a power supply unit supplying power, a scan driver supplying a scan signal, a data driver supplying a data signal, and the like. These devices are driven in cooperation with a memory unit and a timing controller for storing an image signal supplied from the outside.

Hereinafter, a driving method of an organic light emitting display device according to a first embodiment of the present invention will be described with reference to FIG. 2.

2 is an exemplary view of a drive waveform according to the first embodiment of the present invention.

As described with reference to FIG. 1, the display panel of the organic light emitting display device according to the first embodiment of the present invention includes the first, second, third and fourth transistors T1, T2, T3, and T4. And the subpixels including the second capacitors C1 and C2 and the organic light emitting diode D are disposed in a matrix form.

2, the driving method according to the first embodiment of the present invention may include an initialization step (Reset), a sensing step (Vth Sensing), a writing step (Writing), and an emission step (Emission). ).

First, an initialization step (Reset) is a step of turning on the second transistor (T2) and turn on the first transistor (T1).

In the reset step, the scan signal Scan [n-1] output from the scan driver is located in the n-1 th position through the scan wire SCAN [n-1] in the n-1 th position. When supplied to, the second transistor T2 is turned on. In addition, when the scan signal Scan [n] output from the scan driver is supplied to the nth subpixel through the nth scan line SCAN [n], the first transistor T1 is supplied. Turn on.

Then, the remaining amount of data voltages remaining in the first and second capacitors C1 and C2 of the nth pixel located through the turned on first and second transistors T1 and T2 are removed to be positioned at the nth position. Sub-pixels can be initialized. Here, the remaining amount of data voltage remaining in the first and second capacitors C1 and C2 also includes the remaining amount of parasitic capacitance component in the wiring located in the corresponding subpixel.

Subsequently, the sensing step Vth Sensing is a step of turning off the first transistor T1 while the second transistor T2 is turned on.

In the sensing step Vth Sensing, the scan signal Scan [n-1] supplied to the n-th subpixel while maintaining the scan signal Scan [n-1] supplied to the nth-th subpixel is maintained. ]).

Then, the first transistor T1 is turned off while the second transistor T2 positioned in the nth position is turned on so that the threshold voltages Vth of the third and fourth transistors T3 and T4 can be detected. do. Here, the detection of the threshold voltage Vth of the third and fourth transistors T3 and T4 through the second transistor T2 may use the scan wiring SCAN [n-1] positioned in the n−1 th position. At this time, the detected threshold voltages Vth of the third and fourth transistors T3 and T4 are calculated to properly calculate the amount of data signal to be supplied. To this end, the data driver or the device interworking with the data driver may further include a device for processing the threshold voltage Vth sensed in the sensing step Vth sensing.

Meanwhile, as shown in FIG. 2, when the first transistor T1 is turned off to perform the sensing step (Vth Sensing), the second transistor T2 may be turned off for a predetermined time and then turned on again. Of course. Here, turning off the second transistor T2 for a predetermined time and turning it back on again detects the threshold voltages Vth of the third and fourth transistors T3 and T4 through the second transistor T2. It is to explain that it may be implemented.

Thereafter, the writing step is a step of turning off the second transistor T2 and turning on the first transistor T1 to store data in the first and second capacitors C1 and C2.

In the writing step, a current is supplied to the first and second capacitors C1 and C2 positioned in the n-th subpixel, so that the amount supplied to the capacities of the first and second capacitors C1 and C2 is equal to the voltage. , And storing the data voltage.

In the writing step, the second transistor T2 is turned off by scanning the scan signal Scan [n-1] supplied to the n-th subpixel to turn off the second transistor T2, and scanning the n-th subpixel. The signal Scan [n] is supplied to supply the data signal Data [n] output from the data driver to the n-th subpixel while the first transistor T1 is turned on.

Then, the data signal ata [n] is supplied to the first and second capacitors C1 and C2 through the first transistor T1 turned on in the nth subpixel, and the first and second capacitors C1 are provided. , C2 is stored as a data voltage by the amount of current corresponding to the supplied data signal Data [n].

Afterwards, the emission step includes turning off the second transistor T2, turning off the first transistor T1, and using third and fourth transistors with data voltages stored in the first and second capacitors C1 and C2. The organic light emitting diode D is emitted by turning on T3 and T4.

In the emission step, the third and fourth transistors T3 and T4 are turned on by the data voltages stored in the first and second capacitors C1 and C2, and are connected to the anode of the organic light emitting diode D. The power supplied to the first power line VDD flows to the second power line GND to emit light.

In more detail, the data voltages stored in the first and second capacitors C1 and C2 supply the gates with values greater than or equal to the threshold voltages Vth of the third and fourth transistors T3 and T4. Then, the third and fourth transistors T3 and T4 are turned on, and currents flow through the paths formed from the first power line VDD to the second power line GND by driving them. The light emitting diode D emits light.

In this process, the power supplied to the anode of the organic light emitting diode D through the first power line VDD may be supplied once in a pulse form only in the emission step as shown in the figure, and a logic high It is of course possible to take a state of continuously supplying power.

When a part of the driving method as described above is schematically illustrated in one frame, the driving waveform as shown in FIG. 3 can be illustrated.

3 is an exemplary view schematically showing the driving waveform of FIG. 2 in one frame.

As shown in FIG. 3, when the organic light emitting display device is driven, it can be seen that the initialization step is continuously performed on the remaining sub pixels except for the sub pixel to which the data signal is supplied in one frame.

The present invention can achieve the effect of restoring the transistor deterioration of the subpixel by supplying black data at the same time as performing the initialization step of initializing the data voltage supplied to the subpixel.

However, if the display panel is formed using the same subpixel structure as the first embodiment of the present invention, the problem caused by the threshold voltage Vth of the fourth transistor, which is a driving transistor for driving the organic light emitting diode, is shifted. You can compensate.

4 is a diagram illustrating a gate voltage of a fourth transistor included in a subpixel structure according to the first embodiment of the present invention, and FIG. 5 is an organic light emitting diode included in the subpixel structure according to the first embodiment of the present invention. Is a diagram showing a driving current.

In the case of the driving transistor included in the conventional subpixel structure, when the gate voltage is changed by the threshold voltage shift, the driving current reduction rate of the organic light emitting diode is generally large.

However, in the first exemplary embodiment of the present invention, even when the threshold voltage Vth of the fourth transistor, which is the driving transistor, is shifted and the gate voltage is changed, it can be seen that the width of the driving current reduction rate of the organic light emitting diode is small as shown in FIG. .

Second Embodiment

6 is a configuration diagram of a subpixel circuit of an organic light emitting display device according to a second embodiment.

Referring to FIG. 6, the organic light emitting display device according to the second exemplary embodiment of the present invention includes a plurality of first and second power supply lines VDD and GND, scan lines SCAN1 [n], and data lines DATA. and a display panel in which a subpixel (1pixel) connected to [n]) is positioned in a matrix.

However, one subpixel is similar to the first embodiment described above, but the first electrode is connected to the third power line REF [n] and the third power line REF [n], and n− A gate is connected to the first scan line SCAN [n-1] and includes a fifth transistor T5 having a second electrode connected to the first node A. Referring to FIG.

Here, the third power supply line REF [n] supplies a reference voltage to the first electrode of the fifth transistor T5 to perform negative bias annealing on the third and fourth transistors T3 and T4. do. The third power supply lines REF [n] for supplying the reference voltages may be commonly connected to supply the same reference voltages to all subpixels, or may be individually connected to supply different reference voltages.

Since other configurations are the same as those of the first embodiment described above, they will be omitted to avoid duplication of description.

On the other hand, the same structure as the second embodiment of the present invention has a feedback loop between the reference voltage supplied through the third power supply wiring REF [n] and the voltage by the data signal supplied through the data wiring DATA [n]. It is driven by forming a feedback loop.

As a result, optical feedback between the third transistor T3 and the fifth transistor T5 positioned in each subpixel is applied to the third and third transistors while the current flowing through the organic light emitting diode D is reduced. As all of the fourth transistors T3 and T4 are turned off, negative bias annealing can be performed on the third and fourth transistors T3 and T4.

Meanwhile, since the gate biases of the third and fourth transistors T3 and T4 in which the negative bias annealing is performed may be changed in a fluid manner, the reference voltages supplied thereto should be a fluid value rather than a fixed value. This will be described below with reference to FIGS. 7 to 9.

FIG. 7 is a graph of a photo current simulation of a transistor, FIG. 8 is a graph of average current increase according to a decrease in luminance efficiency of an organic light emitting diode, and FIG. 9 is a simulation graph of a negative bias anneal.

First, referring to FIG. 7, it can be seen that the transistor is affected by the photo current received at the gate as the organic light emitting diode D emits light. As an example, the transistor at the time of simulation is W / L = 23/5. Here, the effects of the transistors L1 to L4 generated as the organic light emitting diode D emits light in terms of Vgs [V] and Ids [A] are as follows: " L1 < L2 < L3 < L4.

In addition, the influence of FIG. 7 affects the current Ioled flowing through the organic light emitting diode D as shown in FIG. 8, thereby increasing the average current of the organic light emitting diode D. .

As described with reference to FIGS. 7 and 8, it can be seen that the average current of the transistor is changed by the amount of light fed back from the organic light emitting diode (D). Here, the transistor whose average current changes will be the third and fourth transistors T3 and T4 for driving the organic light emitting diode D, and the fourth transistor T4 will be most affected. .

Referring to FIG. 9, the organic light emitting diode D may change fluidly, such as “ta”, “tb”, “tc”, “td”, and the like, as described above. In addition, the bias applied to the gates of the third and fourth transistors T3 and T4 is also changed flexibly such as "t1", "t2", "t3", and "t4", so that the width of the negative bias annealing section may vary. will be.

Accordingly, the third and fourth transistors T3 and T4 subject to the negative bias annealing can perform a flexible negative bias annealing to estimate the degree of recovery due to the shift of the threshold voltage Vth, as well as image sticking ( Problems such as Image Sticking can be solved.

On the other hand, the organic light emitting display device as the second embodiment of the present invention, like the organic light emitting display device according to the first embodiment described above, the first, second, third, fourth and fifth transistors (T1, The first electrode and the second electrode of T2, T3, T4, and T5 may be selected as a source and a drain or a drain and a source electrode, respectively, which may be N-Mos transistors formed of a-Si (amorphous silicon). have. In addition, the first electrode and the second electrode of the organic light emitting diode D may also be selected as an anode and a cathode or a cathode and an anode, respectively, according to the subpixel circuit configuration.

In addition, the organic light emitting diode (D) has an organic light emitting layer (EML) interposed between a common film such as a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL) and an electron injection layer (EIL). Include.

In this circuit configuration, the first power line VDD may be commonly connected to subpixels positioned in a matrix, or may be divided and connected to R, G, and B subpixels. That is, all of the sub pixels can be supplied with the same power through the first power line VDD, or different power can be supplied for each of the R, G, and B sub pixels.

In the sub-pixel circuit including 5 Transistor 2 Capacitors (5T2C), the third transistor T3 and the fourth transistor T4, which are some transistors, are saturated by current scaling. ) And the fourth transistor T4 can be driven in the linear region. The supplementary description thereof will be described in more detail in the following driving method.

For reference, the organic light emitting display device as described above supplies power to the plurality of first and second power lines VDD and GND positioned on the display panel, and supplies a scan signal to the scan line SCAN1 [n]. When the data signal is supplied to the data line DATA [n], the sub-pixel selected by the scan line SCAN1 [n] emits light to implement an image on the display panel.

Here, the first and second power supply wirings VDD and GND are referred to as "VDD" and "GND" in the description of the description, but the power supplied to the first and second power supply wirings VDD and GND has a mutual voltage difference. Of course, it can be based on the positive or negative power level supplied.

The apparatus for supplying power and signals for driving to the first and second power wirings VDD and GND, the scan wiring SCAN1 [n], and the data wiring DATA [n] described above may be a display panel or an external display panel. It may be selectively positioned on the back.

Such devices may generally include a power supply unit supplying power, a scan driver supplying a scan signal, a data driver supplying a data signal, and the like. These devices are driven in cooperation with a memory unit and a timing controller for storing an image signal supplied from the outside.

Hereinafter, a driving method of an organic light emitting display device according to a second embodiment of the present invention will be described with reference to FIG. 10.

10 is an exemplary view of a drive waveform according to a second embodiment of the present invention.

As described with reference to FIG. 6, the display panel of the organic light emitting display device according to the second exemplary embodiment of the present invention includes first, second, third, fourth and fifth transistors T1, T2, T3, T4, A subpixel including T5), capacitors C1 and C2, and an organic light emitting diode D is positioned in a matrix form.

10, the driving method according to the second embodiment of the present invention includes an initialization step (Reset), a sensing step (Vth Sensing), a writing step (Writing), and an emission step (Emission). ).

First, the initialization step (Reset) to turn on the second transistor (T2), turn on the first transistor (T1) to perform the initialization step, and to turn on the fifth transistor (T5) and the reference voltage (-Ref [ n]) is provided to the third and fourth transistors T3 and T4 to selectively select the negative bias anneal to restore the threshold voltage Vth characteristics of the third and fourth transistors T3 and T4. Step to perform.

Here, the gate biases of the third and fourth transistors T3 and T4 on which the negative bias annealing is performed may vary in flow. Therefore, the reference voltage (-Ref [n]) supplied to them should be a floating value rather than a fixed value. For example, the reference voltage -Ref [n] used when performing negative bias annealing may supply a negative voltage value of −4 [V] to −12 [V], but is not limited thereto.

In the initialization step, a substantial initialization step and a negative bias anneal may be selectively performed.

When performing the initialization step (Reset), the scan signal Scan [n-1] output from the scan driver is located at the n-1 th position via the scan wire SCAN [n-1] at the n-1 th position. When supplied to the subpixel, the second transistor T2 is turned on. In addition, when the scan signal Scan [n] output from the scan driver is supplied to the nth subpixel through the nth scan line SCAN [n], the first transistor T1 is supplied. Turn on.

Then, the remaining amount of data voltages remaining in the first and second capacitors C1 and C2 of the nth pixel located through the turned on first and second transistors T1 and T2 are removed to be positioned at the nth position. Sub-pixels can be initialized. Here, the remaining amount of data voltage remaining in the first and second capacitors C1 and C2 also includes the remaining amount of parasitic capacitance component in the wiring located in the corresponding subpixel.

When performing the negative bias annealing, the fifth signal is turned on by the scan signal Scan [n-1] supplied through the scan wire SCAN [n-1] positioned in the n-1th stage of the initialization step Reset. Transistor T5 is used.

Here, when the fifth transistor T5 is turned on, the reference voltage -Ref [n] output from the power supply unit or the like is supplied to the fifth transistor T5 through the third power supply line REF [n], and eventually, It is supplied to the gates of the third and fourth transistors T3 and T4. At this time, the supplied reference voltage (-Ref [n]) is supplied with a negative voltage value as shown in the figure to restore the negative voltage Vth characteristics of the third and fourth transistors T3 and T4. (Negative Bias Anneal) can be performed.

Subsequently, the sensing step Vth Sensing is a step of turning off the first transistor T1 while the second transistor T2 is turned on.

In the sensing step Vth Sensing, the scan signal Scan [n-1] supplied to the n-th subpixel while maintaining the scan signal Scan [n-1] supplied to the nth-th subpixel is maintained. ]).

Then, the first transistor T1 is turned off while the second transistor T2 positioned in the nth position is turned on so that the threshold voltages Vth of the third and fourth transistors T3 and T4 can be detected. do. Here, the detection of the threshold voltage Vth of the third and fourth transistors T3 and T4 through the second transistor T2 may use the scan wiring SCAN [n-1] positioned in the n−1 th position. At this time, the detected threshold voltages Vth of the third and fourth transistors T3 and T4 are calculated to properly calculate the amount of data signal to be supplied. To this end, a device for processing the threshold voltage Vth detected in the sensing step Vth Sensing should be further provided in the data driver or the device interworking with the data driver.

On the other hand, when the first transistor T1 is turned off to perform the sensing step (Vth Sensing), as shown in FIG. 2 of the first embodiment described above, the second transistor T2 is turned off for a predetermined time and then turned again. Of course, it can be carried out in a warm state. Here, turning off the second transistor T2 for a predetermined time and turning it back on again detects the threshold voltages Vth of the third and fourth transistors T3 and T4 through the second transistor T2. It is to explain that it may be implemented.

Thereafter, the writing step is a step of turning off the second transistor T2 and turning on the first transistor T1 to store data in the first and second capacitors C1 and C2.

In the writing step, a current is supplied to the first and second capacitors C1 and C2 positioned in the n-th subpixel, so that the amount supplied to the capacities of the first and second capacitors C1 and C2 is equal to the voltage. , And storing the data voltage.

In the writing step, the second transistor T2 is turned off by scanning the scan signal Scan [n-1] supplied to the n-th subpixel to turn off the second transistor T2, and scanning the n-th subpixel. The signal Scan [n] is supplied to supply the data signal Data [n] output from the data driver to the n-th subpixel while the first transistor T1 is turned on.

Then, the data signal ata [n] is supplied to the first and second capacitors C1 and C2 through the first transistor T1 turned on in the nth subpixel, and the first and second capacitors are provided. C1 and C2 store the data voltage by the amount of current corresponding to the supplied data signal Data [n].

Afterwards, the emission step includes turning off the second transistor T2, turning off the first transistor T1, and using third and fourth transistors with data voltages stored in the first and second capacitors C1 and C2. The organic light emitting diode D is emitted by turning on T3 and T4.

In the emission step, the third and fourth transistors T3 and T4 are turned on by the data voltages stored in the first and second capacitors C1 and C2, and are connected to the anode of the organic light emitting diode D. The power supplied to the first power line VDD flows to the second power line GND to emit light.

In more detail, the data voltages stored in the first and second capacitors C1 and C2 supply the gates with values greater than or equal to the threshold voltages Vth of the third and fourth transistors T3 and T4. Then, the third and fourth transistors T3 and T4 are turned on, and currents flow through the paths formed from the first power line VDD to the second power line GND by driving them. The light emitting diode D emits light.

In this process, the power supplied to the anode of the organic light emitting diode D through the first power line VDD may be supplied once in a pulse form only in the emission step as shown in the figure, and a logic high It is of course possible to take a state of continuously supplying power.

The organic light emitting display device according to the first and second embodiments of the present invention improves the sub pixel structure to solve the problem of current reduction and luminance reduction of the organic light emitting diode due to the change of the threshold voltage of the driving transistor. In addition, there is an effect of improving the display quality and of providing an organic light emitting display device suitable for high resolution.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

As described above, the present invention improves the subpixel structure of the organic light emitting display device, thereby reducing the current caused by the threshold voltage change of the driving transistor and reducing the luminance of the organic light emitting diode. In addition, there is an effect of improving the display quality and of providing an organic light emitting display device suitable for high resolution.

Claims (13)

And a display panel in which subpixels connected to the plurality of first and second power lines, scan lines, and data lines are positioned in a matrix form. The sub pixel is, A first transistor having a gate connected to the scan line, a first electrode connected to the data line, and a second electrode connected to the first node, and a gate connected to the scan line located at the front end, and a first electrode connected to the second node. A second transistor connected to the second node and a second electrode connected to the third node, an organic light emitting diode having a first electrode connected to the first power line, and a first electrode connected to the second electrode of the organic light emitting diode; A third transistor having a gate connected to one node and a second electrode connected to a third node, a gate connected to the second node, a first electrode connected to the third node, and a second electrode connected to the second power line The fourth transistor connected to the first node, a first capacitor connected to the first node, and a second electrode connected to the second node; a first electrode connected to the first node, and connected to the second power line. A second capacitor connected to a second electrode The organic light emitting display device including an emitter. The method of claim 1, The first, second, third and fourth transistors, N-Mos type organic light emitting display device. The method of claim 1, The first, second, third and fourth transistors, An organic light emitting display device which is an a-Si transistor. The method of claim 1, The sub pixel may include a third power supply wire, And a fifth transistor having a first electrode connected to the third power line, a gate connected to a scan line positioned at the front end, and a second transistor connected to the first node. The method of claim 4, wherein The third power supply wiring, And a reference voltage supplied to the first electrode of the fifth transistor so as to perform negative bias annealing on the third and fourth transistors. A method of driving an organic light emitting display device, comprising: a display panel in which subpixels including first, second, third, and fourth transistors, a capacitor, and an organic light emitting diode are positioned in a matrix form; An initialization step of turning on the second transistor and turning on the first transistor; A sensing step of turning off the first transistor while the second transistor is turned on; A write step of turning off the second transistor and turning on the first transistor to store data in the first and second capacitors; And turning off the second transistor, turning off the first transistor, and turning on the third and fourth transistors with data voltages stored in the first and second capacitors, thereby emitting the organic light emitting diodes. A method of driving an organic light emitting display device. The method of claim 6, In the sensing step, And a method of sensing the gate voltage of the third transistor through the second transistor and varying data voltages to be stored in the first and second capacitors according to the sensed gate voltage of the third transistor. The method of claim 6, In the sensing step, And performing the sensing step in the state where the second transistor is turned on, or turning on and then turning off the second transistor to perform the sensing step. The method of claim 6, When the fifth transistor for supplying a reference voltage to the sub pixel is included, In the initializing step, a negative bias anneal that selectively turns on the fifth transistor and supplies the reference voltage to the third and fourth transistors to restore threshold voltage characteristics of the third and fourth transistors. Method of driving an organic light emitting display device performed by. The method of claim 9, As the timing at which the gate bias of the third and fourth transistors reaches the reference voltage becomes fluid, when the period in which the negative bias annealing is performed is changed, the degree of recovery of threshold voltage characteristics of the third and fourth transistors is also changed. A method of driving an organic light emitting display device. The method of claim 9, And the reference voltage is a negative voltage value of -4 [V] to-12 [V]. The method of claim 6, The initialization step, And a method of driving the organic light emitting display device so as not to overlap with the write step of storing data voltages in the first and second capacitors. The method of claim 6, The first, second, third and fourth transistors, A method of driving an N-Mos type organic light emitting display device formed of a-Si.

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