KR20090002439A - Device isolation film of semiconductor device and method for forming the same - Google Patents
Device isolation film of semiconductor device and method for forming the same Download PDFInfo
- Publication number
- KR20090002439A KR20090002439A KR1020070065772A KR20070065772A KR20090002439A KR 20090002439 A KR20090002439 A KR 20090002439A KR 1020070065772 A KR1020070065772 A KR 1020070065772A KR 20070065772 A KR20070065772 A KR 20070065772A KR 20090002439 A KR20090002439 A KR 20090002439A
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- South Korea
- Prior art keywords
- film
- sod
- active region
- layer
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000002955 isolation Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 abstract description 11
- 238000007254 oxidation reaction Methods 0.000 abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000011810 insulating material Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
1A to 1F are cross-sectional views illustrating a device isolation film and a method of forming the semiconductor device according to the present invention.
The present invention relates to a device isolation film of a semiconductor device and a method of forming the same. In order to solve the problem that the process margin for forming the device isolation film is gradually reduced and thus the active region is damaged, the device isolation film having an STI structure is formed using an SOD film. The present invention relates to a technique of forming a stacked structure of a first SOD film, an insulating film, and a second SOD film to prevent oxidation of an active region by the SOD film and to improve gap fill characteristics of the device isolation film.
In order to increase the integration of devices in terms of high integration, it is necessary to reduce each device dimension, and to reduce the width and area of device isolation regions existing between devices. It can be said that the device isolation technology determines the cell size of the semiconductor device in that it determines the size of the semiconductor device.
Conventional methods for manufacturing device isolation films include LOCOS (LOCOS: LOCOS) method of insulating material isolation method, a structure having a structure in which an oxide film, a polysilicon layer, and a nitride film are stacked on a silicon substrate. Poly-Buffed LOCOS (hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in a substrate, and the like.
Here, when the device isolation film is formed by the LOCOS method, a miniaturization process is difficult, and there is a problem in that the device cannot be completely electrically separated by the LOCOS device isolation film alone.
In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. In addition, due to the polysilicon layer on the top of the substrate, the device isolation film formed inside the substrate during field oxidation is relatively smaller than that of the ride method, thereby reducing the reliability compared to the ride method.
The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is difficult by forming a convex device isolation layer on the semiconductor substrate and having a step.
In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, an insulating material is embedded in the trench, and then the upper surface is planarized using a CMP method and the subsequent process can be easily performed. It was.
Such a method is referred to as a shallow trench isolation (STI) process, and a high-density plasma (HDP) oxide film is embedded in the trench to improve device isolation.
However, as the device isolation film using the STI process is more integrated with the semiconductor device, the gap fill margin of filling the oxide film into the trench is gradually reduced.
In addition, a jaw phenomenon occurs in which the HDP oxide layer located at the boundary between the device isolation layer and the active region, which is a semiconductor substrate, is etched into the trench. Such a problem is called a moat, and the moiety oxidizes the active region and degrades the electrical characteristics of the gate. Therefore, not only the subsequent process is difficult but also a problem arises in that the leakage current of the semiconductor substrate is caused to degrade the characteristics and reliability of the semiconductor device.
According to the present invention, a device isolation film having an STI structure is formed by using an SOD film, but a stacked structure of a first SOD film, an insulating film, and a second SOD film is used to prevent oxidation of an active region by the SOD film and to provide gap fill characteristics of the device isolation film. It is an object of the present invention to provide a device isolation film of a semiconductor device and a method of forming the same, which can improve the efficiency of the semiconductor device and increase the margin of the semiconductor device formation process and improve the reliability of the device.
The device isolation film of the semiconductor device according to the present invention
A trench for forming shallow trench isolation (STI) defining an active region,
A first spin on dielectric (SOD) film embedded in a bottom of the trench;
An insulating film provided on the first SOD film and on sidewalls of the active region;
And a second SOD layer disposed on the insulating layer to completely fill the trench.
The method may further include a well oxide film, a liner nitride, and a liner oxide formed on sidewalls of the active region, wherein the insulating film is a nitride film. The thickness of the insulating film is characterized in that 20 ~ 200Å.
In addition, the device isolation film forming method of a semiconductor device according to the present invention
Forming a trench for forming shallow trench isolation (STI) defining an active region in the semiconductor substrate,
Forming a first spin on dielectric (SOD) film over the semiconductor substrate including the trench;
Etching back the first SOD layer to expose an upper portion of the active region;
Forming an insulating film on sidewalls of the exposed active region and on a surface of the first SOD film; and
And filling the trench by forming a second SOD layer over the insulating layer.
Here, a well oxide, a liner nitride, and a liner oxide may be further formed on sidewalls of the active region, and the first SOD layer may have a thickness of 3000 to 7000 kPa. The method may further include performing a curing heat treatment process on the first SOD layer, wherein the etch back process is performed when the active region is exposed by a thickness of 200 to 1500Å from an upper surface. Characterized in that the heat treatment process to the first SOD film after the etch back process, characterized in that the insulating film is formed to a thickness of 20 ~ 200Å.
Hereinafter, a semiconductor device and a method for forming the same according to the present invention will be described in detail with reference to the accompanying drawings.
1A to 1F are cross-sectional views illustrating a device isolation film and a method of forming the semiconductor device according to the present invention.
Referring to FIG. 1A, the
Next, the
Next, a well oxide, a liner nitride, and a liner oxide film are formed on the sidewalls of the hard mask pattern and the surface of the
Next, the
Thereafter, the first SOD
Referring to FIG. 1B, an etch back process is performed until the upper portion of the
Next, the remaining
Referring to FIG. 1C, an
There is a risk that the -OH group of the first SOD layer oxidizes the active region during the heat treatment process. The liner nitride layer is thin, and in particular, the liner nitride layer on the upper portion of the
In this case, since the insulating
Referring to FIG. 1D, a
Next, as in the
Referring to FIG. 1E, the
Next, the
Subsequently, an element isolation film having a structure of the
Next, in order to densify the device isolation layer, a heat treatment process is performed once again in an N 2 atmosphere.
Referring to FIG. 1F, a
Next, the
Next, a
As described above, the device isolation film of the semiconductor device and the method for forming the semiconductor device according to the present invention are formed by using a SOD film, the device isolation film of the STI structure, by forming a stacked structure of the first SOD film, the insulating film and the second SOD film, SOD The oxidation of the active region by the film can be prevented and the gap fill property of the device isolation film can be improved.
As described above, the device isolation film of the semiconductor device and the method of forming the same according to the present invention are formed by using an SOD film, and forming a device isolation film having a stacked structure of a first SOD film, an insulating film, and a second SOD film. The oxidation of the active region by the SOD film can be prevented and the gap fill property of the device isolation film can be improved. Therefore, it provides an effect of increasing the margin of the process of forming a semiconductor device and improve the reliability of the device.
In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
Claims (11)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070065772A KR20090002439A (en) | 2007-06-29 | 2007-06-29 | Device isolation film of semiconductor device and method for forming the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070065772A KR20090002439A (en) | 2007-06-29 | 2007-06-29 | Device isolation film of semiconductor device and method for forming the same |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20090002439A true KR20090002439A (en) | 2009-01-09 |
Family
ID=40485436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070065772A KR20090002439A (en) | 2007-06-29 | 2007-06-29 | Device isolation film of semiconductor device and method for forming the same |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20090002439A (en) |
-
2007
- 2007-06-29 KR KR1020070065772A patent/KR20090002439A/en not_active Application Discontinuation
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