KR20090002439A - Device isolation film of semiconductor device and method for forming the same - Google Patents

Device isolation film of semiconductor device and method for forming the same Download PDF

Info

Publication number
KR20090002439A
KR20090002439A KR1020070065772A KR20070065772A KR20090002439A KR 20090002439 A KR20090002439 A KR 20090002439A KR 1020070065772 A KR1020070065772 A KR 1020070065772A KR 20070065772 A KR20070065772 A KR 20070065772A KR 20090002439 A KR20090002439 A KR 20090002439A
Authority
KR
South Korea
Prior art keywords
film
sod
active region
layer
forming
Prior art date
Application number
KR1020070065772A
Other languages
Korean (ko)
Inventor
장효식
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070065772A priority Critical patent/KR20090002439A/en
Publication of KR20090002439A publication Critical patent/KR20090002439A/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A device isolation film of a semiconductor device and a method for manufacturing the same are provided to improve a gap fill characteristic and to prevent oxidation of an active region by using an SOD(Spin On Dielectric) layer of a laminated structure. A trench(125) for forming an STI(Shallow Trench Isolation) defines an active region(120). A first SOD(Spin On Dielectric) film(135) is reclaimed to the bottom of the trench. An insulating layer is formed in the top of the first SOD film and a side wall of the active region. The insulating layer protects the upper part of the active region. The isolation layer prevents the oxidation of the active region and solves the moat problem. A second SOD film(150) is formed on an upper part of the insulating layer and completely reclaims the trench. After a gate oxidation film(160) is formed on the upper part of the front of a semiconductor substrate(100), a gate polysilicon layer(162), a gate metal layer(164) and a gate hard mask layer(166) are formed.

Description

DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

1A to 1F are cross-sectional views illustrating a device isolation film and a method of forming the semiconductor device according to the present invention.

The present invention relates to a device isolation film of a semiconductor device and a method of forming the same. In order to solve the problem that the process margin for forming the device isolation film is gradually reduced and thus the active region is damaged, the device isolation film having an STI structure is formed using an SOD film. The present invention relates to a technique of forming a stacked structure of a first SOD film, an insulating film, and a second SOD film to prevent oxidation of an active region by the SOD film and to improve gap fill characteristics of the device isolation film.

In order to increase the integration of devices in terms of high integration, it is necessary to reduce each device dimension, and to reduce the width and area of device isolation regions existing between devices. It can be said that the device isolation technology determines the cell size of the semiconductor device in that it determines the size of the semiconductor device.

Conventional methods for manufacturing device isolation films include LOCOS (LOCOS: LOCOS) method of insulating material isolation method, a structure having a structure in which an oxide film, a polysilicon layer, and a nitride film are stacked on a silicon substrate. Poly-Buffed LOCOS (hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in a substrate, and the like.

Here, when the device isolation film is formed by the LOCOS method, a miniaturization process is difficult, and there is a problem in that the device cannot be completely electrically separated by the LOCOS device isolation film alone.

In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. In addition, due to the polysilicon layer on the top of the substrate, the device isolation film formed inside the substrate during field oxidation is relatively smaller than that of the ride method, thereby reducing the reliability compared to the ride method.

The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is difficult by forming a convex device isolation layer on the semiconductor substrate and having a step.

In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, an insulating material is embedded in the trench, and then the upper surface is planarized using a CMP method and the subsequent process can be easily performed. It was.

Such a method is referred to as a shallow trench isolation (STI) process, and a high-density plasma (HDP) oxide film is embedded in the trench to improve device isolation.

However, as the device isolation film using the STI process is more integrated with the semiconductor device, the gap fill margin of filling the oxide film into the trench is gradually reduced.

In addition, a jaw phenomenon occurs in which the HDP oxide layer located at the boundary between the device isolation layer and the active region, which is a semiconductor substrate, is etched into the trench. Such a problem is called a moat, and the moiety oxidizes the active region and degrades the electrical characteristics of the gate. Therefore, not only the subsequent process is difficult but also a problem arises in that the leakage current of the semiconductor substrate is caused to degrade the characteristics and reliability of the semiconductor device.

According to the present invention, a device isolation film having an STI structure is formed by using an SOD film, but a stacked structure of a first SOD film, an insulating film, and a second SOD film is used to prevent oxidation of an active region by the SOD film and to provide gap fill characteristics of the device isolation film. It is an object of the present invention to provide a device isolation film of a semiconductor device and a method of forming the same, which can improve the efficiency of the semiconductor device and increase the margin of the semiconductor device formation process and improve the reliability of the device.

The device isolation film of the semiconductor device according to the present invention

A trench for forming shallow trench isolation (STI) defining an active region,

A first spin on dielectric (SOD) film embedded in a bottom of the trench;

An insulating film provided on the first SOD film and on sidewalls of the active region;

And a second SOD layer disposed on the insulating layer to completely fill the trench.

The method may further include a well oxide film, a liner nitride, and a liner oxide formed on sidewalls of the active region, wherein the insulating film is a nitride film. The thickness of the insulating film is characterized in that 20 ~ 200Å.

In addition, the device isolation film forming method of a semiconductor device according to the present invention

Forming a trench for forming shallow trench isolation (STI) defining an active region in the semiconductor substrate,

Forming a first spin on dielectric (SOD) film over the semiconductor substrate including the trench;

Etching back the first SOD layer to expose an upper portion of the active region;

Forming an insulating film on sidewalls of the exposed active region and on a surface of the first SOD film; and

And filling the trench by forming a second SOD layer over the insulating layer.

Here, a well oxide, a liner nitride, and a liner oxide may be further formed on sidewalls of the active region, and the first SOD layer may have a thickness of 3000 to 7000 kPa. The method may further include performing a curing heat treatment process on the first SOD layer, wherein the etch back process is performed when the active region is exposed by a thickness of 200 to 1500Å from an upper surface. Characterized in that the heat treatment process to the first SOD film after the etch back process, characterized in that the insulating film is formed to a thickness of 20 ~ 200Å.

Hereinafter, a semiconductor device and a method for forming the same according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a device isolation film and a method of forming the semiconductor device according to the present invention.

Referring to FIG. 1A, the pad oxide film 110 and the pad nitride film 115 are sequentially formed on the semiconductor substrate 100, and the pad nitride film 115 and the pad oxide film are formed using a mask defining the active region 120. The 110 is etched to form a hard mask pattern.

Next, the semiconductor substrate 100 is etched using the hard mask pattern as an etch mask to form trenches 125 for forming shallow trench isolation (STI).

Next, a well oxide, a liner nitride, and a liner oxide film are formed on the sidewalls of the hard mask pattern and the surface of the trench 125 provided with the pad oxide film 130 and the pad nitride film 140. A barrier film 130 is formed. Here, the barrier layer 130 serves to mitigate the impact applied to the sidewall of the active region when the device isolation layer is formed. The liner nitride film prevents out-diffusion of the well dopant, and the liner oxide film is applied for stress relaxation by the liner nitride film.

Next, the first SOD film 135 is formed on the entire surface of the semiconductor substrate 100. At this time, the first SOD film 135 is formed to a thickness of 3000 ~ 7000 Å.

Thereafter, the first SOD film 135 is cured.

Referring to FIG. 1B, an etch back process is performed until the upper portion of the active region 120 is exposed to reduce the height of the first SOD layer 135 and insulate the active region 120. In this case, it is preferable to perform an etch back process so that the exposed active region 120 is exposed to the thickness of 200 ~ 1500Å from the upper surface.

Next, the remaining first SOD film 135 is heat treated. At this time, the heat treatment temperature is preferably adjusted to 100 ~ 400 ℃ and carried out for 5 to 60 minutes. When the heat treatment process is performed as described above, the SOD film 135 is densified. In the heat treatment process, since the exposed portion of the first SOD film 135 is well densified and its efficiency decreases as it enters the inside, the heat treatment is preferably performed after the etch back.

Referring to FIG. 1C, an insulating layer 140 is formed on the entire surface of the semiconductor substrate 100. At this time, it is preferable to use a nitride film (Nitride) and the insulating film is formed to a thickness of 30 ~ 200Å.

There is a risk that the -OH group of the first SOD layer oxidizes the active region during the heat treatment process. The liner nitride layer is thin, and in particular, the liner nitride layer on the upper portion of the active region 120 loses the risk of causing oxidation of the active region 120. have.

In this case, since the insulating layer 140 protects the upper portion of the active region 120 which is a relatively weak portion in the device isolation layer forming process, the insulating layer 140 may prevent oxidation of the active region 120 and may solve the problem of generating a moat. .

Referring to FIG. 1D, a second SOD film 150 is formed on the entire surface of the semiconductor substrate 100. At this time, the second SOD film 150 is formed to a thickness of 3000 ~ 7000 Å.

Next, as in the first SOD film 135, a curing process is performed.

Referring to FIG. 1E, the pad nitride layer 115 is exposed by planarizing etching of the second SOD layer 150 by performing a chemical mechanical polishing (CMP) process.

Next, the pad nitride film 115 and the pad oxide film 110 are removed.

Subsequently, an element isolation film having a structure of the first SOD film 135, the insulating film 140, and the second SOD film 150 insulated from the active region 120 is formed using an etch back process or a CMP process.

Next, in order to densify the device isolation layer, a heat treatment process is performed once again in an N 2 atmosphere.

Referring to FIG. 1F, a gate oxide layer 160 is formed over the semiconductor substrate 100, and a gate polysilicon layer 162, a gate metal layer 164, and a gate hard mask layer 166 are formed thereon.

Next, the gate 170 is formed by sequentially etching the gate hard mask layer 166, the gate metal layer 164, the gate polysilicon layer 162, and the gate oxide layer 160 by an etching process using a gate mask.

Next, a gate spacer 168 is formed on the sidewall of the gate 170.

As described above, the device isolation film of the semiconductor device and the method for forming the semiconductor device according to the present invention are formed by using a SOD film, the device isolation film of the STI structure, by forming a stacked structure of the first SOD film, the insulating film and the second SOD film, SOD The oxidation of the active region by the film can be prevented and the gap fill property of the device isolation film can be improved.

As described above, the device isolation film of the semiconductor device and the method of forming the same according to the present invention are formed by using an SOD film, and forming a device isolation film having a stacked structure of a first SOD film, an insulating film, and a second SOD film. The oxidation of the active region by the SOD film can be prevented and the gap fill property of the device isolation film can be improved. Therefore, it provides an effect of increasing the margin of the process of forming a semiconductor device and improve the reliability of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (11)

A trench for forming shallow trench isolation (STI) defining an active region; A first spin on dielectric (SOD) film embedded in a bottom of the trench; An insulating layer provided on the first SOD layer and on sidewalls of the active region; And And a second SOD layer disposed over the insulating layer to completely fill the trench. The method of claim 1, The device isolation layer of claim 1, further comprising a well oxide, a liner nitride, and a liner oxide on the sidewalls of the active region. The method of claim 1, The insulating film is a device isolation film of a semiconductor device, characterized in that the nitride film. The method of claim 1, The isolation layer of the semiconductor device, characterized in that the thickness of the insulating film is 20 ~ 200Å. Forming a trench for forming shallow trench isolation (STI) defining an active region in the semiconductor substrate; Forming a first spin on dielectric (SOD) film over the semiconductor substrate including the trench; Etching back the first SOD layer to expose an upper portion of the active region; Forming an insulating film on sidewalls of the exposed active region and a surface of the first SOD film; And And forming a second SOD layer over the insulating layer to fill the trench. The method of claim 5, wherein And forming a well oxide, a liner nitride, and a liner oxide on the sidewalls of the active region. The method of claim 5, wherein The first SOD film is a device isolation film forming method of a semiconductor device, characterized in that formed to a thickness of 3000 ~ 7000Å. The method of claim 5, wherein And performing a curing heat treatment process on the first SOD film. The method of claim 5, wherein And the etch back process is performed until the active region is exposed to the thickness of 200 ~ 1500 ~ from the upper surface. The method of claim 5, wherein And a heat treatment process is performed on the first SOD film after the etch back process. The method of claim 10, And the insulating film is formed to a thickness of 20 ~ 200 소자.
KR1020070065772A 2007-06-29 2007-06-29 Device isolation film of semiconductor device and method for forming the same KR20090002439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070065772A KR20090002439A (en) 2007-06-29 2007-06-29 Device isolation film of semiconductor device and method for forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070065772A KR20090002439A (en) 2007-06-29 2007-06-29 Device isolation film of semiconductor device and method for forming the same

Publications (1)

Publication Number Publication Date
KR20090002439A true KR20090002439A (en) 2009-01-09

Family

ID=40485436

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070065772A KR20090002439A (en) 2007-06-29 2007-06-29 Device isolation film of semiconductor device and method for forming the same

Country Status (1)

Country Link
KR (1) KR20090002439A (en)

Similar Documents

Publication Publication Date Title
KR20020071063A (en) Dent free trench isolation structure and method for fabricating the same
US6544861B2 (en) Method for forming isolation trench
KR100458732B1 (en) Method For Manufacturing Semiconductor Devices
KR100703836B1 (en) Method for forming trench type isolation layer in semiconductor device
KR20120090544A (en) Semiconductor device and method for manufacturing the same
KR20090011947A (en) Method for manufacturing of isolation layer of semiconductor device
KR20090002439A (en) Device isolation film of semiconductor device and method for forming the same
KR100540340B1 (en) Method For Manufacturing Semiconductor Devices
KR100519648B1 (en) Method For Manufacturing Semiconductor Devices
KR100344765B1 (en) Method for isolating semiconductor devices
KR20100074668A (en) Manufacturing method for isolation structure of semiconductor device
KR20010061041A (en) Forming method for a field oxide of semiconductor device
KR20030001941A (en) Method For Manufacturing Semiconductor Devices
KR100517351B1 (en) Method for manufacturing device isolation barrier of semiconductor device
KR20080088680A (en) Method for forming shallow trench isolation of semiconductor device
KR100579962B1 (en) Method For Manufacturing Semiconductor Devices
KR100861311B1 (en) Method of manufacturing isolation layer for semiconductor device
KR20080062564A (en) Method for forming isolation layer of semiconductor device
KR20040103557A (en) Method for forming isolation in semiconductor device
KR20080086222A (en) Method for forming shallow trench isolation of semiconductor device
KR20080114065A (en) Method for manufacturing of isolation layer of semiconductor device
KR20040056201A (en) Method for forming isolation of semiconductor device
KR20040059278A (en) Method For Manufacturing Semiconductor Devices
KR20040044206A (en) Device isolation method in a semiconductor device
KR20020054666A (en) A method for forming a field oxide of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination